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 Table of Contents
DDR and HyperLynx Overview ................................................................................................ 11

Objectives ................................................................................................................................. 12

DDRx Basics ............................................................................................................................. 13

Source Synchronous Bus ......................................................................................................... 14

DRAM and DIMM ...................................................................................................................... 15

Unbuffered vs. Registered ........................................................................................................ 16

Rank vs. Side ............................................................................................................................ 17

Example: DIMM Density of 1G .................................................................................................. 18

Slots and Ranks ........................................................................................................................ 19

Fly-By Topology (DDR3/DDR4) ................................................................................................ 20

DDR4 Specific Architecture....................................................................................................... 21

Frequency vs. Bandwidth .......................................................................................................... 22

Data-rate vs. Frequency: Data .................................................................................................. 23

1T vs. 2T Timing ....................................................................................................................... 24

1T vs. 2T Timing Physical Implementation ............................................................................... 25

Data-rate vs. Frequency: Add/Cmd/Ctl ..................................................................................... 26

DDRx Basics: Signal Grouping ................................................................................................. 27

Write and Read Cycles ............................................................................................................. 28

AC and DC Thresholds ............................................................................................................. 29

DDR3 vs. DDR4 (SSTL vs. POD) Current Flow ........................................................................ 30

DDR3 vs. DDR4 Vcent Comparison ......................................................................................... 31

Input Threshold Comparison ..................................................................................................... 32

Average Vref – DDR4 Only ....................................................................................................... 33

Slew Rate Derating ................................................................................................................... 34

Write Leveling – Clock/Strobe (DDR3/4) ................................................................................... 35

Read Leveling (DDR4) .............................................................................................................. 36

HyperLynx DDRx Interface Analysis 3

 Table of Contents
On-Die Termination (ODT) – DDR3 .......................................................................................... 37

On-Die Termination (ODT) – DDR4 .......................................................................................... 38

On-Die Termination Settings DIMM Example (DDR3) .............................................................. 39

JEDEC Standard Topologies .................................................................................................... 40

Non-JEDEC Standard Topologies ............................................................................................ 41

Number of Memory Interfaces................................................................................................... 42

JEDEC Specification Numbers ................................................................................................. 43

Help & SupportNet .................................................................................................................... 44

DDRx Design Methodology Using HyperLynx........................................................................... 45

Fully Supported DDRx Topologies ............................................................................................ 46

INSTRUCTOR Demo – See notes ............................................................................................ 47

Lab 1 ......................................................................................................................................... 48

Preparing for the DDRx Wizard ............................................................................................... 49

Objectives ................................................................................................................................. 50

DDRx Wizard Overview - LineSim ............................................................................................ 51

Required Simulation for a DDRx Bus – LineSim ....................................................................... 52

INSTRUCTOR Demo – See notes ............................................................................................ 53

Single-Board Scenario .............................................................................................................. 54

INSTRUCTOR Demo – See notes ............................................................................................ 55

Multi-board Scenario ................................................................................................................. 56

INSTRUCTOR Demo – See notes ............................................................................................ 57

DDRx Wizard Overview – BoardSim ......................................................................................... 58

Required Simulation for a DDRx Bus – BoardSim .................................................................... 59

INSTRUCTOR Demo – See notes ............................................................................................ 60

Lab 2 ......................................................................................................................................... 64

Modeling DDRx Interfaces ....................................................................................................... 65

HyperLynx DDRx Interface Analysis 4

 Table of Contents
Objectives ................................................................................................................................. 66

Stackups in LineSim ................................................................................................................. 67

Vias in LineSim ......................................................................................................................... 69

INSTRUCTOR Demo – See notes ............................................................................................ 70

Physical Implementation ........................................................................................................... 72

INSTRUCTOR Demo – See notes ............................................................................................ 73

IBIS Models............................................................................................................................... 74

IBIS Model Requirements ......................................................................................................... 75

Power Aware IBIS Models ........................................................................................................ 79

INSTRUCTOR Demo – See notes ............................................................................................ 80

S-Parameters ............................................................................................................................ 81

S-Parameters: 2-Port Analytical Relationships ......................................................................... 82

S-Parameters – 2-Port Practical Perspective ............................................................................ 83

S-Parameter Quality Metrics ..................................................................................................... 84

INSTRUCTOR Demo – See notes ............................................................................................ 85

Timing Models........................................................................................................................... 86

DDR Data and Strobe Timing Parameters ................................................................................ 87

tCKACTiming Spec to Timing Model Example (Read/Write)..................................................... 88

tCKCTL Timing Spec to Timing Model Example (Read/Write) .................................................. 89

tCKDQS Timing Spec to Timing Model Example (Write) .......................................................... 90

tDQSDQ Timing Spec to Timing Model Example (Write) .......................................................... 91

tDS/tDH Timing Spec to Timing Model Example (Read) ........................................................... 92

Completed Table....................................................................................................................... 93

INSTRUCTOR Demo – See notes ............................................................................................ 94

Lab 3 ......................................................................................................................................... 95

Verify Interface/Model Setup ................................................................................................... 96

HyperLynx DDRx Interface Analysis 5

 Table of Contents
Objectives ................................................................................................................................. 97

Getting Ready for DDRx Wizard ............................................................................................... 98

LineSim: Know the Topologies of the Nets ............................................................................... 99

LineSim: Verify the Stackup .................................................................................................... 100

LineSim: Verify the Schematic ................................................................................................ 101

Verify the Probing Location ..................................................................................................... 102

INSTRUCTOR Demo – See notes .......................................................................................... 103

BoardSim: Getting Ready for DDRx Wizard............................................................................ 104

BoardSim: Verify the Design Data .......................................................................................... 105

BoardSim: Verify the Stackup ................................................................................................. 107

Verify the Probing Location ..................................................................................................... 108

INSTRUCTOR Demo – See notes .......................................................................................... 109

Lab 4 ....................................................................................................................................... 110

Running the DDRx Wizard ..................................................................................................... 111

Objectives ............................................................................................................................... 112

DDRx Wizard: Initialization...................................................................................................... 113

DDRx Wizard: Controller ......................................................................................................... 114

DDRx Wizard: DRAMs ............................................................................................................ 115

Simulating with Stacked Die DRAMs ...................................................................................... 116

INSTRUCTOR Demo – See notes .......................................................................................... 117

DDRx Wizard: IBIS Models ..................................................................................................... 118

DDRx Wizard: Nets to Simulate .............................................................................................. 119

DDRx Wizard: DRAM Signals ................................................................................................. 120

DDRx Wizard: Data Strobes ................................................................................................... 121

DDRx Wizard: Data Nets ........................................................................................................ 122

DDRx Wizard: Clock Nets ....................................................................................................... 123

HyperLynx DDRx Interface Analysis 6

 Table of Contents
DDRx Wizard: Addr/Comm Nets ............................................................................................. 124

DDRx Wizard: Control Nets .................................................................................................... 125

DDRx Wizard: Disable Nets .................................................................................................... 126

INSTRUCTOR Demo – See notes .......................................................................................... 127

DDRx Wizard: ODT Models .................................................................................................... 128

DDRx Wizard: ODT Behavior.................................................................................................. 129

DDRx Wizard: IBIS Model Selectors ....................................................................................... 130

DDRx Wizard: Timing Models ................................................................................................. 131

Custom Controller Model ........................................................................................................ 132

INSTRUCTOR Demo – See notes .......................................................................................... 133

Write Leveling (DDR3/4) – DQS to CLK ................................................................................. 134

Write Leveling Delay Calculation: DQS to CLK ....................................................................... 135

Write/Read Leveling – DQ to DQS.......................................................................................... 136

Write and Read Leveling Delay: DQ to DQS........................................................................... 137

Generating Write/Read Leveling Delay File ............................................................................ 138

Using the "…the table on this page" Option ............................................................................ 139

Using the "…the DDR3 Delays external file…" Option ............................................................ 140

INSTRUCTOR Demo – See notes .......................................................................................... 141

DDRx Wizard: Stimulus and Crosstalk .................................................................................... 142

Crosstalk in DDRx Wizard....................................................................................................... 143

INSTRUCTOR Demo – See notes .......................................................................................... 144

DDRx Wizard: Simulation Options .......................................................................................... 145

AC Thresholds Support (DDR3).............................................................................................. 146

DDRx Wizard: Quality Checks ................................................................................................ 148

INSTRUCTOR Demo – See notes .......................................................................................... 149

DDRx Wizard: Report Options ................................................................................................ 150

HyperLynx DDRx Interface Analysis 7

 Table of Contents
INSTRUCTOR Demo – See notes .......................................................................................... 151

DDR4 Timing and Voltage Verification .................................................................................... 152

Vref and Vcent Values ............................................................................................................ 153

In the DDR Wizard – Eye Mask "Time" Calibration ................................................................. 154

In the DDR Wizard – DRAM Vref ; "Voltage" Calibration ........................................................ 155

Vref for Controller (Read) ........................................................................................................ 156

Vref for Controller (Read) (Contd) ........................................................................................... 157

Data Bus Inversion – DDR4/LPDDR4 ..................................................................................... 158

Data Bus Inversion – DDR4/LPDDR4 Comparison................................................................. 159

Power Aware IBIS Models, Why? ........................................................................................... 160

Power Aware IBIS Models ...................................................................................................... 161

INSTRUCTOR Demo – See notes .......................................................................................... 162

DDRx Wizard: Simulate .......................................................................................................... 163

Common Setup Warnings – Voltage Range ........................................................................... 164

Common Setup Warnings – Inconsistent Diff Pins.................................................................. 165

Common Setup Warnings – Model Types .............................................................................. 166

Common Setup Warnings – Model Selector ........................................................................... 167

Common Setup Warnings – Receiver Thresholds .................................................................. 168

DDRx Wizard: Run Simulation ................................................................................................ 169

INSTRUCTOR Demo – See notes .......................................................................................... 170

DDRx Wizard Overview .......................................................................................................... 171

DDRx Simulation Results Folder; xls: DDR/2/3....................................................................... 172

DDRx Simulation Results Folder; HTML: DDR/2/3 ................................................................. 173

DDRx Simulation Results Folder; xls: DDR4........................................................................... 174

DDRx Simulation Results Folder; HTML: DDR4 ..................................................................... 175

INSTRUCTOR Demo – See notes .......................................................................................... 176

HyperLynx DDRx Interface Analysis 8

 Table of Contents
Constraint Derivation; Design Exploration .............................................................................. 177

Why Use the DDRx Batch Wizard in LineSim? ....................................................................... 178

INSTRUCTOR Demo – See notes .......................................................................................... 179

Creating LineSim Schematics for DDRx Wizard; Multi-Board ................................................. 181

Setting up DDRx Wizard for Simulation in LineSim................................................................. 182

INSTRUCTOR Demo – See notes .......................................................................................... 184

Lab 5 through 18 ..................................................................................................................... 185

HyperLynx® DDRx Interface Analysis .................................................................................. 186

Objectives ............................................................................................................................... 187

Quality Checks page ............................................................................................................... 188

Overshoot and Undershoot – ADD, CMD and CTL................................................................. 189

Overshoot and Undershoot – CLK, DQ, DQS, DM ................................................................. 190

Overshoot and Undershoot: (Report) ...................................................................................... 191

Monotonicity and VIH/L(AC/DC) Limit: (Report) ...................................................................... 192

Slew Rate: (Report) ................................................................................................................ 193

Differential SI Checks – VIHDiff/VILDiff (AC & DC) ................................................................. 194

Differential SI Checks – VIHDiff/VILDiff (AC & DC): (Report).................................................. 195

Differential SI Checks – Max VIX ............................................................................................ 196

Differential SI Checks – Max VIX: (Report) ............................................................................. 197

Differential SI Checks – Min VSEH/VSEL ............................................................................... 198

Differential SI Checks – Min VSEH/VSEL: (Report) ................................................................ 199

Differential SI Checks – tVAC/tDVAC ..................................................................................... 200

Differential SI Checks – tVAC/tDVAC: (Report) ...................................................................... 202

Check Round Trip Times Option ............................................................................................. 204

Round Trip Time Overview ..................................................................................................... 205

Syntax for RTT_limits.txt ......................................................................................................... 207

HyperLynx DDRx Interface Analysis 9

 Table of Contents
Round Trip Time: (Report) ...................................................................................................... 208

Round Trip Time1: (Report) .................................................................................................... 209

Round Trip Time2: (Report) .................................................................................................... 210

Jitter ........................................................................................................................................ 211

tJIT .......................................................................................................................................... 212

Total Jitter High/Low Pulse Abs Margin .................................................................................. 214

Total Jitter High/Low Pulse Avg Margin .................................................................................. 215

tERR ....................................................................................................................................... 217

tERR: Report........................................................................................................................... 218

HyperLynx DDRx Interface Analysis 10