1084 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 28, NO.
4, APRIL 2020
ER-TCAM: A Soft-Error-Resilient SRAM-Based Ternary
Content-Addressable Memory for FPGAs
Inayat Ullah , Member, IEEE , Joon-Sung Yang , Senior Member, IEEE , and Jaeyong Chung , Member, IEEE
Abstract— Static random access memory (SRAM)-based ternary
content-addressable memory (TCAM) on field-programmable gate arrays
(FPGAs) is used for packet classification in software-defined networking
(SDN) and OpenFlow applications. SRAMs implementing TCAM con-
tents constitute the major part of a TCAM design on FPGAs, which
are vulnerable to soft errors. The protection of SRAM-based TCAMs
against soft errors is challenging without compromising critical path delay
and maintaining a high search performance. This brief presents a low-
cost and low-response-time technique for the protection of SRAM-based
TCAMs. This technique uses simple, single-bit parity for fault detection
which has a minimal critical path overhead. This technique exploits
the binary-encoded TCAM table maintained in SRAM-based TCAMs
for update purposes to implement a low-response-time error-correction
mechanism at low cost. The error-correction process is carried out in the
background, allowing lookup operations to be performed simultaneously,
thus maintaining a high search performance. The proposed technique
provides protection against soft errors with a response time of 293 ns,
whereas maintaining a search rate of 222 million searches per second on
a 1024 × 40 size TCAM on Artix-7 FPGA.
Index Terms— Field-programmable gate array (FPGA), mem-
ory architecture, soft errors, static random access memory
(SRAM)-based ternary content-addressable memory (TCAM).
I. I NTRODUCTION
Content-addressable memory (CAM) allows the stored content to
be searched in parallel in a single cycle, achieving a high search
performance. A binary CAM stores and searches data in only two
states: “0” and “1,” whereas a ternary CAM (TCAM) represents data
in three different states: “0,” “1,” and do not care state “x.” TCAMs
are extensively used in network systems for packet classification and
filtering [1], [2].
Modern static random access memory (SRAM)-based field-
programmable gate array (FPGA) technology offers the flexibility
and reconfigurability with high performance required in software-
defined networking (SDN) and OpenFlow network accelerators for
big data [2].
Owing to the disturbances from high-energy neutron particles,
circuits on SRAM-based FPGAs are susceptible to single-event
upsets (SEUs) [3]. The on-chip embedded memory has been known
as the most vulnerable to SEUs in advanced process technologies
because of their increasingly small size and highly compact memory
cells [4], [5].
An SEU in embedded memory generates a transient error until the
corrupted data is overwritten [5]. SEUs can result in either single-bit
Manuscript received June 27, 2019; revised September 14, 2019 and
November 10, 2019; accepted December 17, 2019. Date of publication
February 20, 2020; date of current version March 20, 2020. This work
was supported by the Samsung Research Funding and Incubation Center of
Samsung Electronics under Project SRFC-TB1803-02. The EDA tools used
in this work were supported by IDEC, Daejeon, South Korea.
Inayat Ullah and Jaeyong Chung are with the Department of Electron-
ics Engineering, Incheon National University, Incheon 22012, South Korea
(e-mail: jychung@incheon.ac.kr).
Joon-Sung Yang is with the Department of Systems Semiconductor Engi-
neering, Yonsei University, Seoul, South Korea (e-mail: js.yang@yonsei.
ac.kr).
Color versions of one or more of the figures in this article are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TVLSI.2020.2968365
1063-8210 © 2020 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.
Authorized licensed use limited to: University of Canberra. Downloaded on April 28,2020 at 00:25:50 UTC from IEEE Xplore. Restrictions apply.
upsets (SBUs) or multiple-bit upsets (MBUs). Cuckoo hashing offers
a low-cost solution for implementing efficient binary CAMs on
FPGAs [6]. The TCAM function in most of the SRAM-based FPGA
solutions is defined by the content of the configured embedded mem-
ories [i.e., block RAM (BRAM), distributed RAM (distRAM)] [7],
and a transient error may lead to a false match/mismatch and returns
an incorrect match address. Accordingly, in the case of a soft error,
the affected word of SRAM should be overwritten to retrieve the cor-
rect matching information during lookups. However, the protection of
SRAM-based TCAM solutions is challenging without compromising
the critical path delay and maintaining high search performance.
This brief presents a low-cost, low-response time and easy for
integration technique for the protection of SRAM-enabled TCAMs
without compromising the search performance. The error detection
is carried out in a simple way using single-bit parity checking at
a minimal delay and logic overhead. The proposed error-correction
technique exploits the redundant binary-encoded TCAM table main-
tained in SRAM-based TCAM solutions for update purposes to
correct soft errors. It maintains a high search performance while
the proposed error-correction mechanism is carried out in the back-
ground, allowing search operations to be performed simultaneously.
The proposed error-correction technique has a low response time,
ensuring a faultless TCAM design for lookups, during the entire
(almost) processing time.
II. SRAM-B ASED TCAM ON FPGA S
On-chip SRAM memories in modern FPGAs are used for imple-
menting TCAM solutions. For example, a 1 × 1 TCAM can be
implemented using a 2 × 1 RAM such that the match knowledge
for the presence of a “0” TCAM state is represented by storing a “1”
at RAM[0], a value of “1” by storing a “1” at SRAM[1], and “x”
state by storing a “1” at both the SRAM[0] and SRAM[1] locations.
A C-bit TCAM pattern can be implemented using a 1-bit SRAM of
2C positions. The address of an SRAM represents the C-bit TCAM
pattern, whereas the words of the SRAM stores match/mismatch
information for each word of the TCAM table against all the possible
C-bit patterns. In this manner, a C-bit wide TCAM table of B words
can be implemented using a B bits wide SRAM of 2C positions.
Researchers divide the wide TCAM bit patterns into smaller
chunks as they do not scale well in terms of required memory
in SRAM-based TCAMs. The W -bit wide bit patterns of TCAM
with depth D are divided into smaller chunks of C bits and then
implemented using AND-cascaded 2C × D size SRAMs [8], [9]. This
is explained using a simplified implementation of an SRAM-based
TCAM shown in Fig. 1. The 4-bit patterns of a 4-word deep TCAM
are divided into two partitions of 4 × 2, which are then implemented
using the two 4 × 4 SRAMs shown in Fig. 1(b). Let us consider a
search key (1001) is applied for the search operation, the first two
bits (10) would access the third word of the first SRAM (1100) and
the last two bits (01) would access the second word of the second
SRAM (1001). The SRAM words read are ANDed to get the final
match result (1000) which represents a match for rule R0 .
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 28, NO. 4, APRIL 2020
Fig. 1. Simplified implementation of TCAM using SRAM. (a) 4 × 4 TCAM
table. (b) Implementing a 4 × 4 TCAM using two 4 × 4 SRAMs.
There are different solutions for implementing TCAM on
FPGAs [7]. The flip flops (FFs) available in the logic resources of
the FPGA are used for implementing small-size TCAMs [10], [11].
As mentioned before, existing FPGA-based TCAMs mostly employ
BRAM or distRAM [8], [9], [12]–[14]. Higher memory efficiency
is achieved when shallow SRAMs are used to design TCAMs [9].
The minimum depth limitation on the configuration of Xilinx BRAM
is 512, which implies that 9 bits of TCAM are implemented using
29 BRAM bits. Hence, the optimal configuration size of 18- and
36-kb size BRAMs is 512 × 36 and 512 × 72 for which the width of
the TCAM chunk is 9 bits [8], [9]. The distRAM-based TCAMs
configure the four 64-bit LUTRAMs available in SLICEMs as a
32 × 6 simple dual-port RAM [12], [15], thereby implementing
30 TCAM bits per SLICEM. This implies that 256 distRAM bits
are used to implement 30 bits of TCAM, and 8.53 distRAM bits
are utilized for a single-bit of TCAM. Hence, the optimal depth of
distRAM-based SRAMs is 32, for which the width of the TCAM
chunk is 5 bits. In practice, it is recommended to realize TCAM
using BRAMs, and utilizing LUTRAMs for implementing other parts
of the system [9], [14].
Generally, the TCAM designs that use more resources tend to be
more sensitive to soft errors. The breakdown of BRAMs, LUTRAMs,
and slice registers on a 28-nm FPGA device is 34%, 5%, and
1%, respectively, making SEUs in the smaller population much less
likely [16]. Thus, the TCAM architectures implemented in BRAMs
are more vulnerable to soft errors than others (distRAM-based and
SR-based). The rate at which soft errors occur is often measured in
terms of failures in time (FIT) and the real-time soft error rate per
event in the BRAMs of the FPGA device used in the experiments of
the proposed work Artix-7 is 73% ± 9% [17].
The wild-card state “x” enables the TCAM words to represent the
ranges. An input word might match several words when the ranges
of two or more words overlap. In the case of a match with multiple
words, the word with the lowest order is forwarded. It is mandatory
to arrange the TCAM words in an order list such that higher priority
words are stored in lower memory addresses [12], [18]. An update of
a TCAM word might change the priorities and entails a rearrangement
of the words in the TCAM table. During update operations, incoming
words for the search operations remain suspended as cannot be
matched correctly [1], [18]. Future networking systems like the SDN
and OpenFlow require frequent updates in the network switches [1],
[2]. State-of-the-art SRAM-based TCAM solutions on FPGAs update
a TCAM entry in the binary-encoded TCAM table which involves
multiple TCAM entry movements to maintain the order constraint,
further mapped onto SRAMs emulating the TCAM function [8],
[12], [13]. The proposed ER-TCAM exploits this system-level data
redundancy offered by the stored binary-encoded TCAM content to
correct soft errors in SRAMs emulating the TCAM function.
III. C HALLENGES OF SRAM-B ASED TCAM P ROTECTION
The protection of SRAM memories defining the TCAM function
is necessary as they make the major proportion of the design and are
Authorized licensed use limited to: University of Canberra. Downloaded on April 28,2020 at 00:25:50 UTC from IEEE Xplore. Restrictions apply.
1085
more vulnerable to soft errors than logic [19]. However, employing
conventional protection techniques to develop soft-error-hardened
SRAM-based TCAM poses significant challenges for its efficient
employment.
The usual fault tolerance techniques introduce modular or infor-
mational redundancy in the circuit [3]. In the modular redundancy,
triple modular redundancy (TMR) is the most common technique,
which can be used for protecting the logic-based TCAMs. The
basic concept of TMR is to design three identical circuits with
a majority voter to mask errors. Therefore, the TMR-based SEU
hardening of TCAMs is realized at a very high cost of logic, speed,
and power consumption [3]. In the information redundancy, error-
correction codes (ECCs) like Hamming [20] is typically used for
hardening SRAM in the FPGA. The ECCs-based protection of the
SRAM content emulating the TCAM function is realized at a cost
of additional storage and delay overhead. Similar work in [11]
shows that employing single-bit ECCs (SECs) for the protection of
SRAM-based TCAMs adds complex SEC decoders in the critical path
of the design, resulting in a substantial increase in the delay and logic
overhead, leading to a decreasing impact on search performance.
A soft-error protection technique for SRAM-based TCAMs based
on the specificity of the TCAM contents has been presented in
previous work [11]. This technique uses single-bit parity checking
for error detection; however, a complex error-correction scheme is
used, based on some intrinsic redundancy of the memory contents.
Its error-correction process involves reading the entire words of the
corrupted SRAM, and in the worst-case scanning of the entire design-
configured SRAMs. Although this complex error correction process
can be implemented in a soft processor, its response time is very
high. Thus, the contents of SRAMs implementing the TCAM design
remains faulty (inconsistent) for lookups during the already high
error-correction response time. Moreover, it is also not able to provide
protection against 100% SBUs.
A soft error-protection technique for SRAM-based TCAM solu-
tions is required that does not affect the overall search throughput of
the design. In this brief, a soft-error resilient SRAM-based TCAM
design (ER-TCAM) is presented which provides a low-cost error-
protection solution without compromising the critical path delay,
while maintaining a high system throughput. Error detection is
performed using a single-bit parity checking at the cost of minimal
storage, logic, and delay overhead. ER-TCAM exploits the binary-
encoded TCAM table maintained on-chip for update purposes in
error correction, achieving a substantially lower response time com-
pared with that of others at no additional cost. Moreover, the ER-
TCAM technique does not affect the data path processing of the
TCAM design, as the search operations are allowed during the error-
correction process.
IV. E RROR -R ESILIENT SRAM-B ASED TCAM: ER-TCAM
Informational redundancy is essential to realize fault tolerance in
SRAM-based TCAMs. In SRAM-based TCAMs, the 2C × D bit data
stored in SRAMs realizing TCAM functionality is generated from a
D × C TCAM content, which is at most 2D × C bit information
because of the three states of a TCAM cell can be represented using
two SRAM bits (“0”→“00,” “1”→“01,” and “x”→“10”). As dis-
cussed before, in modern SRAM-based TCAMs, the original TCAM
content is also maintained on-chip for update purposes, so the 2C X D
bit data of the design-configured SRAMs is completely redundant.
ER-TCAM exploits this system-level data redundancy to correct soft
errors in SRAMs. The basic idea of the ER-TCAM technique is
illustrated in Fig. 2. The two SRAMs, shown in Fig. 2(a), implements
the TCAM table partitions presented in Fig. 1(a). Fig. 2(b) shows an
8 × 4 size SRAM storing binary-encoded contents of the TCAM
1086 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 28, NO. 4, APRIL 2020
Fig. 2. Simplified example of the proposed ER-TCAM. (a) Error detection
in parity protected SRAMs implementing TCAM. (b) Error correction vector
generation using the binary encoded TCAM contents.
Fig. 3. Proposed ER-TCAM architecture for error detection.
table, providing redundancy of the matching information in SRAMs
realizing TCAM.
To detect an SBU in SRAMs, the ER-TCAM adds a parity bit for
each SRAM word as shown in Fig. 2(a). Error detection is performed
on the words of SRAMs accessed during lookups. Once an error is
detected in a word, the ER-TCAM uses the redundant information
stored in the binary-coded TCAM table for correction.
For example, when a search key (0110) is applied to SRAMs
shown in Fig. 2(a), accesses the second (00101) and third words
(01110) of the first and second SRAMs, respectively. The calculated
parity for the match bits of the second SRAM word (01110) does
not match the parity stored, indicating the occurrence of an SBU in
SRAM as shown in Fig. 2(a). The ER-TCAM accesses the words
of SRAM storing the binary-encoded contents of the related TCAM
partition one by one. The SRAM words read are matched with the
corresponding bit pattern (10) to compute match bits and associated
parity (01010) collectively called error-correction vector (ECV) as
shown in Fig. 2(b). The computed ECV is further written over the
corrupted SRAM word. In this way, the ER-TCAM ensures 100%
coverage against the SBUs. Moreover, the ER-TCAM is able to
protect against a special case of MBUs when an odd number of
bits flip in an SRAM word detected and corrected using the same
aforementioned processes.
A. Architecture of the Proposed ER-TCAM
Fig. 3 shows the proposed ER-TCAM error-detection architecture.
When an input search key is applied for lookup, the bits of the SRAM
words read are EX-ORed to get an error signal. The error signals from
the N SRAMs of the TCAM design are encoded to get a log2 N-bit
error code that uniquely identifies respective corrupted SRAM. The
error code and related search-key bit patterns are forwarded to the
error-correction module.
Fig. 4 shows the ER-TCAM architecture for error correction which
mainly comprises an SRAM storing binary-encoded contents of the
TCAM table, an ECV computation unit, an address generation unit
(AGU), and a read/write controller. The MOD-D counter generates a
new sequence of log2 D bits for every cycle. The SRAM address is
Authorized licensed use limited to: University of Canberra. Downloaded on April 28,2020 at 00:25:50 UTC from IEEE Xplore. Restrictions apply.
Fig. 4. Proposed ER-TCAM error-correction module.
executed such that log2 N-bits of the SRAM ID constitute its most
significant bits and points to the start of the corresponding sub-block
in SRAM, and the lower log2 D bits from the counter select SRAM
words in the sub-block. In this way, the AGU accesses all the binary-
encoded words of the corresponding partition of the TCAM table. The
TCAM words read are matched with the C-bit pattern to get a match-
bit each cycle, thus requiring D clock cycles to compute the match
bits and the associated parity bit, composing the ECV. The read/write
controller generates write enable high signal for the corresponding
SRAM to write the computed ECV over the corrupted SRAM word.
During the error-correction process, the ER-TCAM allows search
operations as SRAMs realizing the TCAM function are available
for lookup operations. The ER-TCAM configures these SRAMs as
simple dual-port RAM that performs the read and write in parallel at
the same clock cycle. Once the ECV is computed, it is written using
the write port of SRAM, thus, the error correction process completely
overlaps the search operations in the ER-TCAM. Although a soft
error can occur in the SRAM storing binary-encoded TCAM table;
however, its error occurrence probability compared with that of
SRAMs realizing TCAM is very low, owing to its relatively small
size. Still, the ER-TCAM is able to protect SRAM storing the binary-
encoded TCAM table using ECCs at a very little cost of memory and
error-correction latency overhead.
V. I MPLEMENTATION AND P ERFORMANCE E VALUATION
A. FPGA Implementation and Results
ER-TCAM design experiments were conducted using Xilinx
Vivado Design Suite 2018.3, targeting the Artix-7 FPGA device
(xc7a200tffv1156-2). The maximum achievable clock rate and
resource consumption of the ER-TCAM are reported using the Xilinx
post-place-and-route results.
Table I lists the FPGA resource utilization for three different
TCAM sizes (case I: 64 × 40, case II: 512 × 40, and case III:
1024 × 40) implemented using BRAM and distRAM resources for
the ER-TCAM technique. The ER-TCAM implementation cases I,
II, and III utilizes 5-, 38-, and 76 36-kb size BRAMs, respectively,
and 0.5-, 1.5-, and 2.5 36-kb size BRAMs, respectively, for storing
the binary encoded contents of the respective TCAM tables as shown
in the second and fifth columns of Table I. The memory overhead
in the ER-TCAM for maintaining a binary-encoded TCAM table
is minimal as SRAM-based TCAMs utilize 57 BRAM bits for
implementing a single TCAM bit, while the binary-encoded storage
of a ternary bit requires only two bits, thus, a memory overhead of
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 28, NO. 4, APRIL 2020 1087

TABLE I TABLE II
FPGA I MPLEMENTATION R ESULTS OF THE ER-TCAM FPGA R ESOURCE U TILIZATION C OMPARISON OF VARIOUS BRAM AND
DIST RAM-B ASED TCAM S P ROTECTION A RCHITECTURES

only 3.5% BRAM bits. The distRAM-based ER-TCAM cases I, II,

and III utilize 352, 2816, and 5632 LUTRAMs, respectively. As can
be seen, the resource utilization for implementing the ER-TCAM
technique is considerably small. Moreover, the ER-TCAM cases I–III
maintain a high search rate of 233, 227, and 222 million searches
per second ( SPS), respectively, when implemented in the BRAM
and 250, 233, and 223 SPS, respectively, when implemented in the
distRAM.

B. Comparison With Other TCAM Protection Techniques

1) FPGA Resource Utilization: Table II compares the FPGA
resource utilization for various SRAM-based TCAM protection
techniques implemented using BRAM and distRAM resources,
respectively. Column 3 lists the BRAMs and distRAM usage for emu- TABLE III
lating TCAM along with the BRAMs usage for storing binary- E RROR C ORRECTION L ATENCY OF P ROPOSED ER-TCAM
encoded TCAM tables, as shown in parentheses. All of the given
SRAM-based TCAM-protection techniques use the same method-
ology to emulate TCAM discussed before in Section II, thereby
utilizing almost comparable BRAM and LUTRAM resources. Owing
to the additional check bits used in the SEC-based TCAM protection
for error correction, its LUTRAM utilization is higher than others
as shown in Table II. Table II shows that the LUT utilization of the
SEC-based and Reviriego et al. [11] is higher than the ER-TCAM
because of their complex error-correction mechanisms.
2) Error Detection Delay (EDD) and Response Time: As discussed The error-correction time in the ER-TCAM is presented in Table III
before, SEUs may result in a false match/mismatch, returning an and is calculated according to the following equation:
incorrect matching address. The error-detection process examines
the correctness of the matching address; therefore, the EDD greatly Error correction time
affects the search performance of TCAM. On the other hand, once an = Delay × # of cycles required for error correction. (1)
error is detected, the stored TCAM contents become inconsistent and
The error-correction process in the ER-TCAM constitutes the
search operations are not allowed during the error-correction process.
cycles required for computing ECV and one cycle to write ECV
Therefore, minimal EDD and deterministic low error-correction
onto the corrupted SRAM. The ER-TCAM computes a single match
response time are required to avoid its negative impact on the overall
bit cycle, thereby the ECV computing takes cycles equal to the
search performance of TCAM.
width of SRAMs realizing TCAM. The ER-TCAM configures the
A comparison of the ER-TCAM with other FPGA-based TCAM
BRAMs as 512 × 72 RAM, each word storing 64 matching bits, thus
protection architectures in terms of EDD (lookup plus parity checking
takes 65 clock cycles in the error-correction process. The ER-TCAM
delay) is shown in the last column of Table II. ER-TCAM cases
configures the distRAMs as 32×65 RAM, thus takes 65 cycles in the
I, II, and III are able to achieve EDD of 8.6, 8.8, and 9 ns,
error-correction process. Table III shows that the ER-TCAM is able
respectively, when implemented in the BRAM and 8, 8.6, and
to achieve a very low error-correction response time, thus ensuring a
8.98 ns, respectively, when implemented in the distRAM. As can
faultless TCAM for the entire operating time of the applications.
be observed, the EDD in ER-TCAM remains low irrespective of
the size of the implemented TCAM table. However, the EDDs in
Reviriego et al. [11] and SEC-based protection techniques are very VI. C ONCLUSION
high and do not scale well with an increase in the size of the This brief presents an error-detection and -correction technique
implemented TCAM table. for SRAM-based TCAMs, which makes the most of the redundant

Authorized licensed use limited to: University of Canberra. Downloaded on April 28,2020 at 00:25:50 UTC from IEEE Xplore. Restrictions apply.
1088 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 28, NO. 4, APRIL 2020
original TCAM content maintained on-chip for update purposes to
provide a low area, critical path delay, and response time protection.
The proposed method uses single-bit parity to detect faults at a
minimal cost of logic and critical path delay. The proposed error
resiliency technique, called ER-TCAM, employs the binary-encoded
TCAM table in SRAM-based TCAMs to correct errors. SRAMs
implementing the TCAM function are available for search operations
during the error-correction process carried out in the background,
thus, the proposed error-correction technique does not affect the
data path processing. The ER-TCAM achieved a search performance
of up to 250 million searches per second with an EDD of 8 ns
and a deterministic error-correction time of 260 ns when tested
on the Artix-7 FPGA device. However, the error-correction time
of other existing error-correction techniques is very high and non-
deterministic. Compared with others, the ER-TCAM achieves at least
two times better EDD. The ER-TCAM can be useful for network
system or other system-on-chips that require SRAM-based TCAMs
as a search engine for accelerating specific tasks.
R EFERENCES
[1] P. He, W. Zhang, H. Guan, K. Salamatian, and G. Xie, “Partial order
theory for fast TCAM updates,” IEEE/ACM Trans. Netw., vol. 26, no. 1,
pp. 217–230, Feb. 2018.
[2] W. Fu, T. Li, and Z. Sun, “FAS: Using FPGA to accelerate and secure
SDN software switches,” Secur. Commun. Netw., vol. 2018, Jan. 2018,
Art. no. 5650205.
[3] T. Li, H. Liu, and H. Yang, “Design and characterization of
SEU hardened circuits for SRAM-based FPGA,” IEEE Trans. Very
Large Scale Integr. (VLSI) Syst., vol. 27, no. 6, pp. 1276–1283,
Feb. 2019.
[4] T. Li, H. Yang, H. Zhao, N. Wang, Y. Wei, and Y. Jia, “Investigation
into SEU effects and hardening strategies in SRAM based FPGA,” in
Proc. 17th Eur. Conf. Radiat. Effects Compon. Syst. (RADECS), 2019,
pp. 1–5.
[5] A. Ramos, R. G. Toral, P. Reviriego, and J. A. Maestro, “An
ALU protection methodology for soft processors on SRAM-based
FPGAs,” IEEE Trans. Comput., vol. 68, no. 9, pp. 1404–1410,
Mar. 2019.
Authorized licensed use limited to: University of Canberra. Downloaded on April 28,2020 at 00:25:50 UTC from IEEE Xplore. Restrictions apply.
[6] S. Pontarelli, P. Reviriego, and J. A. Maestro, “Parallel D-pipeline:
A cuckoo hashing implementation for increased throughput,” IEEE
Trans. Comput., vol. 65, no. 1, pp. 326–331, Mar. 2015.
[7] P. Reviriego, A. Ullah, and S. Pontarelli, “PR-TCAM: Efficient TCAM
emulation on Xilinx FPGAs using partial reconfiguration,” IEEE Trans.
Very Large Scale Integr. (VLSI) Syst., vol. 27, no. 8, pp. 1952–1956,
Mar. 2019.
[8] Ternary Content Addressable Memory (TCAM) Search IP for SDNet
V1.0; Xilinx Product Guide PG190, Xilinx, San Jose, CA, USA,
Nov. 2017.
[9] W. Jiang, “Scalable ternary content addressable memory implementation
using FPGAs,” in Proc. 9th ACM/IEEE Symp. Archit. Netw. Commun.
Syst., 2013, pp. 71–82.
[10] M. Irfan and Z. Ullah, “G-AETCAM: Gate-based area-efficient
ternary content-addressable memory on FPGA,” IEEE Access, vol. 5,
pp. 20785–20790, 2017.
[11] P. Reviriego, S. Pontarelli, and A. Ullah, “Error detection and correction
in SRAM emulated TCAMs,” IEEE Trans. Very Large Scale Integr.
(VLSI) Syst., vol. 27, no. 2, pp. 486–490, Feb. 2019.
[12] I. Ullah, Z. Ullah, U. Afzaal, and J.-A. Lee, “DURE: An energy-and
resource-efficient TCAM architecture for FPGAs with dynamic updates,”
IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 27, no. 6,
pp. 1298–1307, Mar. 2019.
[13] Z. Ullah, K. Ilgon, and S. Baeg, “Hybrid partitioned SRAM-based
ternary content addressable memory,” IEEE Trans. Circuits Syst. I, Reg.
Papers, vol. 59, no. 12, pp. 2969–2979, Dec. 2012.
[14] I. Ullah, Z. Ullah, and J.-A. Lee, “Efficient TCAM design based on
multipumping-enabled multiported SRAM on FPGAA,” IEEE Access,
vol. 6, pp. 19940–19947, 2018.
[15] Xilinx. (2016). 7 Series FPGAs Configurable Logic Block User
Guide UG474 (V1.8). Accessed: Jun. 25, 2019. [Online]. Available:
http://www.xilinx.com
[16] A. M. Keller and M. J. Wirthlin, “Impact of soft errors on large-
scale FPGA cloud computing,” in Proc. ACM/SIGDA Int. Symp. Field-
Program. Gate Arrays, 2019, pp. 272–281.
[17] Device Reliability Report, Xilinx, San Jose, CA, USA, 2018.
[18] D. Shah and P. Gupta, “Fast updating algorithms for TCAM,” IEEE
Micro, vol. 21, no. 1, pp. 36–47, Jan. 2001.
[19] S. R. Nassif, N. Mehta, and Y. Cao, “A resilience roadmap,” in Proc.
Design, Autom. Test Eur. Conf. Exhib., 2010, pp. 1011–1016.
[20] S. B. Akers, “A parity bit signature for exhaustive testing,” IEEE
Trans. Comput.-Aided Design Integr. Circuits Syst., vol. CAD-7, no. 3,
pp. 333–338, Mar. 1988.