Professional Documents
Culture Documents
Presented by Gudied by
R.POORNIMA Dr.V.J.ARUL KARTHICK
ME-VLSI PROFESSOR&HEAD,
DEPARTMENT OF HOD
OBJECTIVE
• The SRAM based TCAM will using major part in FPGA based
application it will support to reduced vulnerable to soft error with
high search performance and reduced critical path delay.
•It reduce the cost and response time with single bit parity fault
detection and minimal critical path overhead.
INTRODUCTION
• A binary CAM stores and searches data in only two state 0and1
• Some existing method implement the TCAM memory cells with FPGA flip-flops and logic.This approach has limited scalability in terms of the TCAM size 64×40, 512×40, 1024×40
• once the error is detected in a word,the ER-TCAM stroed in the binary code TCAM table for correction
ER TCAM FOR ERROR DETECTION
cont’d…
• When an input search key is applied for lookup, the bits of the
SRAM words read are EX-ORed to get an error signal.
• The error signals from the N SRAMs of the TCAM design are
encoded to get a log2N-bit error code that uniquely identifies
respective corrupted SRAM.
• The error code and related search-key bit patterns are forwarded
to the error-correction module.
ER-TCAM for Error Correction
cont’d…
• High performance
APPLICATIONS
• File-storage management
• Pattern recognition
• Artificial intelligence
RESULT
CONCLUSION
• The proposed error-correction technique does not affect the
data path processing.
2)W. Fu, T. Li, and Z. Sun, Jan. 2018, “FAS: Using FPGA to accelerate and
secure SDN software switches,” Secur. Commun. Netw., vol. 2018, Art. no.
5650205.
3)T. Li, H. Liu, and H. Yang, “Design and characterization of SEU hardened
circuits for SRAM-based FPGA,” IEEE Trans. Very Large Scale Integr.
(VLSI) Syst., vol. 27, no. 6, pp. 1276–1283, Feb. 2019.