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ER-TCAM: A SOFT-ERROR-RESILIENT SRAM-BASED

TERNARY CONTENT-ADDRESSABLE MEMORY FOR


FPGAS

Presented by Gudied by
R.POORNIMA Dr.V.J.ARUL KARTHICK
ME-VLSI PROFESSOR&HEAD,
DEPARTMENT OF HOD
OBJECTIVE

• The SRAM based TCAM will using major part in FPGA based
application it will support to reduced vulnerable to soft error with
high search performance and reduced critical path delay.

•It reduce the cost and response time with single bit parity fault
detection and minimal critical path overhead.
INTRODUCTION

•FPGA is semiconductor device around the matrix of CLB


connected via programmable interconnects.

• Content-addressable memory (CAM) allows the stored content


to be searched in parallel in a single cycle, achieving a high
search performance.

• A binary CAM stores and searches data in only two state 0and1

• TCAM represent data in three state 0,1,and do not care state x


cont’d…
• (SRAM)-based FPGA technology offers the flexibility and
reconfigurability with high performance required in software
defined networking (SDN).
EXITING METHOD

• Some existing method implement the TCAM memory cells with FPGA flip-flops and logic.This approach has limited scalability in terms of the TCAM size 64×40, 512×40, 1024×40

• Multi-bit error with same parity cannot be


identified in the existing method.

• Eg.0110🡪1111(2 bit error but both has parity‘0’)


Simplified implementation of TCAM using SRAM. (a) 4×4
TCAM table. (b) Implementing a 4 ×4 TCAM using two 4 × 4
SRAMs.
PROPOSED METHOD

• Enhanced ER-TCAM Size up to 2048 x 40, and proved with


existing ER-TCAM Size 64×40, 512×40, 1024×40.

• MBU(Multiple bit error) Once an error is detected, by


assuming that the erroneous frame is erased, its contents are
recovered using an erasure code

• The identification of the exact location of erroneous bits is not


of our interest, rather a low-cost error detection technique with a
very high detection coverage is required.
cont’d…
•For detecting MBUs in the configuration frames of the FPGA,
we propose a lowcost technique, namely, n dimensional parity.
MBU DETECTION
Simplified example of the proposed ER-TCAM. (a) Error detection in
parity protected SRAMs implementing TCAM. (b) Error correction
vector generation using the binary encoded TCAM contents.

• The EXOR operation they easily find the error

• once the error is detected in a word,the ER-TCAM stroed in the binary code TCAM table for correction
ER TCAM FOR ERROR DETECTION
cont’d…

• When an input search key is applied for lookup, the bits of the
SRAM words read are EX-ORed to get an error signal.

• The error signals from the N SRAMs of the TCAM design are
encoded to get a log2N-bit error code that uniquely identifies
respective corrupted SRAM.

• The error code and related search-key bit patterns are forwarded
to the error-correction module.
ER-TCAM for Error Correction
cont’d…

• ER-TCAM architecture for error correction which mainly


comprises an SRAM storing binary-encoded contents of the
TCAM table, an ECV computation unit, an address generation
unit (AGU), and a read/write controller.

• The AGU accesses all the binary encoded words of the


corresponding partition of the TCAM table. The TCAM words
read are matched with the C-bit pattern to get a match bit each
cycle
cont’d…

• Once the ECV is computed, it is written using the write port of


SRAM, thus, the error correction process completely overlaps the
search operations in the ER-TCAM
ADVANTAGES

• Multi-bit error correction

• High performance
APPLICATIONS

• File-storage management

• Pattern recognition

• Artificial intelligence
RESULT
CONCLUSION
• The proposed error-correction technique does not affect the
data path processing.

• The ER-TCAM achieved a search performance of up to 250


million searches per second with an EDD(Error detection delay)
of 8 ns and a deterministic error-correction time of 260 ns when
tested on the Artix-7 FPGA device.

• The ER-TCAM achieved a higher search performance


compared to existing techniques
cont’d

• However, the error-correction time of other existing error-


correction techniques is very high and nondeterministic.
REFERENCES
1)P. He, W. Zhang, H. Guan, K. Salamatian, and G. Feb. 2018 Xie, “Partial
order theory for fast TCAM updates,” IEEE/ACM Trans. Netw., vol. 26, no. 1,
pp. 217–230, .

2)W. Fu, T. Li, and Z. Sun, Jan. 2018, “FAS: Using FPGA to accelerate and
secure SDN software switches,” Secur. Commun. Netw., vol. 2018, Art. no.
5650205.

3)T. Li, H. Liu, and H. Yang, “Design and characterization of SEU hardened
circuits for SRAM-based FPGA,” IEEE Trans. Very Large Scale Integr.
(VLSI) Syst., vol. 27, no. 6, pp. 1276–1283, Feb. 2019.

4) T. Li, H. Yang, H. Zhao, N. Wang, Y. Wei, and Y. Jia,2019 “Investigation


into SEU effects and hardening strategies in SRAM based FPGA,” in Proc.
17th Eur. Conf. Radiat. Effects Compon. Syst. (RADECS), pp. 1–5.

5)A. Ramos, R. G. Toral, P. Reviriego, and J. A. Maestro,Mar2019 “An ALU


protection methodology for soft processors on SRAM-based FPGAs,” IEEE
Trans. Comput., vol. 68, no. 9, pp. 1404–1410,.
THANKYOU

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