Name: __________________________________ Roll No: __________________

Computer Logic Design

Fall 2006 Semester

Sessional 2 Exams
Saturday, 11th November 2006

Total Time: 1 Hour

Total Marks: 40
Course Instructors:
Usman Khalid / Azhar Rauf

You are advised to READ these notes:

1. There are 3 questions. Attempt all of them on this question paper.

2. No answer sheets will be given. Rough paper if required must be attached to

this question paper.

3. The points for each question are written next to each question.

4. You may use the Flip-Flop Characteristic and Excitation Tables provided to you.

5. Other than 4. above, the exam is closed books, closed notes. Please see that the
area in your threshold is clean. You will be charged for any material which can be
classified as ‘helping in the paper’ found near you.

6. Calculator sharing is strictly prohibited.

7. The invigilator present is not supposed to answer any questions. If you have any
queries please state these on the answer sheet and continue. If there is any
problem with the question paper, students will be given the benefit of the doubt.

8. If there is any missing parameter, write down your assumption and continue.

Page 1 of 5
Problem 1: Points: 16 (12+4+2 effort)
A sequence of bits is received at a serial interface. Design a state-machine to detect a
total number of 3 ones and 2 zeroes in any order. After the detection of required number
of 1s, if the total number of zeros is not detected, the state machine should wait for
detecting the required number of zeros and vise versa.
Draw state diagram for:
a. Moore machine implementation
b. Mealy machine implementation

No overlapping of the last bit:

Page 2 of 5
NOTE:
Since it was not mentioned in the question so there are two possible solutions for both
machines,
1. Overlapping of the last bit and
2. No overlapping
Both the solutions are considered as correct. Previous Solution for Mealy machine was
incorrect since Moore machine was implemented under no overlap case and Mealy
machine was implemented under overlap case.
Now there is no overlap in both cases.

Problem 2: Points: 8 (4+4+1+1 effort)

Draw a Truth Table for a 4-bit priority encoder with active low inputs D0-D3 where D3
has the highest priority. Outputs are active high. When a valid output is available a signal
V asserts active high.
(No need to implement the Truth Table.)

Page 3 of 5
 D3’ D2’ D1’ D0’ A1 A0 V
1 1 1 1 0 0 0
0 X X X 1 1 1
1 0 X X 1 0 1
1 1 0 X 0 1 1
1 1 1 0 0 0 1

Problem 3: Points: 8 (2+2+2+2+1+1+8 effort)

Complete the timing diagram (given on next page) for the following circuit. Assume all
flip flops to be positive edge triggered, and an ideal timing diagram.

00
2-4 active high decoder
D3 D2 D1 D0

0 1 2 3
11 4-1 Mux

1
0
1
0
1 11 L S Reg Operation
L S x 0 Write
0 1 Left Shift
2
2

1 1 1 Right Shift
clk
4 Parallel in Serial Out LSB 1
Bidirectional Register a a>b
1011 a=b
Parallel in Serial Out a<b
b
4 Bidirectional Register MSB 1

Page 4 of 5
 clk
0.5 Q1 1
0.5 Q1’ 0

2 Q2 0

S 0

0.5 LSB 0

0.5 MSB 0
2 a=b 1
2 a>b 0

2 a<b 0

Page 5 of 5