Department of Computer Engineering

EE233: Digital Logic Design

Course Instructor: Dated:

Lab Engineer 1: Semester:

Lab Engineer 2: Session:

LAB 12 Sequential Circuits: Shift Registers

Name Roll. No. Report Marks (10) Viva Marks (5) Total Marks (15)

Checked on: ____________________________

Signature: ____________________________

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EE233: Digital Logic Design

Sequential Circuits: Shift Registers

12.1. Introduction
This lab exercise aims to develop an understanding of the working of a shift register, universal shift register and its
different modes of operation. In one task, pseudo-random number sequence is generated by use of shift register and XOR
gate and in another a Johnson counter is designed and tested using shift register.

12.2. Objective
This lab will enable the students to achieve the following:
 Understand the shift operation and the construction and working of a shift register
 Demonstrate parallel load, shift left and shift right operations in a universal shift register
 Generate pseudo-random numbers using shift registers
 Design and test the operation of a Johnson counter using shift register

12.3. Conduct of Lab

1. The students have to perform this experiment using logic trainer.
2. The students are required to work in groups of two. Every group member is expected to contribute equally to the
completion of the lab and achieve the learning objectives.
3. In case some aspect of the lab experiment is not understood the students are advised to seek help from the teacher, the
lab technicians or the assigned Teaching Assistant (TA).

12.4. Theory and Background

12.4.1. Register
A register is a group of flip-flops that can store binary information. One flip-flop can store one bit. An n-bit register has n
flip-flops and stores n-bits of binary information.
12.4.1.1. Shift register
In addition to flip-flops, a register also has logic gates that determine how the data in the register is to be processed. A
register with combinational logic gates that has the ability to shift its data from right to left or left to right is called a shift
register. Depending on the combinational logic circuit used in the shift register, it may have operations of parallel load,
serial input, clear, shift right and shift left etc.

12.5. Parts and Equipment

1. Digital Logic Trainer
2. 74194: 4-bit bidirectional universal shift register
3. 7486: Quad 2-input XOR gate
4. Connecting wires

12.6. Lab Tasks

12.6.1. Universal Shift register

1. A universal shift register is the most general of the shift registers and is capable of performing the following four
operations:

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Registers

 Load parallel input

 Shift right with serial input from left
 Shift left with serial input from right
 Hold output
To select one of the four modes, there are two select inputs S1 and S0. 74LS194 is a 4-bit bidirectional universal shift
register. Its pin configuration is as below:

Figure 12.1: Pin configuration of 74LS194

S0-S1: Mode selection inputs

Clear (Active-Low): Stores 0 in all bits of the register asynchronously
Shift right serial input (SIR): Serial input when right shift mode is selected
A, B, C, D: Parallel outputs
Shift left serial input (SIL): Serial input when left shift mode is selected
A, B, C, D: Parallel inputs; these will be loaded into the shift register when parallel input mode selected
QA-QD: Parallel outputs
Clock: Positive-edge of the clock triggers the register
2. Apply the inputs according to the following table. Keep the frequency of the clock low such that you get time to
change the inputs in between consecutive clock edges. Enter output states in the empty boxes: [5 marks]
Table 12.1: Operation of 74194

S1 S0 SIR SIL A B C D Clock OA OB OC OD Mode of operation

1 1 X X 1 1 0 1 ↑ Load
0 1 1 X X X X X ↑
0 1 1 X X X X X ↑
Shift Right
0 1 0 X X X X X ↑
0 1 0 X X X X X ↑
1 0 X 1 X X X X ↑
1 0 X 1 X X X X ↑
Shift Left
1 0 X 0 X X X X ↑
1 0 X 0 X X X X ↑
0 0 X X X X X X ↑ Hold Output

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12.6.2. LFSR
1. The following is a 4-bit Fibonacci Linear Feedback Shift Register made using a XOR gate. It ican be used to generate
pseudo-random sequence of numbers.

Figure 12.2: LSFR

2. Build this circuit on breadboard using universal shift register IC 74194 and XOR gate IC 7486. Select the parallel load
mode of the shift register and load 0001 in the register. Now select the shift mode of the shift register and apply clock
pulse by manually toggling the logic switch to which clock pin of the IC is connected. Note down the 4-bit output after
each positive edge of the clock in Table 12.2. [5 marks]
Table 12.2: LSFR

Clock Shift Clock Shift Clock Shift Clock Shift

Edge Register Edge Register Edge Register Edge Register
No. Output No. Output No. Output No. Output
1. 9. 16. 24.
2. 10. 17. 25.
3. 11. 18. 26.
4. 12. 19. 27.
5. 13. 20. 28.
6. 14. 21. 29.
7. 15. 22. 30.
8. 23. 31.
3. This circuit generates a sequence of random numbers and repeats the sequence after a few clock cycles. State below
your observations; specifically state the number of clock cycles after which the sequence restarts. [2 marks]

12.6.3. Johnson counter using shift register

1. A Johnson counter is a modified ring counter. A 4-bit Johnson counter outputs the following 4-bit sequence (Table
12.3) in 8 clock cycles and then repeats.

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Table 12.3: Johnson counter

Clock
edge A B C D
number
1 0 0 0 0
2 1 0 0 0
3 1 1 0 0
4 1 1 1 0
5 1 1 1 1
6 0 1 1 1
7 0 0 1 1
8 0 0 0 1
9 (repeat) 0 0 0 0
2. Use a 4-bit shift register and additional combinational logic to design a Johnson counter. Draw logic circuit in the
space below: [3 marks]

3. Build and test your design on breadboard and show working to lab engineer to obtain credit. [4 marks]
State at least two key theoretical concepts or design techniques that you have studied, verified by experiment or
practiced in today’s lab session. [2 marks]

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