MANUAL

INTEGRATED CIRCUITS LAB

Experiment No:
Date:

DESIGN AND TESTING OFSYNCHRONOUS COUNTERS

AND
AIM:
SPECIFIED SEQUENCE COUNTER.
To design, set up and verify the working of the following circuits using
JKFFs.

a) 4 bit up counter
b) 4 bit down counter
c) 3 bit up/down counter
d) Mode 5 up counter
e) Self starting mode 5 counter
f) Self starting counter for a sequence 0, 2,4, 5, 0, 2, 4, 5.....

COMPONENTS AND EQUIPMENTS REQUIRED:

ICs 7476, 7473, 7408, 7400, 7432 and trainer kit.
THEORY
Synchronous and asynchronous counters provide same outputs. The difference is that
in the synchronous counters all flip flops work in symchronism with the input clock pulse. That
means the outputs of all the flip flops in the counter change state at the same instant. Therefore,
the propagation delay occurring in asynchronous counter is eliminated in synchronous counters.
Synchronous counters for any given count sequence or modulus can be designed and set up by
the following procedure.

1. Find the number of flip flops using the relation M-2 where M is the modulus of the
counter and N is minimum number of flip flop required. N=log. M
2. Write down the count sequence (FF outputs) in a tabular form.
3. Determine the flip flop inputs which must be present for the desired next state using
excitation table of flip flops.
4. Prepare Karnaugh maps for each FF inputs in terms of FF outputs as the input variables.
Obtain the minimized expression from the k-maps.
S. Set up the circuit using FF's and other gates.

Up/down counters:
An up/down counter is capable of progressing the counting in either direction through a
An counter can have any specified sequence of states. A mode control
up/down
certain sequence.
pin is used to decide whether the counter should count up or down.

Self starting counters:

While the counting progresses, there is a chance of the counter falling to an unused or
undesired state. If it happens, the next state will be unknown to counter and it might not progress
 INTEGRATED CIRCUITS LAB MANUAI

to make the counter start

ds aesired. To avoid this kind of lock out alogic circuit is designed
truth table. Counter has
state. Refer to the
Om the initial state if the counter falls to an undesired that if the count happens to be
O Count Irom O to 4. Precaution should he taken in the design so

an undesired one, next count is made 0 to reset the counter.

EXCITATION TABLE OF KFLPFLOP

nGnt D D
0 0 0 X
0
1 0
1 1X 0

4 BIT BINARY UP COUNTER

Ql

+5 b
127476 127476 127416 127476

CLK
Cr
 3 BIT UP/DOWN COUNTER

Cr Cir
2
12
hl4 12Q
1/2 7476 S12 7476
E3 3

M 1213
CLK

4BIT BINARY DOWN COUNTER

+SV
12 7476 2 7476 1/27476 /27476

CIK
Ch
 MOD SUP COUNTER

Qy

1/2 7476
1/27476 1/2 7476

CLK

SELF STARTING MODE S COUNTER

1/2 7476 1/27476 1/2 7476

+5 K
CLK

SELF STARTING SEQUENCE COUNTER FOR A SEQUENCE 0,2,4,5,0,2,4,5

1/27476 1/2 7476 1/2 7476

+SV

CLK

PROCEDURE

1. Test all components and IC packages using multimeter or digital IC tester.

2. Set up the circuit one by one and verify the counter states.

RESULT
Circuit was designed and output was verified.