Chapter 6

Registers and Counters

 原編者 : 嚴茂旭 副教授

 修改 : 盧晃瑩
 6.1 Registers:

• Clocked sequential circuits

– connected to form a feedback path
Flip-flops + Combinational gates
(essential) (optional)
• Register:
– a group of flip-flops and and combinational gates
– 1 register is 1-bit memory.

• Counter:
– A register that goes through a predetermined sequence of states

Registers and Counters

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 6-1 Registers:

• A n-bit register
– n flip-flops capable of storing n
bits of binary information

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 6-1 Registers
• 4-bit register with parallel load
A
A0
0
0 y = s’A + sI
y
I 1
I0 1 S
S
Load
1
A1
0

I1 1 S

Load
1
A2
0

I2 1 S

Load
1
A3
0

I3 1 S

Load
1
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 6-2 Shift Registers

• Shift register
– A register is capable of shifting its binary information in one or both
directions
• Simplest shift register

1 0 1 1 0
1 1 0 1 1

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 6-2 Shift Registers

• Serial transfer
– Serial transfer
» Information is transferred one bit at a time
» shifts the bits out of the source register into the destination regis
ter
– Parallel transfer:
» All the bits of the register are transferred at the same time

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 6-2 Shift Registers
• Ex: Serial transfer from reg. A to reg. B

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 6-2 Shift Registers
• Serial addition using D flip-flops

0101
1 1 1
1010
0101
+ 0011
------------------
1000
0011
?001

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 6-2 Shift Registers
• Serial adder using JK flip-flops

(Ci) (Ci+1)

– Circuit diagram
JQ = x y
KQ = x’y’ = (x +
y)’
S =xyQ

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 6-2 Shift Registers (cont’s)
• Ex: 4-bit universal shift register

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 6-2 Shift Registers (cont’s)

(S1,S0) (S1,S0) (S1,S0) (S1,S0)

0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3

A3 A2 A1 A0
Si_R A3 A2 A1
A2 A1 A0 Si_L
I3 I2 I1 I0

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 6-2 Shift Registers (cont’s)

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 6-3 Ripple Counters

• Categories of counters
1. Ripple counters
The flip-flop output transition serves as a source for triggering ot
her flip-flops.
Þ no common clock pulse (not synchronous).

2. Synchronous counters:
The CLK inputs of all flip-flops receive a common clock.

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 6-3 Ripple Counters

• Counter:
– a register that goes through a prescribed sequence of state
s.

– upon the application of input pulses

» Input pulses: may be clock pulses or originate from some e
xternal source.
» The sequence of states: may follow the binary number seque
nce ( Binary counter) or any other sequence of states.

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 6-3 Ripple Counters
• 2-bit ripple counter:

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 6-3 Ripple Counters
• Ex:

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 6-3 Ripple Counters
Ex:

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 6-3 Ripple Counters

• Example: 4-bit binary ripple counter

– Binary count sequence: 4-bit

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 6-3 Ripple Counters


10

10

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 6-3 Ripple Counters
• BCD ripple counter

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 6-3 Ripple Counters
• Three-decade BCD counter

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 6-4 Synchronous Counters

• Sync counter
– A common clock triggers all flip-flops simultaneously

• Design procedure
– apply the same procedure of sync seq. ckts
– Sync counter is simpler than general sync seq. ckts

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 6-4 Synchronous Counters
EX: Base-16 counter

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 6-4 Synchronous Counters
EX: Base-8 up/down counter

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 6-4 Synchronous Counters
EX: Design a decimal counter, which goes through

0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0

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 6-4 Synchronous Counters
• 4-bit binary counter with parallel load

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 load count load’
c_en

c_en
A0

async

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 6-4 Synchronous Counters
• Generate any count sequence
– e.g. BCD counter  Counter with parallel load

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 6-5 Other Counters

• Counters:
– can be designed to generate any desired sequence of states

• Divide-by-N counter (modulo-N counter)

– a counter that goes through a repeated sequence of N states
– The sequence may follow the binary count or may be any othe
r arbitrary sequence

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 6-5 Other Counters

• n flip-flops  2n binary states

• Unused states
– states that are not used in specifying the FSM
– may be treated as don’t-care conditions or may be assigned specific next states

• Self-correcting counter
– Ensure that when a ckt enter one of its unused states, it eventually goes into o
ne of the valid states after one or more clock pulses so it can resume normal o
peration.
 Analyze the ckt to determine the next state from an
unused state after it is designed

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 6-5 Other Counters
EX:

• Two unused states: 011 & 111

The simplified flip-flop input eqs:
JA = B, KA = B
JB = C, KB = 1
JC = B’, KC = 1

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 • Ring counter:
– a circular shift register : Only one flip-flop is set at any partic
ular time, and all others are cleared
(initial value = 1 0 0 … 0 )
– The single bit is shifted from one flip-flop to the next to produ
ce the sequence of timing signals.

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 6-5 Other Counters
Ex: • Ring counter:
• 4-bit ring counter – a circular shift register : Only one flip-
flop is set at any particular time, and all
A3 A2 A1 A0 others are cleared
1 0 0 0 (initial value = 1 0 0 … 0 )
0 1 0 0 – The single bit is shifted from one flip-
flop to the next to produce the sequence
0 0 1 0 of timing signals.
0 0 0 1
1 0 0 0

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 6-5 Other Counters
• Application of counters
– Counters may be used to generate timing signals to control the s
equence of operations in a digital system.

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 6-5 Other Counters
Johnson counter:

• Ring counter vs. Switch-tail ring counter

– Ring counter
» a k-bit ring counter circulates a single bit among the flip-flops to
provide k distinguishable states.

– Switch-tail ring counter (Johnson counter)

» A circular shift register’s complement output of the last flip-flo
p is connected to the input of the first flip-flop

» a k-bit switch-tail ring counter will go through a sequence of 2k

distinguishable states. (initial value = 0 0 … 0)

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 6-5 Other Counters
Ex: a k-bit switch-tail ring counter + 2k decoding gates
provide outputs for 2k timing signals

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 6-5 Other Counters

• Disadvantage: switch-tail ring counter

– If it finds itself in an unused state, it will persist to circulate in the i
nvalid states and never find its way to a valid state.
– One correcting procedure: DC = (A + C) B
• Summary:
– Johnson counters can be constructed for any # of timing sequences
:
# of flip-flops = 1/2 (the # of timing signals)
# of decoding gates = # of timing signals
A 2-input gate for each state

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