Chapter 5

Synchronous Sequential Logic

 原編者 : 嚴茂旭 副教授

 修改 : 盧晃瑩
 5-1 Introduction
• Digital logic circuits:
– Combinational
– Sequential

• Combinational circuits (see Ch. 4)

– contains no memory elements
– the outputs depends on the inputs

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5-2
 5-2 Sequential Circuits
• Sequential circuits (From Ch. 5)

– a feedback path
– the state of the sequential circuit
– (inputs, current state) Þ (outputs, next state)

– synchronous:
Synchronous Sequential the transition happens at discrete instants of time
Logic
5-3
– asynchronous: at any instant of time
 5-3 Latches
• Two NOR gates

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 5-3 Latches
• Two NAND gates

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 5-3 Latches
• D Latch (Transparent Latch)
– D Þ Q when En = 1; no change when En = 0

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 5-3 Latches
Graphic symbols

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 5-4 Flip-Flops
Edge-triggered D flip-flop
• Master-slave D flip-flop
– two separate flip-flops
– a master flip-flop (positive-level triggered)
– a slave flip-flop (negative-level triggered)

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 5-4 Flip-Flops

• If level-triggered flip-flops are used

– the feedback path may cause instability problem
• Edge-triggered flip-flops
– the state transition happens only at the edge
– eliminate the multiple-transition problem

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 5-4 Flip-Flops
• Edge-triggered flip-flops
– the state changes during a clock-pulse transition
• A D-type positive-edge-triggered flip-flop

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5-4 Flip-Flops
• Setup time (ts)
– D input must be maintained at a constant value prior to the applicat
ion of the positive CP pulse
• Hold time (th)
– D input must not changes after the application of the positive CP pu
lse

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 5-4 Flip-Flops
• Propagation delay time (tPHL, tPLH)
– the interval between the trigger edge and the stabilization of the out
put to a new state

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 5-4 Flip-Flops

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5-4 Flip-Flops

Q’

CLK

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 5-4 Flip-Flops
Other Flip-Flops
• JK flip-flop

 D = JQ’ (t) + K’Q(t)

 Q(t+1) = JQ’(t) + K’Q(t)
K 0 1
–D = J’K’Q(t) + JK’ + JKQ’(t)
J = J’K’Q + JK’(Q+Q’) + JKQ’
0 Q(t) 0 = J’K’Q + JK’Q + JK’Q’ + JKQ’
1 1 Q’(t) = K’Q (J’+ J) + JQ’(K’ + K)
= JQ’ (t) + K’Q(t)
Synchronous Sequential Logic = JQ’ + K’Q
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 5-4 Flip-Flops
Other Flip-Flops
• T flip-flop

 Q(t+1) = T ⊕ Q = TQ’ + T’Q

Synchronous
– D Sequential
5-16
= T ⊕ QLogic
= TQ’ + T’Q
»
 Characteristic Tables

 Q(t+1) = JQ’(t) + K’Q(t)

 Q(t+1) = T ⊕ Q = TQ’ + T’Q

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 5-4 Flip-Flops
Other Flip-Flops with direct inputs
• asynchronous set and/or asynchronous reset

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5-5 Analysis of Clocked Sequential Ckts
• A sequential circuit
– (inputs, current state) Þ (output, next state)
– Analysis: Circuit diagram => Equations => State table => State diagra
m

• State equations
– A(t + 1) = A(t)x(t) + B(t)x(t)
– B(t + 1) = A’(t)x(t)
• A more compact form
– A(t + 1) = Ax + Bx
– B(t + 1) = Ax
• The output equation
– y(t) = (A(t) + B(t))x’(t)
– y = (A + B)x’

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5-5 Analysis of Clocked Sequential Ckts
State table

• State equations (excitation

functions)

– A(t + 1) = Ax + Bx
– B(t + 1) = A’x

• Output equations
– y(t) = (A(t) + B(t))x’(t)
– y = (A + B)x’

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5-5 Analysis of Clocked Sequential Ckts
• State (transition) diagram
– a circle: a state
– a directed lines connecting the circles:
» Each directed line is labeled “inputs/outputs”

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5-5 Analysis of Clocked Sequential Ckts

Analysis with D flip-flops

• Input equation
– DA = A ⊕ x ⊕ y

• State equation
– A(t + 1) = A ⊕ x ⊕ y

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5-5 Analysis of Clocked Sequential Ckts
• Input equation
Analysis with JK flip-flops JA = B, KA= Bx’
JB = x’, KB = A’x + Ax’
￭ State equation
A(t+1) = JAA’ + KA’A
= BA’ + (Bx’)’A
= A’B + AB’ + Ax

B(t+1) = JB B’ + KB’B
= x’B’ + (A’x + Ax’)’B
= x’B’ + A’Bx’ + ABx

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5-5 Analysis of Clocked Sequential Ckts
Analysis with T flip-flops • Input & output equatios
– TA=Bx
– TB= x
– y = AB
• 注意 : 輸出 y 只有
與目前狀態 AB 有 • State equations
關，與輸入 x 無關 – A(t + 1) = (Bx)’A + (Bx)A’
= AB’ + Ax’ + A’Bx
– B(t + 1) = x ⊕ B

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5-5 Analysis of Clocked Sequential Ckts
Mealy and Moore models
• Mealy model: the outputs are functions of both the present state and inputs
 the outputs may have momentary false values unless the inputs are synchronized with
the clocks
• Moore model: the outputs are functions of the present state only
– The outputs are synchronous with the clocks

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5-5 Analysis of Clocked Sequential Ckts
Ex. ?

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 5-7 State Reduction and Assignment
• State Reduction
– reductions on the number of flip-
flops and the number of gates

– only the input-output sequences are important

– two circuits are equivalent
» have identical outputs for all input sequenc
es
» the number of states is not important

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 5-7 State Reduction and Assignment
• Equivalent states
– two states are said to be equivalent
» for each member of the set of inputs, they give exactly the same out
put and send the circuit to the same state or to an equivalent state
» one of them can be removed

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 5-7 State Reduction and Assignment
• (a, b, c)(d, e, f, g) …. 根據輸出分成兩類

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 5-7 State Reduction and Assignment
State assignment
– to minimize the cost of the combinational circuits
– three possible binary state assignments

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 5-7 State Reduction and Assignment
Ex: (Text, ex5-12)

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 5-8 Design Procedure
– circuit behavior (a state diagram)

– state reduction

– assign binary values to the states

– state table

– choose the type of flip-flops

– simplify input equations and output equations

– logic diagram

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 5-8 Design Procedure
Synthesis using D flip-flops
• Ex: Input =1 => next state = new state & output =1, else next state = unchanged & out
put =0

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 5-8 Design Procedure
Synthesis using D flip-flops

A(t + 1) = DA(A, B, x)
= S(3, 5, 7)

B(t + 1) = DB(A, B, x)
= S(1, 5, 7)

y(A, B, x) = S(6, 7)

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 5-8 Design Procedure

Simplify using the K map

DA= Ax + Bx
DB= Ax + B’x
y = AB

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 5-8 Design Procedure
• Logic diagram

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 5-8 Design Procedure
Excitation tables of JK F/F

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 5-8 Design Procedure

Excitation tables of T F/F • Excitation tables

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 5-8 Design Procedure
Synthesis using JK flip-flops
• Ex: The same example

JA

KA

JB

KB

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 5-8 Design Procedure

JA(A, B, x) = S(2) + (4,5,6,7)

KA(A, B, x) = S(7) + (0,1,2,3)

JB(A, B, x) = S(1,5) + (2,3,6,7)

KB(A, B, x) = S(2,7) + (0,1,4,5)

– JA = Bx’; KA = Bx
– JB = x; KB = (A⊕x)’
– y = AB

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 5-8 Design Procedure

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 5-8 Design Procedure
Synthesis using T flip-flops
• A n-bit binary counter

– state diagram

Synchronous Sequential Logic

5-42 – no inputs (except for the clock input)
 5-8 Design Procedure
• State table and the flip-flop inputs

TA2(A2, A1, A0) = S(3, 7)

TA1(A2, A1, A0) = S(1, 3, 5, 6, 7)

TA0(A2, A1, A0) = S(0, 1, 2, 3, 4, 5, 6, 7)

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 5-8 Design Procedure
￭ Simplify

TA2(A2, A1, A0) = S(3, 7)

TA1(A2, A1, A0) = S(1, 3, 5, 6, 7)

TA0(A2, A1, A0) = S(0, 1, 2, 3, 4, 5, 6, 7)

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 5-8 Design Procedure
• Logic simplification
– TA2 = A1A2
– TA1 = A0
– TA0 = 1

• Logic diagram

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