Boolean Algebra and Logic Gates

Chapter 2
Boolean Algebra and Logic Gates
 原編者 : 嚴茂旭副教
授
 修改 : 盧晃瑩
Two-valued Boolean Algebra
 Boolean set : {0,1}
 The rules of operations:
x y xy x y x+y x x
0 0 0 0 0 0 0 1
0 1 0 0 1 1 1 0
1 0 0 1 0 1
1 1 1 1 1 1

2-2
Basic Theorems and Properties

2-3
• Theorem 1(a): x+x = x
– x+x = (x+x) 1 by postulate: 2(b) =
(x+x) (x+x') 5(a) = x+xx'
4(b) = x+0 5(b)
=x 2(a)
– Theorem 1(b): x • x = x
– x•x=xx+0 by postulate: 2(a) = xx +
xx' 5(b) = x (x + x')
4(a) =x•1 5(a) =x
2(b)

2-4
 Theorem 5 , DeMorgan's Theorems
 (x+y)' = x' y'
 (x y)' = x' + y'

x y x+y (x+y) x y xy
0 0 0 1 1 1 1
0 1 1 0 1 0 0
1 0 1 0 0 1 0
1 1 1 0 0 0 0

2-5
 Theorem 6
 x + xy = x • 1 + xy = x (1 +y)
=x•1
=x
 x (x + y) = x by duality
 Truth table
x y xy x + xy
0 0 0 0
0 1 0 0
1 0 0 1
1 1 1 1

2-6
Boolean Functions => Truth table
 The truth table for F1 and F2 F1(x, y, z)= x + y z‘
F2 (x, y, z)= x' y' z + x' y z + x y’

2-7
Boolean Functions => Logic gates

2-8
Boolean Functions => Logic gates

2-9
TTL 7408 (AND Gate)
實體包裝內部構造
VCC
GND
VCC
GND
元件符號真值表輸入端輸入端輸出端

A B OUT
0 0 0
A
OUT
B 0 1 0
1 0 0
1 1 1

2-10
Implementation F1 = x + y’z
7404
VCC
7432
GND
VCC
7408
GND

2-11
Algebraic Manipulation
2. x + x’y = x(y + y’ ) + x’y = xy + xy’ + x’y

= xy + xy’ + xy + x’y = x(y + y’ ) + (x +x’ )y
=x+y

2-12
Complement of a Function
F1(x, y, z)= x + y z‘
F2 (x, y, z)= x' y' z + x' y z + x y’

F1’ F2’
1 1
0 0
1 1
1 0
0 0
0 0
0 1
0 1
2-13
 by DeMorgan's theorem
 (A+B+C)' = (A+X)' let B+C = X = A'X'
by DeMorgan's = A'(B+C)'
= A'(B'C') by
DeMorgan's = A'B'C'
associative
 Generalized
 (A+B+C+ ... +F)' = A'B'C' ... F'
 (ABC ... F)' = A'+B'+C'+ ... +F'

2-14

2-15

2-16
Canonical and Standard Forms
 Minterm: an AND term consists of all literals in their
normal form or in their complement form
 e.g. x , y  xy, xy', x'y, x'y'

 Also called a standard product
 n variables  2n minterms
 Maxterm: an OR term
 e.g. x , y  x+y, x+y', x‘+y, x‘+y'

 Also called a standard sum
 n variables  2n maxterms
2-17
Maxterm and minterm
 Each maxterm is the complement of its corresponding
minterm, and vice versa.

2-18
Maxterm and minterm
 An Boolean function can be expressed by
 a truth table
 sum of minterms: e.g.
f1 = x'y'z + xy'z' + xyz = m1 + m4 +m7
f2 = x'yz+ xy'z + xyz'+xyz = m3 + m5 +m6 + m7

2-19
Maxterm and minterm
 The complement of a Boolean function
 f1' = m0 + m2 +m3 + m5 + m6 =
x'y'z'+x'yz'+x'yz+xy'z+xyz'
 f1 = (f1')' = (x+y+z)
(x+y'+z) (x+y'+z') (x'+y+z')(x'+y'+z) = M 0 M2
M3 M 5 M 6
 Any Boolean function can be expressed as

 a sum of minterms
 a product of maxterms
 canonical form
2-20
Sum of minterms, Sum of products (SOP)
 EX2.4: Express the Boolean function F=A+B’C
as a sum of minterms
 Sol:
 F = A+B'C = A (B+B') + B'C
= AB +AB' + B'C
= AB(C+C') + AB'(C+C') + (A+A')B'C
=ABC+ABC'+AB'C+AB'C'+A'B'C
 F(A, B, C) = A'B'C +AB'C' +AB'C+ABC'+ ABC

= m1 + m4 +m5 + m6 + m7
= S(1, 4, 5, 6, 7)
 Another approach: Build the truth table first

2-21
Product of maxterms, Product of sums (POS)
 Conversion between Canonical Forms
 F(A, B, C) = S(1, 4, 5, 6, 7)
 F’(A, B, C) = S(0, 2, 3) = m0 + m1 + m2
 By DeMorgan's theorem
F = (m0 + m2 + m3)’ = m’0 • m’2 • m’3
= M0M2M3 = Π(0, 2, 3)
 m j' = M j

2-22
 Ex: Express the Boolean function F = xy + x’z as a product of
maxterms
Sol: F(x, y, z) = S(1, 3, 6, 7) = P (0, 2, 4, 5)

2-23
 Standard Forms
 sum of products F1 = y' + xy+ x'yz‘ (Fig. 2.3a)
 product of sums F2 = x(y'+z)(x'+y+z') (Fig. 2.3b)

2-24
F3 = AB + C (D + E) (Fig. 2.4a)
= AB + C (D + E) = AB + CD + CE (Fig. 2.4b)

2-25
Digital logic gates

2-26
Digital logic gates

2-27
Digital logic gates
 NAND and NOR are commutative but not associative

2-28
Digital logic gates
 Multiple NOR = a complement of OR gate
Multiple NAND = a complement of AND gate
 The cascaded NAND operations = sum of products

The cascaded NOR operations = product of sums

2-29
Digital logic gates
 The XOR and XNOR gates are commutative and associative
 XOR is an odd function: it is equal to 1 if the inputs variables have

an odd number of 1's

2-30
Digital logic gates
 Positive logic is used in this book

2-31
Digital logic gates

2-32
Integrated Circuits
 An IC (a chip)
 Ex:
 SSI: < 10 gates
 MSI: 10 ~ 100 gates
 LSI: 100 ~ xk gates
 VLSI: > xk gates

 small size (compact size)
 low cost
 low power consumption
 high reliability
 high speed

2-33
Integrated Circuits
 Digital logic families: circuit technology
 TTL: transistor-transistor logic
 ECL: emitter-coupled logic (high speed, high power consumption)
 MOS: metal-oxide semiconductor (NMOS, high density)
 CMOS: complementary MOS (low power consumption)

2-34
Integrated Circuits
 The characteristics of digital logic families
 Fan-out: the number of standard loads that the output of a typical
gate can drive
 Power dissipation
 Propagation delay: the average transition delay time for the signal
to propagate from input to output
 Noise margin: the minimum of external noise voltage that caused

an undesirable change in the circuit output

2-35
Integrated Circuits
 CAD – Computer-Aided Design
 Millions of transistors
 Computer-based representation and aid
 Automatic the design process
 Design entry
 Schematic capture
 HDL – Hardware Description Language
 Verilog, VHDL
 Simulation
 Physical realization
 ASIC, FPGA, PLD

2-36

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Chapter 2