Maulana Azad National Institute of

Technology

Department of Computer Science and Engineering

Computer System Organization Lab

Submitted by: Shreya Rangile

Scholar no: 201112024
Section 1

1
 Index
S Name of Assignment Page Assigned Submission
No. No. Date Date

1. Assembly Language Program on the Usage of Loops 4 25/01/22 31/01/22

• Find the sum of 5 numbers 1+2+3+4+5 using loop

• Find the sum of 5+6+7 using 1+2+..7 – 1+2+3+4 using loop

2. Assembly Language Program to realize Simple Instruction Set 6 01/02/22 07/02/22

• Write a program to find the smallest of 5 numbers in an array

starting at 0021H and store the result at location 0030H.

• Find the square of an 8 bit number.

• Subtract two 8 bit numbers stored at memory location 0020H

and 0021H and store the result and arrow at locations 0022H
and 0023H respectively.

3. Assembly Language Program to Calculate Factorial in 8085. 9 08/02/22 16/02/22

4. Simulation of Shift Register (SISO and SIPO) 10 15/02/22 22/02/22

• Simulate SISO shift registers using D – Flip Flops for the

serial input bit string “1010”.

• Simulate the SISO shift registers by realizing D – Flip Flop

using the JK – Flip Flop for the serial input bit string “1010”.

5. Simulation of Shift Register (PIPO and PISO) 18 22/02/22 01/03/22

• Simulate SIPO shift registers using D – Flip Flops for the

serial input bit string “1010”.

• Simulate the SIPO shift registers by realizing D – Flip Flop

using the JK – Flip Flop for the serial input bit string “1010”.
6. Simulation of Ripple Carry Adder 24 08/03/22 22/03/22

• Simulate 4-bit ripple-carry adder.

• Simulate 16-bit ripple-carry adder using 4-bit ripple carry

adders.
7. Simulation of Carry Look Ahead Adder. 31 29/03/22 04/04/22

2
 • Design 4 bit carry look ahead adder

• Design 6 bit carry look ahead adder

8. C Program to Implement Direct Mapping, Associative 38 05/04/22 14/04/22

Mapping and Set-Associative Mapping.

3
 Assignment 1

Q1) Find the sum of 5 numbers 1+2+3+4+5 using loop.

MVI B,05H

XRA A

MOV C,A

LOOP: ADD B

JNC SKIP

INR C

SKIP: DCR B

JNZ LOOP

LXI H,0000H

MOV M,C

INX H

MOV M,A

HLT

Output:

4
Q2) Find the sum of 5+6+7 using 1+2+..7  -   1+2+3+4  using loop.
MVI B,4H
LOOPB: ADD B
DCR B
JNZ LOOPB
OUT 05H

MVI B,7H
LOOPD: ADD B
DCR B
JNZ LOOPD
OUT 06H

IN 05H
MOV B,A
IN 06H
SUB B
OUT 07
HLT

Output:

5
 Assignment 2

Q1) Write a program to find the smallest of 5 numbers in an array starting at

0021H and store the result at location 0030H.

CODE: LXI H,0020H

MOV C,M
INX H
MOV B,M
DCR C
LOOP: INX H
MOV A,M
CMP B
JNC SKIP
MOV B,A
SKIP: DCR C
JNZ LOOP
LXI H,0030H
MOV M,B
HLT

OUTPUT:

6
Q2) Find the square of a 8-bit number.

CODE: XRA A
MOV C,A

LXI H,0000H
MOV B,M
MOV D,M

LOOP: ADD B
JNC SKIP
INR C
SKIP: DCR D
JNZ LOOP

INX H
MOV M,A
INX H
MOV M,C

HLT

OUTPUT:

7
Q3) Subtract two 8-bit numbers stored at memory location 0020H and 0021H
and store the result and borrow at locations 0022H and 0023H respectively.

CODE: XRA A
MOV C,A

LXI H,0020H
MOV A,M

INX H
SUB
JNC SKIP
INR C
SKIP: INX H

MOV M,A

INX H
MOV M,C

HLT

OUTPUT:

8
 Assignment 3

Q) Write a program to find the factorial of a numbers. Fetch the number from
memory location 0100H. Store the result in memory locations 0101H and
0102H (Result may be a 16-bit number).
CODE:
LXI H,0100H
MOV E,M
MVI D,00H
MOV B,M
DCR B

FACT: MOV A,B

LXI H,0000H
CPI 00H
JZ GO
MUL: DAD D
DCR A
JNZ MUL
GO: XCHG
DCR B
JNZ FACT
SHLD 0101H
HLT

OUTPUT:

9
 Assignment 4

EXPERIMENT 1

AIM: To simulate SISO shift registers using D-Flip Flops for the serial input bit
string “1010”.

OBJECTIVE: To study the behaviour of different modes of data input by using

SISO shift register.

DESCRIPTION: Shift registers hold the data in their memory which is moved
or “shifted” to their required positions on each clock pulse. The data in SISO
register is shifted serially “IN” and “OUT” of the register, one bit at a time in
either a left or right direction under clock control.

CIRCUIT:

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 EXPERIMENT 2

AIM: To simulate SISO shift registers by realising D-Flip Flops using JK Flip
Flops for the serial input bit string “1010”.

OBJECTIVE: To study the behaviour of different modes of data input by using

SISO shift register.

DESCRIPTION: Shift registers hold the data in their memory which is moved
or “shifted” to their required positions on each clock pulse. The data in SISO
register is shifted serially “IN” and “OUT” of the register, one bit at a time in
either a left or right direction under clock control.

CIRCUIT:

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 EXPERIMENT 3

AIM: To simulate SIPO shift registers using D-Flip Flops for the serial input bit
string “1010”.

OBJECTIVE: To study the behaviour of different modes of data input by using

SIPO shift register.

DESCRIPTION: Shift registers hold the data in their memory which is moved
or “shifted” to their required positions on each clock pulse. The register is
loaded with serial data, one bit at a time, with the stored data being available at
the output in parallel form.

CIRCUIT:

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 EXPERIMENT 4

AIM: To simulate SIPO shift registers by realising D-Flip Flops using JK Flip
Flops for the serial input bit string “1010”.

OBJECTIVE: To study the behaviour of different modes of data input by using

SISO shift register.

DESCRIPTION: Shift registers hold the data in their memory which is moved
or “shifted” to their required positions on each clock pulse. The register is
loaded with serial data, one bit at a time, with the stored data being available at
the output in parallel form.

CIRCUIT:

16
 Assignment 5

Experiment 1

AIM: To simulate PISO shift registers using D-Flip Flops for the serial input bit string
“1010”.

OBJECTIVE: To study the behaviour of different modes of data input by using PISO shift
register.

DESCRIPTION: Parallel-in/ serial-out shift registers do everything that the previous serial-
in/ serial-out shift registers do plus input data to all stages simultaneously. The parallel-in/
serial-out shift register stores data, shifts it on a clock-by-clock basis, and delays it by the
number of stages times the clock period.

CIRCUIT:

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 Experiment 2

AIM: To simulate PISO shift registers by realising D-Flip Flops using JK Flip Flops for the
serial input bit string “1010”.

OBJECTIVE: To study the behaviour of different modes of data input by using PISO shift
register.

DESCRIPTION: Parallel-in/ serial-out shift registers do everything that the previous serial-
in/ serial-out shift registers do plus input data to all stages simultaneously. The parallel-in/
serial-out shift register stores data, shifts it on a clock-by-clock basis, and delays it by the
number of stages times the clock period.

CIRCUIT:

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 Experiment 3

AIM: To simulate PIPO shift registers using D-Flip Flops for the serial input bit string
“1010”.

OBJECTIVE: To study the behaviour of different modes of data input by using PIPO shift
register.

DESCRIPTION: Parallel-in/ serial-out shift registers do everything that the previous serial-
in/ serial-out shift registers do plus input data to all stages simultaneously.

CIRCUIT:

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 Experiment 4

AIM: To simulate PIPO shift registers by realising D-Flip Flops using JK Flip Flops for the
serial input bit string “1010”.

OBJECTIVE: To study the behaviour of different modes of data input by using PIPO shift
register.

DESCRIPTION: Parallel-in/ serial-out shift registers do everything that the previous serial-
in/ serial-out shift registers do plus input data to all stages simultaneously.

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CIRCUIT:

Assignment 6

Experiment 1

Aim : To simulate 4-bit Ripple carry adder.

Objective : To design the 4-bit ripple carry adder using full adders and to check it’s activity after
implementation.

Description : A full adder is a combinational circuit that forms the arithmetic sum of three bits, consists
of 3 inputs (A, B & Cin) and 2 outputs (Sum & Cout). Where, Sum = A Ꚛ B Ꚛ Cin and Cout = Cin(A Ꚛ
B) + AB

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Now, in a ripple carry adder which is designed by full adders :

● Each full adder has to wait for it’s Cin from it’s previous stage full adder.
● Thus, nth full adder has to wait until all (n-1) full adders have completed their operations.
● This causes a delay and makes ripple carry adder extremely slow.
● The situation becomes worst when the value of n becomes very large.
● To overcome this advantage, carry look ahead adder comes into play.

Simulated circuit :

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 Experiment 2

Aim : To simulate 16-bit Ripple carry adder using 4-bit Ripple carry adders.

Objective : To design the 16-bit ripple carry adder using full adders and to check it’s activity after
implementation.

Description : Now, in a 16-bit ripple carry adder which is designed by using 4-bit ripple carry adders :

● Each RC adder has to wait for it’s Cin from it’s previous stage RC adder.
● Thus, nth RC adder has to wait until all (n-1) RC adders have completed their operations.
Simulated circuit :

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 Assignment 7

Q1) Design 4 – bit carry look ahead adder.

Description: A carry look-ahead adder reduces the propagation delay by introducing more complex
hardware. In this design, the ripple carry design is suitably transformed such that the carry logic over
fixed groups of bits of the adder is reduced to two-level logic.

In ripple carry adders, for each adder block, the two bits that are to be added are available instantly.
However, each adder block waits for the carry to arrive from its previous block. So, it is not possible to
generate the sum and carry of any block until the input carry is known. The (𝑖)𝑡ℎ block waits for the( 𝑖 −
1)𝑡ℎ block to produce its carry. So there will be a considerable time delay which is carry propagation
delay.

● Carry generate = Gi
● Carry propagate = Pi
Pi = Ai Ꚛ Bi

Gi = Ai.Bi

Si = Pi Ꚛ Ci

Ci+1 = Gi + Pi.Ci

And

Full adder for CLA :

31
4 – bit CLA Circuit:

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Q2) Design 6 – bit carry look ahead adder.

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6 – bit CLA Circuit:

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37
 Assignment 8

Q) Write a program to implement Direct, Fully Associative and K-way Set

Associative cache mapping.

Solution.
#include <bits/stdc++.h>

using namespace std;

#define endl '\n'

typedef long long ll;

int main_memory_size = 128;

int cache_memory_size = 16;

int address_size = (int)log2(main_memory_size * 4);

int binToDec(vector<bool> &arr, int l, int r)

int ans = 0;

for (int i = r; i >= l; i--)

ans += (1 << abs(r - i)) * arr[i];

return ans;

int gen_rand(int l, int r)

random_device dev;

38
 mt19937 rng(dev());

uniform_int_distribution<mt19937::result_type> dist(l, r);

return dist(rng);

class MainMemoryAddress

public:

vector<bool> address;

MainMemoryAddress()

address = vector<bool>(address_size, 0);

void create(int r)

int i = address_size - 1;

while (r)

address[i] = (r & 1);

i = i - 1;

r = r >> 1;

pair<int, int> positions()

int line = binToDec(address, 0, address_size - 1) / 4;

int no_in_line = binToDec(address, 0, address_size - 1) % 4;

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 return {line, no_in_line};

void generateNextReference()

int line = binToDec(address, 0, address_size - 1) / 4;

int no_in_line = binToDec(address, 0, address_size - 1) % 4;

if (no_in_line == 3)

line++;

no_in_line = 0;

else

no_in_line++;

create((line * 4) + no_in_line);

string data()

string ans;

for (auto x : address)

ans.push_back(x + 48);

return ans;

};

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class DataAddress

public:

vector<MainMemoryAddress> reference;

DataAddress(int n)

reference = vector<MainMemoryAddress>(n);

};

class MainMemory

public:

vector<vector<char>> mainMemory;

vector<vector<MainMemoryAddress>> mainMemoryAddress;

MainMemoryAddress next_empty;

MainMemory()

mainMemory = vector<vector<char>>(main_memory_size, vector<char>(4));

mainMemoryAddress = vector<vector<MainMemoryAddress>>(main_memory_size,
vector<MainMemoryAddress>(4));

void insert(string data, DataAddress &address)

int n = data.length();

for (int i = 0; i < n; i++)

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 {

pair<int, int> pos = next_empty.positions();

mainMemory[pos.first][pos.second] = data[i];

mainMemoryAddress[pos.first][pos.second].create((pos.first * 4) + pos.second);

address.reference[i] = next_empty;

next_empty.generateNextReference();

string getData(DataAddress &address)

int n = address.reference.size();

string ans;

for (int i = 0; i < n; i++)

pair<int, int> pos = address.reference[i].positions();

ans.push_back(mainMemory[pos.first][pos.second]);

return ans;

void showMainMemory()

for (int i = 0; i < main_memory_size; i++)

for (int j = 0; j < 4; j++)

cout << "Value : " << mainMemory[i][j] << " Address : " <<
mainMemoryAddress[i][j].data() << " ";

42
 }

cout << endl;

};

class CacheMemoryAddress

public:

vector<bool> address;

CacheMemoryAddress()

address = vector<bool>(address_size, 0);

void create(int r, int tag)

int i = address_size - 1;

while (r)

address[i] = (r & 1);

i = i - 1;

r = r >> 1;

i = address_size - 1 - log2(cache_memory_size * 4);

while (tag)

address[i] = (tag & 1);

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 i = i - 1;

tag = tag >> 1;

void createFullyAssosiative(int r, int tag)

int i = address_size - 1;

while (r)

address[i] = (r & 1);

i = i - 1;

r = r >> 1;

i = address_size - 3;

while (tag)

address[i] = (tag & 1);

i = i - 1;

tag = tag >> 1;

void createKSetAssosiative(int r, int c, int tag, int space)

int i = address_size - 1;

while (r)

address[i] = (r & 1);

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 i = i - 1;

r = r >> 1;

i = address_size - 3;

while (c)

address[i] = (c & 1);

i = i - 1;

c = c >> 1;

i = address_size - 3 - log2(space);

while (tag)

address[i] = (tag & 1);

i = i - 1;

tag = tag >> 1;

vector<int> position()

int row = binToDec(address, address_size - 2 - log2(cache_memory_size / 4),

address_size - 3);

int col = binToDec(address, address_size - 2, address_size - 1);

int tag = binToDec(address, 0, address_size - 3 - log2(cache_memory_size / 4));

return {row, col, tag};

string data()

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 {

string ans;

for (auto x : address)

ans.push_back(x + 48);

return ans;

};

class CacheMemory

vector<vector<char>> cahceMemory;

vector<vector<CacheMemoryAddress>> cahceMemoryAddress;

vector<bool> included;

public:

CacheMemory(MainMemory &memory)

cahceMemory = vector<vector<char>>(cache_memory_size, vector<char>(4));

cahceMemoryAddress = vector<vector<CacheMemoryAddress>>(cache_memory_size,
vector<CacheMemoryAddress>(4));

included = vector<bool>(main_memory_size, false);

void storeDirect(MainMemory &memory, int k)

for (int i = 0; i < cache_memory_size; i++)

46
 {

cahceMemory[i] = memory.mainMemory[i + k * 4];

for (int j = 0; j < 4; j++)

cahceMemoryAddress[i][j].create(i * 4 + j, (i + k * 4) / 4);

void storeFullyAssosiative(MainMemory &memory)

int l = 0, r = memory.next_empty.positions().first;

for (int i = 0; i < cache_memory_size; i++)

int choose_itr = gen_rand(l, r);

while (included[choose_itr])

choose_itr = gen_rand(l, r);

cahceMemory[i] = memory.mainMemory[choose_itr];

for (int j = 0; j < 4; j++)

cahceMemoryAddress[i][j].createFullyAssosiative(i * 4 + j, choose_itr);

void storeKSetAssosiative(MainMemory &memory, int k)

47
 int l = 0, r = memory.next_empty.positions().first;

int n = cache_memory_size / k;

for (int i = 0; i < n; i++)

for (int j = i * k; j < (i + 1) * k; j++)

int choose_itr = gen_rand(l, r);

while (included[choose_itr] and choose_itr % k != i)

choose_itr = gen_rand(l, r);

cahceMemory[j] = memory.mainMemory[choose_itr];

for (int t = 0; t < 4; t++)

cahceMemoryAddress[j][t].createKSetAssosiative(t, j - i * k, choose_itr / k,
cache_memory_size / k);

void showCacheMemory()

for (int i = 0; i < cache_memory_size; i++)

for (int j = 0; j < 4; j++)

cout << "Value : " << cahceMemory[i][j] << " Address : " <<
cahceMemoryAddress[i][j].data() << " ";

48
 }

cout << endl;

};

int main()

MainMemory memory;

int k, cnt, y;

cin >> cnt;

while (cnt--)

int n;

string s;

cout << "Enter length of data." << endl;

cin >> n;

cout << "Enter data string." << endl;

cin >> s;

DataAddress data(n);

memory.insert(s, data);

CacheMemory cache(memory);

CacheMemory cacheFullyAssosiative(memory);

CacheMemory cacheKWaySetAssosiative(memory);

cout << "Enter index for first element in cache." << endl;

cin >> k;

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 cout << "Enter k in K-Way Set Assosiative" << endl;

cin >> y;

cache.storeDirect(memory, k);

cacheFullyAssosiative.storeFullyAssosiative(memory);

cacheKWaySetAssosiative.storeKSetAssosiative(memory, y);

cout << endl

<< "Main memory is as Follows" << endl

<< endl;

memory.showMainMemory();

cout << endl

<< "Direct Cache memory is as Follows" << endl

<< endl;

cache.showCacheMemory();

cout << endl

<< "Fully Assosiative Cache memory is as Follows" << endl

<< endl;

cacheFullyAssosiative.showCacheMemory();

cout << endl

<< "K Set Assosiative Cache memory is as Follows" << endl

<< endl;

cacheKWaySetAssosiative.showCacheMemory();

return 0;

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