Lab Session # 8

Implementation of Registers

1. Introduction
In this experiment, you will get introduced to the concept of registers and some of their types. In addition,
you will learn to design, implement and test parallel load and shift registers using QUARTUS II Software.

2. Objectives
By the end of this lab experiment, students will:
• Learn the concept of registers.
• Learn to design and implement parallel load and shift registers using Quartus II.
• Practice testing their designs by simulation and downloading on the Cyclone IV E FPGA on Altera
DE2-115 board.

3. Registers

A set of n flip-flops that can store n bits of binary information is referred to as a register.

• In addition to flip-flops, which hold the binary information, a register may have
combinational gates, which determine how the information is transferred into register.

• A common clock is used for each flip-flop in a register.

• In a n-bit register, if CLRN (Clear) input of all D-flip-flops goes to 0, all flip-flops are reset
asynchronously and register outputs Qn-1 …. Q1Q0 = 0.

• The CLRN inputs is maintained at logic 1 during normal clocked operation.

• Various types of registers such as Parallel-load, Universal-shift register etc. are available.

3.1 Parallel-Load Register

In order to store n-bit data in parallel (in one clock cycle), input data bits are connected to their
respective D flip-flop inputs. Figure 1 shows an n-bit register with n inputs (Dn-1 … D1 D0) connected to
D inputs of n D f lip-flop. One clock pulse (at positive edge) will load all the n-bits of data into the
register, hence, Qn-1 ... Q1 Q0 = Dn-1 … D1 D0.
 Figure 1: n-Bit Register

Problem Statement: Designing n-Bit Parallel-load Register

Design a 4-bit parallel-load register using Quartus II Software.

1. Design this circuit (with file name Regr4) using Quartus II behavioral Verilog code.

module Regr4 (D, Clear, Clock, Q);

input [3:0] D;
input Clear, Clock;
output reg [3:0] Q;
always @ (posedge Clock)
if ( Clear )
Q <= D;
else
Q <= 4’b0;
endmodule

2. Analyze and Synthesize this circuit and Create the symbol (Regr4).
3. Perform Functional Simulation and Test the following functional table. Do not group all the
inputs.

Table 1: Functional Table for Regr4 Module

Parallel data
Clear Clock Q3 Q2 Q1 Q0
I3 I2 I1 I0

1 1011 ↑

0 X X

1 1001 ↑
 4. Comment the output Waveform: Mark at changes in the output at the positive edges of the clock.
Identify asynchronous operation (Change in the output without any clock).

3.2 Shift Register

It is also possible to transfer all bits using a single wire, by performing the transfer one bit at a time, in
n consecutive clock cycles. This scheme is referred to as serial transfer. A shift register shifts binary
data stored in the register to right or left one bit at a time synchronously on each clock pulse. On
every clock pulse, all the bits are shifted and hence one bit of data is shifted out at one end of the
register and a new bit is brought in serially at the other end.

• To implement a shift register, it is necessary to use edge-triggered flip-flops since the level-
sensitive gated latches are not suitable because a change in the value of the serial input would
propagate through more than one latch during the time when the clock is equal to 1.

Figure 2 shows a four-bit shift register that is used to shift its contents one bit position to the right. The
data bits are loaded into the shift register in a serial fashion using the serial input (SRin). The
contents of each flip-flop are transferred to the next flip-flop at each positive edge of the clock.

Figure 2: 4-Bit Shift Register

Table 2 shows what happens when the signal values applied to the serial input are 1, 0, 0, 1, 1during five
consecutive clock cycles.

• For every shift to the left b y one bit position, with a 0 inserted as the new least significant
bit, the binary number stored in the register is multiplied by 2. Similarly, for every shift to
the right by one bit position, with a 0 inserted as the new most significant bit, the binary
number stored in the register is divided by 2.
 Table 2: Sample Sequence of a 4-Bit Register

Inputs Outputs

Clear Clock SRin Q3 Q2 Q1 Q0

0 X X 0 0 0 0

1 ↑ 1 1 0 0 0

1 ↑ 0 0 1 0 0

1 ↑ 0 0 0 1 0

1 ↑ 1 1 0 0 1

1 ↑ 1 1 1 0 0

3.3 Shift Register with Parallel-load Facility

Some registers provide necessary input and output terminals for parallel transfer with shift right
capabilities. The most general shift register has the following capabilities.
• A clear control to clear the register to 0.
• A clock input to synchronize the operations.
• A shift-right or parallel-load control to enable shift right or parallel-load operation.
• A serial input line.
• n parallel output lines.

Based on Figure 1 and Figure 2, the design of a register that allows parallel–load with shift right
capabilities basically needs to select data input to each flip-flop. The D input should get data either
from its parallel-load input or from the output of a previous stage, and a 2-to-1 Mux can select the
appropriate input. The first two stages of a 4-bit register with parallel–load and shift right
capabilities is shown in Figure 3 and the subsequent stages will be identical to the second stage.

Figure 3: 4-Bit Register with Parallel–load and Shift Right Capabilities

 Problem Statement: Designing 4-Bit Register with Parallel–load and Shift Right

Capabilities

Complete the design in Figure 3 (on paper) for the missing bits (bit 1 and bit 0).
Student Name: Date:
Student ID:

Lab Exercise # 8

Problem Statement:
Using Quartus II Software, design a 4-bit Register with parallel–load and shift right capabilities. The
operation is selected based on the OP bits as shown below:
OP Register Operation

0 Shift Right

1 Parallel-load

Procedure:
1. Implement the circuit designed in Figure 3 as schematic capture.
2. Create a new Block Diagram/Schematic File → Save As → lab8.bdf
3. Double-Click on the empty screen to enter a new symbol → select the following symbols:

a. Regr4 symbol created from the Verilog code Regr4.v

b. lpm-mux from Megawizard

4. Save then Analyze and Synthesize the file to make sure that there are no errors.
5. Compile the file.
6. Perform a Functional Simulation to test the behavior of your design for several test cases to show
the correct functionality of the design (Table 1).
7. To download your design to Altera DE2-115 Board to and check its functionality correctness, you
will need to add the LFC symbol, which will provide control over the Clk signal using a Push
Button (PB).
8. Your instructor will provide you with the LFC symbol, or LFC Verilog code, for which you will
have to create a symbol (refer to Section 3.5 in Lab Session#1).
9. Place the LFC symbol in the same Block Diagram/Schematic design file where you have the
Regr4 and lpm_mux symbols connected.
10. Connect the Clk through LFC circuit. Now, the clock is generated by the LFC block, which is
triggered by the Push Button (PB).
11. Save your new design with a different name. Note that you cannot use the new design (with the
LFC symbol) to perform functional simulation. The LFC symbol is added only when downloading
your design to Altera DE2-115 Board.
12. Analyze and synthesize your design for the implemented circuit (refer to Section 3.2.5 in Lab
Session#1).
13. Compile your design.
14. Prepare the following pin assignment table using the pin configuration datasheet.
 Table 3: Pin Assignment

Input Selected DE2-115 Output Selected DE2-115

Signal Switch Cyclone IV E Pin Signal LED Cyclone IV E Pin
Pin
I0 SW0 Q3 LEDG3
I1 Q2 LEDG2
I2 Q1 LEDG1
I3 Q0 LEDG0
SRin
OP
Clear
PB KEY0
Clock CLOCK_50

15. Fit, Analyze and download the design into Cyclone IV E FPGA on Altera DE2-115 Board.
16. Compile your design AGAIN.
17. Program and configure the FPGA to test the implemented design physically using switches and
LEDs.
18. Test your downloaded design for the following cases (complete the table based on your results):

Table 4: Test Cases for the Designed Circuit

Input Output

Clear OP SRin I3 I2 I1 I0 PB Q3 Q2 Q1 Q0

0 X X X X 0 0 0 0

1 1 X 1011 ↑ 1 0 1 1

1 0 1 X ↑ 1 1 0 1

1 0 1 X ↑

1 0 0 X ↑

1 1 X 0110 ↑

1 0 0 X ↑

1 0 1 X ↑

19. Print your design files and simulation waveforms.

Ask your engineer to check your results, write his/her comments and sign below:

………………………………………………………………………………………………………………………...…………………………...……….
……………………………………………………………………………………………………………………...………………………...…………….
…………………………………………………………………………………………………………………...…………………………………………

Engineer Signature
……..……………..
Attachments:
Please attach with the lab exercise sheet printouts of the files indicated below. Don't forget to
write your Name and ID Number as comments in every file before printing.

1. Verilog code file (*.v file)

2. Waveform file with comments (*.sim.vwf file)
3. Graphical design file without Pin Assignment (*.bdf file)
4. Waveform file (*.sim.vwf file)
5. Graphical design file with Pin Assignment (*.bdf file)