Lab Session # 5

Implementing an n-Bit Adder/Subtractor

1. Introduction
In this experiment, students will be introduced to the concept of implementing iterative circuit with
repeated blocks/modules in Quartus II Software. They will also be introduced to the design of widely
used Multi-Function Circuit, namely Adder/Subtractor. Then implementing a 3-bit adder using Quartus II
13.1 software.

2. Objectives
By the end of this lab experiment, students will:
• Learn to design and implement an iterative circuit using Quartus II Software in both block diagram
schematic and Verilog programming language.
• Learn to design Multi-function circuits (adder/subtractor).

3. Iterative and Multi-Function Circuits

An iterative circuit is a way to break down a large system into smaller subsystems. In such circuit, a
common block of circuitry is repeated multiple times. Arithmetic operations like addition, subtraction,
multiplication, etc. are implemented using iterative circuits. In practical digital systems, it is necessary to
implement several functions as part of some large logic circuit. Circuits that implement these functions
can often be combined into a less-expensive single circuit with multiple outputs. An example of a multi-
function circuit is an Adder/Subtractor circuit.

In this experiment, an Adder/Subtractor circuit is broken down into subsystems and constructed in three
stages, as follows:

• Stage 1: Designing a Full Adder

• Stage 2: Designing an n-Bit Adder as an Iterative circuit using Full Adder
• Stage 3: Designing an Adder/Subtractor circuit as a Multi-Function circuit using n-Bit
Adder

Important Remarks:
• As multiple circuits are implemented, create a project with the name of lab4, then name
the top-level file as AddSub3.
• Make sure every design file has a different name when adding it to the same project.
• Make sure every design file is made as top-level entity before processing it.
3.1 Addition
Addition of two 1-digit binary numbers produces a 2-digit binary output. The two bits of result are
referred to as Sum and Carry, as shown below:

A B Carry Sum
0 + 0 = 0 0 → (0)
0 + 1 = 0 1 → (1)
1 + 0 = 0 1 → (1)
1 + 1 = 1 0 → (2)

• For the first 3 cases, Carry = ‘0’, and for the last case Carry = ‘1’
• A combinational circuit that performs the addition of two 1-digit binary numbers is called a Half
Adder.

3.2 Full Adder

When added numbers contain more digits, carry obtained from addition of lower order pair of digits is
added with next higher order pair of digits. The combinational circuit that performs the addition of two 1-
digit binary numbers, A and B, and a previous carry Cin, is called a Full Adder. Figure 1 shows an example
of a Full Adder operation, whereas the complete Truth Table of a Full Adder is illustrated in Table 1.

Figure 1: An Example of a Full Adder Operation

Table 1: Addition of two 1-bit variables (A and B) and Carry (Cin)

Inputs Outputs

Cin A B S Cout Cin

0 0 0 0 0 0

0 0 1 1 0 0

0 1 0 1 0 0

0 1 1 0 1 0

1 0 0 1 0 1

1 0 1 0 1 1

1 1 0 0 1 1

1 1 1 1 1 1
 • From the k-maps shown in Figure 2(a), the expression for Sum (S) can be written as:
S = A' B Cin' + A B' Cin' + A' B' Cin + A B Cin
• Alternative simpler expression for S can be derived from Table 1 by observing output S, which is
equal to 1 only for an odd number of inputs having the value 1. As this is the property of an XOR
function, then:
S=A B Cin.
• Expressions for Carry-Out (Cout) can be written as:
Cout = A B + A Cin + B Cin

Figure 2 (a): K-Map for S output Figure 2 (b): K-Map for Cout output

Problem Statement: Designing a Full Adder

Design a Full adder with three inputs (A, B, Cin), and two outputs (S, Cout). The logic expressions are:
S=A B Cin
Cout = A B + A Cin + B Cin
Figure 3 shows an outline of a Full Adder’s Verilog code, its block diagram and symbol.

1. Draw the logic circuit and write all the input/output signal names.
 2. Design this circuit using Quartus II, in Verilog HDL editor (with the name FA).
3. Analyze and Synthesize the circuit.
4. Create a symbol for the circuits.

module FA ( A, B, Cin, S, Cout );

input …... ... ,
output ………. ,
assign S = A ^ B ^ Cin ;
…
endmodule

Figure 3: An Outline of a Full Adder’s Verilog code, Its Block Diagram and Symbol

3.3 n-Bit Adder

As a rule, the addition of n-bit numbers requires an n-Bit Adder. An n-Bit Adder is an iterative circuit,
which is implemented by repeating the basic building block as shown in Figure 4. The circuit shown in the
figure is capable of adding two numbers, each consisting of n bits ( X = Xn-1 … X1 X0 and Y = Yn-1…Y1Y0 ).

Figure 4: Block Diagram of n-Bit Adder

• Right most FA performs X0 + Y0 + C0. This addition results in a Sum (S0) and a Carry-out (C1).
Carry (C1) is connected as an input to the second stage. C0 is always equal to logic zero.
• Although the first block can be substituted by a Half Adder circuit, for the sake of generality, we
use a Full Adder and ground the C0 input.
• Each Full Adder adds one bit from X with one bit from Y and a Carry-out from previous stage.
• Sum is an n+1-bit number ( Cn Sn-1 … S1 S0 ).
 Figure 5: An Example of a 4-Bit Addition

Problem Statement: Designing an n-Bit Adder

Design a 3-Bit Adder as an iterative circuit (Refer to Figure 4) to add two 3-bit numbers X (X2 X1 X0) and
Y (Y2 Y1 Y0).
1. Draw the block diagram of the 3-Bit Adder and write all the signal names in the block.

2. Design the circuit (with file name adder3) using Quartus II, in schematic capture using the
symbol of the full adder (FA).
3. Analyze and Synthesize the circuit.
4. Test the circuit by performing Functional Simulation.
5. Design the circuit (with the name Adder3) using Quartus II, in Verilog HDL editor using the
function FA implemented in the previous step.
6. Analyze and Synthesize the circuit.
7. Create a symbol for the circuit.
8. Add the symbol to block diagram schematic and connect the input and output
9. Analyze and synthesize
10. Test the design by performing functional simulation.
3.3.1 Iterative Circuit Design as Schematic Capture (Performed by the lab instructor and
observed by the students)

Step 1: Import the module FA

i. Open a new Block Diagram/Schematic File in the Graphic Editor window.

ii. Save the file as adder3.bdf and make sure to check the option “Add file to current project”.
iii. Double-click on any empty spot in the schematic file to enter a symbol and expand the “Project”
hierarchy in the “Symbol Window”. Select the symbol FA → click OK. The selected FA symbol
will appear in the Graphic Editor window.
iv. Create 3 instances of FA by holding the Ctrl key and dragging the chosen symbol with the mouse
left key pressed.
v. Add appropriate input and output ports names to your design.

Step 2: Connect the symbols in the diagram by drawing lines (wires)

i. When a schematic has more interconnections, it is better to connect symbols using name
association.
• Name association can be done by drawing small wires and writing the same
name at both ends of connection points.
• When the left mouse button is clicked on this small wire, make sure the name
box associated with that wire also turns BLUE indicating the name is correctly
assigned to the wire.
• After writing the name, make sure the writing is NOT GREEN. Green writing
means comments and will not be linked to the wire (will be ignored by the
program).
ii. A multibit variable like x {x2 x1 x0} is referred by the vector notation x[2..0] indicating the range
2 to 0.
• Each bit will have a separate name, like, x[2], x[1] and x[0].
• The square parenthesis is mandatory for every bit when referring to the bits of
a vector variable.
• Make sure to name your variables in small letter to distinguish them from the
Verilog design.
iii. Save your design.
3.3.2 Iterative Circuit Design as Verilog code (Implemented in the lab by the students)

i. Open a new Verilog File and Save the file as Adder3.v make sure to check the option “Add file to
current project”.

ii. ALWAYS make sure the module name (Adder3) is the same as the file name (Adder3.v), with no
spaces or special characters used.

iii. Type the code for 3-Bit Adder by completing the following program.
 iv. Save your design.

v. Analyze and Synthesize the design then create symbol.

vi. Create a block diagram schematic and save it with the name AddSub3.
vii. Add the symbol of Adder3 (created in the previous step) and connect all inputs and output
viii. Ff
ix. Test the design by performing Functional Simulation.

4. Multi-Function Circuit: Adder/Subtractor Circuit

4.1 Binary Subtraction
• The subtraction of binary numbers can be done by means of complement arithmetic.
• The subtraction ( A – B ) can be done by taking the 2's complement of B and adding it to A.
• The 2's complement can be obtained by taking the 1's complement and adding ‘1’ to the least
significant pair of bits.
• The 1's complement can be implemented with inverters. The value ‘1’ can be added to the sum
through input carry, i.e., C0.

Figure 6 (a): Direct Subtraction Figure 6 (b): Subtraction as Addition

4.2 n-Bit Adder/Subtractor Unit
The addition and subtraction operations can be combined into one circuit with one common binary
adder. The variables X and Y input to an adder for the two operations differ as shown in Table 2.

Table 2: Operands for an n-Bit Adder/Subtractor Circuit

Operation Operands input to an n-bit adder Cin

Addition X Y 0

Subtraction X Y’ 1

Table 3: Y with respect to Cin

Input Output
Relation
Cin Y YM

0 0 0
YM = Y
0 1 1

1 0 1
YM = Y’
1 1 0

• A two input Exclusive-OR (XOR) gate can be used for every bit of Y so that:
o For addition, Y is passed on as it is
o For subtraction, Y' is passed on
o Table 3 shows this relation
• The Cin input will be referred to as AddSub input, which in turn controls the operation, either
addition or subtraction.
o When AddSub = 0, the circuit is an adder
o When AddSub = 1, the circuit becomes a subtractor
 Figure 7: Block Diagram of n-Bit Adder/Subtractor

Problem Statement: Designing an Adder/Subtractor (Implemented by the lab

instructor and observed by the students)

Design a 3-bit adder/ subtractor (Ref Figure 4) to add/subtract two 3-bit numbers X (X2 X1 X0) and Y
(Y2Y1Y0).
1. Draw the block diagram of the 3-Bit Adder/Subtractor and write all the signal names in the
block.
2. Prepare a Truth Table with 2 test cases for Addition, and 2 test cases for Subtraction.

3. Design the circuit (with file name AddSub3) using Quartus II, as a schematic capture.
4. Perform Full Compilation for the circuit.
5. Perform Functional Simulation and verify the Test cases.
Student Name: Date:
Student ID:

Lab Exercise # 5

Problem Statement:
Implement the Problem Statements illustrated in the experiment description.

Procedure:
1. Follow the Design Procedure presented in the experiment description.
2. Synthesize your designs (refer to Section 3.2.5 in Lab Session#3).
3. Perform a Functional Simulation for every design (refer to Section 3.4 in Lab Session#3) to test
your design for all the possible test cases.
4. Submit the compressed project folder on OCS. (Mandatory)

Ask your engineer to check your results, write his/her comments and sign below:

………………………………………………………………………………………………………………………...…………………………...……….
……………………………………………………………………………………………………………………...………………………...…………….
…………………………………………………………………………………………………………………...…………………………………………

Engineer Signature
……..……………..

Attachments: (optional)
Please attach with the lab exercise sheet printouts of the files indicated below. Don't forget to
write your Name and ID Number as comments in every file before printing.

1. Schematic Capture or Verilog file of Full Adder.

2. Schematic Capture or Verilog file of 3-bit Adder.
3. Schematic Capture of 3-Bit Adder/Subtractor.
4. Functional Simulation Waveform File (*.sim.vwf file).