Lab Session # 1

Introduction to QUARTUS II Software

1. Introduction
In this experiment, you will get introduced to Quartus II Web Edition Software (version 13.1) and use it
to design digital circuits and verify their functionalities.

2. Objectives
By the end of this lab experiment, students will be able to:
• Create a project.
• Enter a design as a schematic diagram using Quartus II graphic editor.
• Enter a design in hardware description language Verilog using a Text editor.
• Synthesize a circuit from the schematic diagram / Verilog code.
• Simulate the designed circuit using the waveform editor to verify its functionality.
• Create a symbol from design files.

3. Implementation Using Quartus II Software

At each stage in the design flow for logic circuits, Quartus II Software generates files with different
extensions, as listed in Table 1. To hold the design files for this lab, create a new folder for every lab
session in the Documents folder.
Table 1: Files Generated by Quartus

Stage File Extension Icon Expansion

.qpf
Quartus Project File
(in main project Folder)
Creation of Project
.qsf
(in main project Folder) Quartus Settings File

.bdf
(in main project Folder) Block Design File

Design Entry
.v
(in main project Folder) Verilog File

.map.rpt
Analysis & Synthesis Mapping report file
(in “output_files” Folder)

.vwf
(in main project Folder) Vector Waveform File
Functional
Simulation
.sim.vwf
(in “simulation/qsim” Folder) Vector Waveform File

.bsf
Symbol (in main project Folder) Block Symbol File
Each logic circuit, or subcircuit, being designed with Quartus II Software is called a Project. The software

works on one project at a time and keeps all information for that project in a single directory (folder) in

the file system. To begin a new logic circuit design, the first step is to Create a Project.

3.1 Starting Quartus II Software and Creating a Project ( .qpf File)

1. Start the Quartus II software by clicking on the shortcut created on the Desktop.
2. If the shortcut does not exist on the Desktop, click on the Start Menu, then on All
Programs/Apps, and select Quartus II 13.1 (32-bit).
3. The software information/upgrade page (Figure 1) will appear for few seconds, then the
software main interface will be displayed (Figure 2).

Figure 1: Software Information/Upgrade Page

Figure 2: Software Main Interface

4. Close the Getting Started window (if any).
5. To start a New Project, you can access the New Project Wizard either from the software main
interface (Figure 2), or by clicking on File (top menu bar) → New Project Wizard (Figure 3).

Figure 3: Acessing the New Project Wizard

6. The first page in the New Project Wizard is an Introduction (Figure 4). You can simply skip it →
Next. If you don’t want to view this introduction page again, you can check the small box at the
bottom of this page before you click Next.

Figure 3: Introduction of the New Project Wizard

7. Choose the working directory, for example, C:\264\Lab1, or you can browse to any other
folder/directory of your choice. Make sure the directory name follows the naming rules as
follows:
a. It should not be lengthy (maximum eight characters)
b. Doesn’t have space in it.
c. It must be alphanumeric which means starting with alphabet, may include numbers and
underscore character only.
8. Type a name for the project, for example, Lab1. Note that project name must follow the same
rules of the directory name as explained in the previous point.
9. Same name (Lab1) will automatically appear for the top-level design entity. You can either keep
it as it is, or you can change the top-level design entity by typing a new design file name, for
example, ex1 (Figure 4) → Click on Next.

Figure 4: Directory, Name and Top-Level Entity of the New Project

10. A new window opens for additional user-specified design files. As there are no other design files
to be added, just leave it blank (Figure 5) → Click on Next.

Figure 5: Adding Already Exsiting Design Files to the New Project

11. In the new window for the Family & Device Settings, choose the Device Family Cyclone IV E and
the Device Name EP4CE115F29C7, which is the Cyclone Device on the board (Figure 6) → Click
on Next.

Figure 6: Family & Device Settings for the New Project

12. A new window opens for third-party tools. As there are no such tools to be added, just leave it as
it is (Figure 7) → Click on Next.
 Figure 7: Tools Settings for the New Project

13. A new window with the summary of the chosen settings will appear (Figure 8) → Click on Finish.

Figure 8: Summary of the Chosen Settings for the New Project

14. Main Quartus window appears. Verify the new project name Lab1, the top-level entity name ex1,
as well as the project directory/path location appears in the display title bar (Figure 9).

Figure 9: Display Title

3.2 Design Entry - Schematic Capture Using Graphic Editor (Circuitg Block)

Problem Statement 1:

Consider the basic logic gates:

• AND logic gate
• OR logic gate
• NOT logic gate
Use Quartus II software to implement these gates with block diagram schematic. Then test designs using
waveforms to ensure correctness.

3.2.1 Create the Block Diagram/Schematic File ( .bdf File)

i. Select File (top menu bar) → New (Figure 11) → Choose Block Diagram/Schematic
File (Figure 12) → Click on OK. This opens the Graphic Editor window with the name
Block1.bdf.

Figure 11: Create New File

 Figure 12: Create New Block Diagram/Schematic File

ii. Select File (from top menu bar) → Save As. Save as type choose Block
Diagram/Schematic File (*.bdf).

iii. In the box labeled File name check the default name as ex1.

iv. Put a checkmark in the box Add file to current project (Figure 13) → Click on Save.

Figure 13: Save the New Block Diagram/Schematic File as ex1.bdf

v. The Graphic Editor window name changes from Block1.bdf to ex1.bdf (Figure 14).

Figure 14: The New Block Diagram/Schematic File saved as ex1.bdf

3.2.2 Import Logic-Gate Symbols

i. Double-Click on the blank space in the Graphic Editor window.
ii. Expand the hierarchy in the c:/altera/13.1/quartus/libraries/ box → choose
primitives → logic. Select the required gate (Figure 15) → Click on OK.

Figure 15: Inserting a Symbol

iii. A symbol in the Graphic Editor window can be moved by clicking on it and dragging it to
a new location with the mouse button Pressed. Repeat this step for all the logic gates
required for the design.

3.2.3 Import Input and Output Symbols

i. Double-Click on any blank space in the Graphic Editor window.
 ii. Expand the hierarchy in the c:/altera/13.1/quartus/libraries/ box → choose
primitives → pin.
iii. Import instances of the Input port and Output port.
iv. Point to the word pin_name on the input/output symbol and Double-Click on the
mouse → Type the new desired pin name → Click on OK.
v. Enter the input port names x and y and the output port names xandy, xory and notx.

3.2.4 Connect the Symbols

i. Move the mouse cursor to the points or gates that you want to draw connection to or
from.
ii. When the mouse cursor changes shape to (+), hold the left button of the mouse and
move the cursor then drop to the desired point.
iii. Continue the procedure until all connections are done (Figure 16)

Figure 16: Complete Block Diagram/Schematic File Design

3.2.5 Perform Analysis and Synthesis (.map.rpt File)

i. Save the ex1.bdf file by clicking on the Floppy Icon in the top menu bar.
ii. Make ex1.bdf as the Top-Level Entity in the design hierarchy.
• View the Project Navigator, on the left side of the Quartus II Software window,
by clicking on View (in the top menu bar) → Utility Windows → Project
Navigator.
• In the Project Navigator, select the Files tab.
• Check the listed project elements and files.
• Select the desired design file (ex1.bdf) → Right-Click on it → choose Set as
Top-Level Entity (Figure 17).
 Figure 17: Set Design File as Top-Level Entity

iii. Click on Start Analysis & Synthesis icon on the top menu bar (Figure 18).

Figure 18: Processing Icons of the Top Menu Bar

iv. If there are no errors, a pop-up window appears stating Analysis & Synthesis was
successful (Figure 19).
 Figure 19: Successful Analysis & Synthesis

3.2.6 Schematic Error

• In the case of an error, a message corresponding to an error is displayed in RED color in
the Messages window.
• Double-Clicking on an error message will highlight the offending part of the circuit in
the Graphic Editor window.
• Similarly, some warning messages may also appear. Their details can be explored in the
same way as in the case of error messages.

3.3 Design Entry - Verilog HDL Using Text Editor (Circuitv Block)
Verilog HDL (referred in short as Verilog) is a hardware description language that has a syntax similar to
C programming language and is used to write descriptions of large circuits, in a relatively compact form.

Problem Statement 2:

Consider the basic logic gates:

• AND logic gate
• OR logic gate
• NOT logic gate
1. Design this circuit using Verilog HDL (ex2) and Synthesize it.
2. Test and verify its functional correctness.
3. Create a symbol for ex2.
3.3.1 Create a Verilog HDL File (.v)
i. Select File (top menu bar) → New → choose Verilog HDL File (Figure 20) → Click on
OK.

Figure 20: Create New Verilog HDL File

ii. Select File (top menu bar) → Save As. In Save as type choose Verilog HDL File (*.v).
iii. Change the default name Verilog1 and type the verilog module name ex2 It is
mandatory that the module name and the verilog file names are Identical.
iv. Put a checkmark in the box Add file to current project (Figure 21) → Click on Save.

Figure 21: Save the New Verilog HDL File as ex2.v

v. A Text Editor window opens and the name of the file ex2.v appears at the top.
 vi. Type in the verilog code shown below.

// ex1 in Verilog

module ex2 (a,b, aandb, aorb, nota);

input a, b;
output aandb, aorb, nota;
assign aandb = a & b;

assign aorb = a | b ;

assign aorb = ~a ;

endmodule

vii. Note that the entire code is Case Sensitive.

viii. Words in Blue (such as module, input, output, assign, endmodule) are keywords
ix. Text starting with ( // ) indicates that this is comments and will be colored in
Green.
x. Save the ex2.v File (Figure 22).

Figure 22: Complete Verilog HDL Design (File saved as module name)

3.3.2 Perform Analysis and Synthesis (.map.rpt File)

• Follow same steps as explained in Section 3.2.5, but on the new design file now which is
(ex2.v).
• Don’t forget to set ex2.v as Top-level Entity.

Note: The top-level design entity is always the file that will be analyzed, compiled,
simulated or processed (i.e., a symbol is created for it). Make sure correct design file is
always set as Top-level entity.

3.4 Testing the Functionality of the Designed Circuit

The functional correctness of the designed circuit can be tested by applying the test vectors
corresponding to every row of the truth table and checking whether the output logic values exactly
matches the ones in the truth table. For the sake of simplicity, the following steps test the Verilog HDL
design file Circuitv.v for the following cases:
Table 2: Truth table for the base logic gates

input output

X Y XandY XorY NotX

0 0 0 0 1

0 1 0 1 1

1 0 0 1 0

1 1 1 1 0

3.4.1 Create a Waveform (.vwf File – University Program VWF) for the Design
i. Select File (top menu bar) → New → University Program VWF (Figure 23) → Click on
OK.

Figure 23: Create New Waveform File (.vwf)

ii. The Simulation Waveform Editor window will appear showing a new Waveform.
iii. Select File (top menu bar) → Save As and select Save as type University Program VWF
(*.vwf) and type the name ex2 (as the design file name), or simply leave its name as
Waveform (Figure 24).
• No need for the Waveform file to have the same name as the design file
(Schematic/Verilog).
iv. Click on Save.
 Figure 24: Saving the Waveform File (Waveform.vwf)
v. Set the desired time for the simulation by choosing Edit (top menu bar) → End Time →
Enter the End time required, giving 100ns for each test condition/case [End Time = # of
test conditions/cases * 100ns]. For Table 2, we need (4 rows * 100 ns = 400ns) → Click
on OK.
vi. Set the time dedicated for each test condition/case (indicated as Grid Size). Select Edit
(top menu bar) → Grid Size → Enter Period as 100 ns.
vii. To view the complete Waveform, select View (top menu bar) → Fit in Window.
viii. Double-Click on the empty space below Name in the Simulation Waveform Editor
window (Left Side).
ix. The Insert Node or Bus window will appear (Figure 25) → Click on Node Finder.

Figure 25: Inserting Node or Bus Window

x. The Node Finder window will appear (Figure 26) → In the Filter select Pins:all → List.
xi. All the nodes in the circuit will appear on the left side of the bottom window.
xii. Click on the arrows in the middle of the window to select the required nodes, which will
move to the other (right) side (Figure 26) → Click on Ok.
 Figure 26: Node Finder Window

xiii. The Node Finder window will appear again with **Multiple Items** displayed as the
name of the node → Click on Ok. The nodes will appear in the waveform window.
xiv. Rearrange the nodes and make sure that the waveforms are in the same order from Top
to bottom as the respective variables appear in the Truth Table from left to right.
xv. You can group the input/output signals as follows:
• Select the first input signal at the top of the Waveform. Hold the shift key and
click on the rest of the input signals in the waveforms. Selected input signals will
be highlighted.
• Click on the right mouse button and select Grouping → Group.
• Enter a name for the inputs and Select the Radix as Binary.
• Repeat the steps for output signals in the waveforms.
xvi. To enter the value of any input signal, select the time interval 0 to 100 ns, by clicking the
mouse at the start of the interval and dragging it to its end. This highlights the selected
interval.
xvii. Click on the ‘0’ or ‘1’ or ‘?’ icon on the top side of the frame to set the value of the input to
low logic, high logic, or arbitrary value, respectively. Make sure the correct interval is
shown (0 to 100 ns) and the Radix is Binary.
xviii. Enter the required value for each interval.
xix. After entering all the values for the input signals, save the file → Select File (top menu
bar) → Click on Save.

3.4.2 Performing a Functional Simulation

The Quartus II Simulator takes the inputs from the University Program VWF file created
(Waveform.vwf) in the main project folder, and generates the outputs in a new Read-Only
University Program VWF file with the same Project Name (Lab3.sim.vwf) in a sub-folder
(\simulation\qsim\) in the main project folder (i.e., C:\Users\DLL\Documents\Lab3\
simulation\qsim\). To perform the Functional Simulation:

i. In the Simulation Waveform Editor window, select Simulation (top menu bar) → Click
on Run Functional Simulation (Figure 27).

Figure 27: Running the Functional Simulation

ii. A pop-up window will appear to show the progress of the simulation, then indicate the
successful completion of the simulation by displaying the Completed Successfully
message (Figure 28).

Figure 28: Successful Completion of the Simulation

 iii. The results of the Functional Simulation will be displayed in a Read-Only University
Program VWF file (Figure 29) with the same Project Name (Lab3.sim.vwf) that is
located in a sub-folder (\simulation\qsim\) in the main project folder (i.e.,
C:\Users\DLL\Documents\Lab3\ simulation\qsim\)

Figure 29: Results of the Simulation

iv. Check that the output S1 and S2 are as specified in the truth table for every row of the
Table, whereas every column in the Waveform represents a test condition/case (row) in
a truth table.

3.5 Creating a Symbol (.bsf File)

Creating a symbol for any design file (Block Diagram/Verilog HDL) allows you to use a symbol
representation for the designed circuit in designing another bigger circuit with the use of the symbol
created. To create a symbol for any design file (Block Diagram/Verilog HDL):
1. Perform Analysis and Synthesis on the desired design file (ex2.v) to ensure there are no errors
in the design file.
• Refer to Section 3.2.5
• Make sure the design file is the current Top-Level Entity
2. Click on the tab for the desired design file (ex2.v) file to make this file as the active window
(otherwise you will find the option in the following step disabled!! As in Figure 30).

Figure 30: Disabled List

3. Choose File (top menu bar) → Create/Update → Create Symbol Files for Current File (Figure
31).

Figure 31: Creating a Symbol for the Design File (Circuitv.v)

4. The Messages box at the bottom of the window will show the text in Figure 32, indicating the
successful creation of the symbol file.

Figure 32: Succssful Creation of the Symbol File

5. The symbol can be found under the Project branch when trying to insert a symbol in a graphical
design file in the same project (Figure 33).

Figure 31: Creating a Symbol

Student Name: Date:
Student ID:

Lab Exercise # 1

Problem Statement:
Perform the Functional Simulation for the designed circuit to test it for all the possible logic conditions.

Procedure:
1. Create a Block Diagram/Schematic design file Circuitg.bdf for the circuit (refer to Section 3.2).
2. Synthesize it (refer to Section 3.2.5).
3. Perform a Functional Simulation to test Circuitg.bdf for the following logic conditions. (refer to
Section 3.4)

Table 3: Truth Table for the Given Equation

Inputs Outputs

P Q R S1 S2

0 0 0 0 1

0 0 1 0 1

0 1 0 0 1

0 1 1 1 1

1 0 0 1 1

1 0 1 1 1

1 1 0 0 0

1 1 1 1 0

4. Create a Verilog HDL design file Circuitv.bdf for the circuit (refer to Section 3.3.1).
5. Synthesize it (refer to Section 3.3.2).
6. Create a Symbol for this module (refer Section 3.5).
7. Print your design files and simulation waveforms.

Ask your engineer to check your results, write his/her comments and sign below:

………………………………………………………………………………………………………………………...…………………………...……….
……………………………………………………………………………………………………………………...………………………...…………….
…………………………………………………………………………………………………………………...…………………………………………

Engineer Signature
……..……………..
Attachments:
Please attach with the lab exercise sheet printouts of the files indicated below. Don't forget to
write your Name and ID Number as comments in every file before printing.

1. Graphical design file (*.bdf file)

2. Symbol file (*.bsf)
3. Verilog code (*.v file).
4. Waveform file (*.sim.vwf file)