Section 5.

The
The ADSP-2100
ADSP-2100 Family
Family Core
Core
Architecture
Architecture IIII

a 5-1
 ADSP-2100
ADSP-2100 Family
Family Data
Data Address
Address
Generators
Generators
Instruction
Register

Data Address Data Address

Program
Generator #1 Generator #2
Sequencer

14
PMA Bus

14
DMA Bus

24
PMD Bus

Bus Exchange
16
DMD Bus

Input Registers Input Registers Input Registers

ALU MAC SHIFTER

Output Registers Output Registers Output Registers

16
R Bus

5-2
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 Data
Data Address
Address Generator
Generator (DAG)
(DAG)
Operations
Operations
•• Registered
Registered Indirect
Indirect Addressing
Addressing

•• Automatic
Automatic Post-Modify
Post-Modify of
of Address
Address

•• Circular
Circular Buffering
Buffering

•• DAG
DAG 11 Fetches/Stores
Fetches/Stores to
to Data
Data Memory
Memory

•• DAG
DAG 22 Fetches/Stores
Fetches/Stores to
to Data
Data or
or Program
Program Memory
Memory

•• Bit-Reversal
Bit-Reversal for
for FFT
FFT Support
Support (DAG
(DAG 11 Only)
Only)

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Data
Data Address
Address Generator
Generator Block
Block Diagram
Diagram
DMD BUS

FROM MUX
INSTRUCTION
2 14 14 14 14
FROM
INSTRUCTION
2
L I M
REGISTERS MODULUS REGISTERS REGISTERS
4 x 14 LOGIC 4 x 14 4 x 14

14 ADD

BIT
REVERSE

DAG1 ONLY

ADDRESS
5-4
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 DAG
DAG Features
Features
•• Data
Data Fetch/Store/Execute
Fetch/Store/Execute Simultaneous
Simultaneous with
with Arithmetic
Arithmetic
Instructions
Instructions
•• Two
Two DAGs
DAGs inin Processors
Processors
•• Four
Four Index
Index Registers
Registers per
per DAG
DAG
•• Four
Four Modify
Modify Registers
Registers per
per DAG
DAG
•• Four
Four Length
Length Registers
Registers per
per DAG
DAG
•• II (Index
(Index Registers)
Registers)
–– Contains
Contains address
address of
of data
data to
to be
be accessed
accessed
•• M
M (Modify
(Modify Registers)
Registers)
–– Used
Used to
to post-modify
post-modify index
index value
value
–– Can
Can be any 14-bit value, positive or
be any 14-bit value, positive or negative
negative
•• LL (Length
(Length Registers)
Registers)
–– Used
Used with
with circular
circular buffering
buffering
Notes:
Notes:
–– Within
Within aa DAG,
DAG, any
any modify
modify register
register can can bebe used
used with
with any
any index
index register
register
–– Length registers are tied to their corresponding index
Length registers are tied to their corresponding index registers registers
–– Length
Length registers
registers are
are not
not initialized
initialized at at power-up,
power-up, and
and must
must bebe set
set prior
prior to
to corresponding
corresponding index
index
register use
register use
–– Length
Length registers
registers must
must bebe set
set to
to 00 ifif circular
circular buffers
buffers are
are not
not used
used
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 DAG
DAG Operation
Operation

Contents
Contents of
of the
the selected
selected II register
register
I placed
placed on
on the
the DMA
DMA oror PMA
PMA bus
bus

The
The value
value contained
contained in in the
the specified M register
specified M register
M is
is then
then added
added to
to the
the II register
register

The
The resultant
resultant value
value isis checked
checked against
against the
the
I+M corresponding
corresponding L L register
register (if L == 0),
(if L 0), and
and II is
is
updated
updated with
with (I M) modulo
(I ++ M) modulo L. L.

5-6
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 Example
Example DAG
DAG Instructions
Instructions
AX0
AX0 == DM(0x3800);
DM(0x3800); /*
/* Load
Load AX0
AX0 with
with the
the contents
contents of
of address
address */
*/
/*
/* 0x3800.
0x3800. ThisThis is
is aa data
data Memory
Memory READ
READ
/*
/* with
with aa direct
direct address)
address) */ */

I0=0x3800;
I0=0x3800; /*
/* Setup
Setup I,M
I,M and
and LL registers
registers of
of DAG1
DAG1 */
*/
L0=0;
L0=0; /*
/* L0=0,
L0=0, therefore
therefore this
this buffer
buffer is
is NOT
NOT circular
circular */
*/
M0=1;
M0=1;
AX0
AX0 == DM(I0,
DM(I0, M0);
M0); /*
/* Data
Data Memory
Memory READ
READ (Indirect
(Indirect Address)
Address) */
*/

AY1
AY1 == DM(I4,
DM(I4, M7);
M7); /*
/* Data
Data Memory
Memory READ
READ (Indirect
(Indirect Address)
Address) */
*/
/*
/* using
using DAG2
DAG2 */
*/
AX1
AX1 == PM(I4,
PM(I4, M7);
M7); /*
/* Program
Program Memory
Memory READ
READ (Indirect
(Indirect Address)
Address) */
*/
MODIFY
MODIFY (I4,
(I4, M5);
M5); /*
/* Add
Add the
the value
value in
in M5
M5 to
to I4
I4 */
*/

a
 More
More Example
Example DAG
DAG Instructions
Instructions
/*Dual
/*Dual memory
memory READ
READ */
*/

AX1
AX1 == DM(I2,M3),
DM(I2,M3), AY0
AY0 == PM(I4,M7);
PM(I4,M7);

/*
/* MAC
MAC instruction
instruction with
with DATA
DATA and
and Program
Program Memory
Memory READ
READ */
*/

MR=MR+MX0
MR=MR+MX0 ** MY0
MY0 (SS),
(SS), MX0
MX0 == DM(I2,M2),
DM(I2,M2), MY0
MY0 == PM(I6,M6);
PM(I6,M6);

Note:
Note: LL registers
registers must
must be
be 00 ififcircular
circular buffers
buffersare
arenot
not used
used

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 DAG
DAG Instructions
Instructions
Load / Store Instructions

Data Memory Program Memory

dreg = DM(ix, mx); dreg = PM(ipx, mpx);
DM(ix,mx) = dreg; PM(ipx,mpx) = dreg;
DM(ix,mx) = <data>;
DM(<address>) = dreg;
dreg = DM(<address>);
ix = [I0, I1, I2, I3] ipx = [I4, I5, I6, I7]
mx = [M0, M1, M2, M3] mpx =[M4, M5, M6, M7]

OR

ix = [I4, I5, I6, I7]

mx = [M4, M5, M6, M7]

dreg = [AX0, AX1, AY0, AY1, MX0, MX1, MY0, MY1, AR, MR0, MR1, MR2, SI, SE, SR0, SR1]

- DAG operations can be combined with ALU, MAC or shifter instructions

- Length registers must be initialized - set to zero if not used
- All DAG operations execute in a single instruction cycle
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 Modulo
Modulo Addressing
Addressing Example
Example
Base Address = 0x0030
I0 = Current Address
M0 = Modify Value (3)
L0 = Buffer Length (8)
0x0030 |M| < L

I0
Address Sequence

0x0037 30
31
32
33
34
35
36
37 5 - 10
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 Modulo
Modulo Addressing
Addressing Code
Code Example
Example
.VAR/DM/CIRC Buff[8]; /* Define Buffer */

I0 = ^Buff; /* I0 = Start address of Buff */

L0 = %Buff; /* L0 = Length of Buff */
M0 = 3; /* Modify value = 3 */
AX0 = DM (I0, M0); /* Fetch data at address 30 */
AY0 = DM (I0, M0); /* Fetch data at address 33 */
AX1 = DM (I0, M0); /* Fetch data at address 36 */
AY1 = DM (I0, M0); /* Fetch data at address 31 */

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Bit
Bit Reversal
Reversal with
with the
the ADSP-2100
ADSP-2100 Family
Family
• Used only in FFT routines
• Only available with DAG1
• Enabled by setting bit 1 of MSTAT register or using the instruction:

ENA BIT_REV;

• Reverses all 14 bits of address

A13 A0
normal order: 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0x28

A13 A0
bit-reversed: 0 0 0 1 0 1 0 0 0 0 0 0 0 0
0x500

• For a buffer of size 2^N, set M register to 2^(14-N)

i.e. a buffer of size 8 = 2^3 locations, M = 2^(14-3) = 2^11 = 2048 =
0x800

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 Bit
Bit Reversal
Reversal Example
Example
Buff_1 Address Buff_2
placed
.VAR/DM/ABS=0X28 BUFF_1[8]; Addr Data I Value
on DMA bus Addr Data
.VAR/DM BUFF_2[8]; 0x28 0 I0=0x0500 ---> 0x0028 0x30 0
/* Linker placed buff_2 at 0x30 */
ENA BIT_REV; 0x29 1 I0=0x0D00 ---> 0x002C 0x31 4
I0=0X500;
M0=0X800; 0x2A 2 I0=0x1500 ---> 0x002A 0x32 2
L0=0;
I4=^BUFF_2; 0x2B 3 I0=0x1D00 ---> 0x002E
0x33 6
L4=%BUFF_2;
M4=1; 0x2C 4 I0=0x2500 ---> 0x0029
0x34 1
CNTR=8;
DO COPY UNTIL CE; 0x2D I0=0x2D00 ---> 0x002D 0x35
5 5
AX0=DM(I0,M0);
COPY: DM(I4,M4)=AX0; 0x2E 6 I0=0x3500 ---> 0x002B 0x36 3
DIS BIT_REV;
0x2F 7 I0=0x3D00 ---> 0x002F 0x37 7

I register must be intialized with the bit reversed value of the starting address of the buffer (You must
calculate or use the simulator to determine the value). The starting address for the data array must be an
integer multiple of the FFT size (0, N, 2N .....)
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 DAGs
DAGs Mini-Quiz
Mini-Quiz
DM(0x3800) 0x1234 Write the ADSP- 2100 instructions
0x1234 to find the sum of the N = 5 numbers
0x1234 stored in Data Memory.
0x1234
0x1234 Hint!
Data Memory • Use multifunction instructions
• Nine instructions total
• Three instructions are repeated

Questions:

1) How many instructions cycles are required?

2) How many instruction cycles are required if N=100?

3) Is this an efficient use of the processor?

5 - 14
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