PIC18(L)F2X/45K50

6.6.3.1 FSR Registers and the INDF
Operand
At the core of indirect addressing are three sets of reg-
isters: FSR0, FSR1 and FSR2. Each represents a pair
of 8-bit registers, FSRnH and FSRnL. Each FSR pair
holds a 12-bit value, therefore, the four upper bits of the
FSRnH register are not used. The 12-bit FSR value can
address the entire range of the data memory in a linear
fashion. The FSR register pairs, then, serve as pointers
to data memory locations.
Indirect addressing is accomplished with a set of
Indirect File Operands, INDF0 through INDF2. These
can be thought of as “virtual” registers: they are
mapped in the SFR space but are not physically
implemented. Reading or writing to a particular INDF
register actually accesses its corresponding FSR
register pair. A read from INDF1, for example, reads
the data at the address indicated by FSR1H:FSR1L.
Instructions that use the INDF registers as operands
actually use the contents of their corresponding FSR as
a pointer to the instruction’s target. The INDF operand
is just a convenient way of using the pointer.
Because indirect addressing uses a full 12-bit address,
data RAM banking is not necessary. Thus, the current
contents of the BSR and the Access RAM bit have no
effect on determining the target address.
6.6.3.2 FSR Registers and POSTINC,
POSTDEC, PREINC and PLUSW
In addition to the INDF operand, each FSR register pair
also has four additional indirect operands. Like INDF,
these are “virtual” registers which cannot be directly
read or written. Accessing these registers actually
accesses the location to which the associated FSR
register pair points, and also performs a specific action
on the FSR value. They are:
• POSTDEC: accesses the location to which the
FSR points, then automatically decrements the
FSR by 1 afterwards
• POSTINC: accesses the location to which the
FSR points, then automatically increments the
FSR by 1 afterwards
• PREINC: automatically increments the FSR by 1,
then uses the location to which the FSR points in
the operation
• PLUSW: adds the signed value of the W register
(range of -128 to +127) to that of the FSR and
uses the location to which the result points in the
operation.
In this context, accessing an INDF register uses the
value in the associated FSR register without changing
it. Similarly, accessing a PLUSW register gives the
FSR value an offset by that in the W register; however,
neither W nor the FSR is actually changed in the
operation. Accessing the other virtual registers
changes the value of the FSR register.

FIGURE 6-7: INDIRECT ADDRESSING

000h
Using an instruction with one of the ADDWF, INDF1, 1 Bank 0
indirect addressing registers as the 100h
operand.... Bank 1
200h
Bank 2
300h
...uses the 12-bit address stored in FSR1H:FSR1L
the FSR pair associated with that
7 0 7 0
register.... Bank 3
x x x x 1 1 1 0 1 1 0 0 1 1 0 0 through
Bank 13

...to determine the data memory

location to be used in that operation.
In this case, the FSR1 pair contains E00h
ECCh. This means the contents of Bank 14
location ECCh will be added to that F00h
of the W register and stored back in Bank 15
ECCh. FFFh
Data Memory

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Operations on the FSRs with POSTDEC, POSTINC
and PREINC affect the entire register pair; that is, roll-
overs of the FSRnL register from FFh to 00h carry over
to the FSRnH register. On the other hand, results of
these operations do not change the value of any flags
in the STATUS register (e.g., Z, N, OV, etc.).
The PLUSW register can be used to implement a form
of indexed addressing in the data memory space. By
manipulating the value in the W register, users can
reach addresses that are fixed offsets from pointer
addresses. In some applications, this can be used to
implement some powerful program control structure,
such as software stacks, inside of data memory.
6.6.3.3 Operations by FSRs on FSRs
Indirect addressing operations that target other FSRs
or virtual registers represent special cases. For
example, using an FSR to point to one of the virtual
registers will not result in successful operations. As a
specific case, assume that FSR0H:FSR0L contains
FE7h, the address of INDF1. Attempts to read the
value of the INDF1 using INDF0 as an operand will
return 00h. Attempts to write to INDF1 using INDF0 as
the operand will result in a NOP.
On the other hand, using the virtual registers to write to
an FSR pair may not occur as planned. In these cases,
the value will be written to the FSR pair but without any
incrementing or decrementing. Thus, writing to either
the INDF2 or POSTDEC2 register will write the same
value to the FSR2H:FSR2L.
Since the FSRs are physical registers mapped in the
SFR space, they can be manipulated through all direct
operations. Users should proceed cautiously when
working on these registers, particularly if their code
uses indirect addressing.
Similarly, operations by indirect addressing are generally
permitted on all other SFRs. Users should exercise the
appropriate caution that they do not inadvertently change
settings that might affect the operation of the device.
6.7 Data Memory and the Extended
Instruction Set
Enabling the PIC18 extended instruction set (XINST
Configuration bit = 1) significantly changes certain
aspects of data memory and its addressing. Specifi-
cally, the use of the Access Bank for many of the core
PIC18 instructions is different; this is due to the intro-
duction of a new addressing mode for the data memory
space.
What does not change is just as important. The size of
the data memory space is unchanged, as well as its
linear addressing. The SFR map remains the same.
Core PIC18 instructions can still operate in both Direct
and Indirect Addressing mode; inherent and literal
instructions do not change at all. Indirect addressing
with FSR0 and FSR1 also remain unchanged.
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6.7.1 INDEXED ADDRESSING WITH
LITERAL OFFSET
Enabling the PIC18 extended instruction set changes
the behavior of indirect addressing using the FSR2
register pair within Access RAM. Under the proper
conditions, instructions that use the Access Bank – that
is, most bit-oriented and byte-oriented instructions –
can invoke a form of indexed addressing using an
offset specified in the instruction. This special
addressing mode is known as Indexed Addressing with
Literal Offset, or Indexed Literal Offset mode.
When using the extended instruction set, this
addressing mode requires the following:
• The use of the Access Bank is forced (‘a’ = 0) and
• The file address argument is less than or equal to
5Fh.
Under these conditions, the file address of the
instruction is not interpreted as the lower byte of an
address (used with the BSR in direct addressing), or as
an 8-bit address in the Access Bank. Instead, the value
is interpreted as an offset value to an Address Pointer,
specified by FSR2. The offset and the contents of
FSR2 are added to obtain the target address of the
operation.
6.7.2 INSTRUCTIONS AFFECTED BY
INDEXED LITERAL OFFSET MODE
Any of the core PIC18 instructions that can use direct
addressing are potentially affected by the Indexed
Literal Offset Addressing mode. This includes all
byte-oriented and bit-oriented instructions, or almost
one-half of the standard PIC18 instruction set.
Instructions that only use Inherent or Literal Addressing
modes are unaffected.
Additionally, byte-oriented and bit-oriented instructions
are not affected if they do not use the Access Bank
(Access RAM bit is ‘1’), or include a file address of 60h
or above. Instructions meeting these criteria will
continue to execute as before. A comparison of the
different possible addressing modes when the
extended instruction set is enabled is shown in
Figure 6-8.
Those who desire to use byte-oriented or bit-oriented
instructions in the Indexed Literal Offset mode should
note the changes to assembler syntax for this mode.
This is described in more detail in Section 27.2.1
“Extended Instruction Syntax”.
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 PIC18(L)F2X/45K50
FIGURE 6-8: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND
BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED)

EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff)

000h
When ‘a’ = 0 and f  60h:
060h
The instruction executes in
Direct Forced mode. ‘f’ is inter- Bank 0

preted as a location in the 100h

Access RAM between 060h 00h
Bank 1
and 0FFh. This is the same as through 60h
locations F60h to FFFh Bank 14
Valid range
(Bank 15) of data memory. for ‘f’
Locations below 60h are not FFh
F00h Access RAM
available in this addressing
Bank 15
mode.
F60h
SFRs
FFFh
Data Memory

When ‘a’ = 0 and f5Fh: 000h

The instruction executes in
Indexed Literal Offset mode. ‘f’ 060h
Bank 0
is interpreted as an offset to the
100h
address value in FSR2. The 001001da ffffffff
two are added together to Bank 1
obtain the address of the target through
Bank 14
register for the instruction. The
address can be anywhere in FSR2H FSR2L
the data memory space.
F00h
Note that in this mode, the Bank 15
correct syntax is now: F60h
ADDWF [k], d SFRs
where ‘k’ is the same as ‘f’. FFFh
Data Memory

BSR
When ‘a’ = 1 (all values of f): 000h 00000000

The instruction executes in

060h
Direct mode (also known as
Bank 0
Direct Long mode). ‘f’ is inter- 100h
preted as a location in one of
the 16 banks of the data Bank 1 001001da ffffffff
memory space. The bank is through
Bank 14
designated by the Bank Select
Register (BSR). The address
can be in any implemented F00h
bank in the data memory Bank 15
space. F60h
SFRs
FFFh
Data Memory

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6.7.3 MAPPING THE ACCESS BANK IN 6.8 PIC18 Instruction Execution and
INDEXED LITERAL OFFSET MODE the Extended Instruction Set
The use of Indexed Literal Offset Addressing mode Enabling the extended instruction set adds eight
effectively changes how the first 96 locations of Access additional commands to the existing PIC18 instruction
RAM (00h to 5Fh) are mapped. Rather than containing set. These instructions are executed as described in
just the contents of the bottom section of Bank 0, this Section 27.2 “Extended Instruction Set”.
mode maps the contents from a user defined “window”
that can be located anywhere in the data memory
space. The value of FSR2 establishes the lower bound-
ary of the addresses mapped into the window, while the
upper boundary is defined by FSR2 plus 95 (5Fh).
Addresses in the Access RAM above 5Fh are mapped
as previously described (see Section 6.4.3 “Access
Bank”). An example of Access Bank remapping in this
addressing mode is shown in Figure 6-9.
Remapping of the Access Bank applies only to opera-
tions using the Indexed Literal Offset mode. Operations
that use the BSR (Access RAM bit is ‘1’) will continue
to use direct addressing as before.

FIGURE 6-9: REMAPPING THE ACCESS BANK WITH INDEXED LITERAL OFFSET
ADDRESSING
Example Situation:
ADDWF f, d, a 000h
FSR2H:FSR2L = 120h
Bank 0
Locations in the region
from the FSR2 pointer 100h
(120h) to the pointer plus Bank 1
120h
05Fh (17Fh) are mapped Window
17Fh 00h
to the bottom of the
Bank 1
Access RAM (000h-05Fh). 200h Bank 1 “Window”
Special File Registers at 5Fh
60h
F60h through FFFh are
mapped to 60h through Bank 2
FFh, as usual. SFRs
through
Bank 0 addresses below Bank 14
5Fh can still be addressed FFh
by using the BSR. Access Bank
F00h
Bank 15
F60h
SFRs
FFFh
Data Memory

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7.0 FLASH PROGRAM MEMORY 7.1 Table Reads and Table Writes
The Flash program memory is readable, writable and In order to read and write program memory, there are
erasable during normal operation over the specified two operations that allow the processor to move bytes
VDD ranges. between the program memory space and the data RAM:
A read from program memory is executed one byte at • Table Read (TBLRD)
a time. A write to program memory is executed on • Table Write (TBLWT)
blocks of 64 bytes at a time. Program memory is
The program memory space is 16 bits wide, while the
erased in blocks of 64 bytes at a time. A bulk erase
data RAM space is 8 bits wide. Table reads and table
operation cannot be issued from user code.
writes move data between these two memory spaces
Writing or erasing program memory will cease through an 8-bit register (TABLAT).
instruction fetches until the operation is complete. The
The table read operation retrieves one byte of data
program memory cannot be accessed during the write
directly from program memory and places it into the
or erase, therefore, code cannot execute. An internal
TABLAT register. Figure 7-1 shows the operation of a
programming timer terminates program memory writes
table read.
and erases.
The table write operation stores one byte of data from the
A value written to program memory does not need to be
TABLAT register into a write block holding register. The
a valid instruction. Executing a program memory
procedure to write the contents of the holding registers
location that forms an invalid instruction results in a
into program memory is detailed in Section 7.6 “Writing
NOP.
to Flash Program Memory”. Figure 7-2 shows the
operation of a table write with program memory and data
RAM.
Table operations work with byte entities. Tables
containing data, rather than program instructions, are
not required to be word aligned. Therefore, a table can
start and end at any byte address. If a table write is being
used to write executable code into program memory,
program instructions will need to be word aligned.

FIGURE 7-1: TABLE READ OPERATION

Instruction: TBLRD*

Program Memory
Table Pointer(1)
Table Latch (8-bit)
TBLPTRU TBLPTRH TBLPTRL
TABLAT

Program Memory
(TBLPTR)

Note 1: Table Pointer register points to a byte in program memory.

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FIGURE 7-2: TABLE WRITE OPERATION

Instruction: TBLWT*

Program Memory Holding Registers

Table Pointer(1) Table Latch (8-bit)

TBLPTRU TBLPTRH TBLPTRL TABLAT

Program Memory
(TBLPTR<MSBs>)

Note 1: During table writes the Table Pointer does not point directly to Program Memory. The LSBs of TBLPRTL
actually point to an address within the write block holding registers. The MSBs of the Table Pointer deter-
mine where the write block will eventually be written. The process for writing the holding registers to the
program memory array is discussed in Section 7.6 “Writing to Flash Program Memory”.

7.2 Control Registers
Several control registers are used in conjunction with
the TBLRD and TBLWT instructions. These include the:
• EECON1 register
• EECON2 register
• TABLAT register
• TBLPTR registers
7.2.1 EECON1 AND EECON2 REGISTERS
The EECON1 register (Register 7-1) is the control
register for memory accesses. The EECON2 register is
not a physical register; it is used exclusively in the
memory write and erase sequences. Reading
EECON2 will read all ‘0’s.
The EEPGD control bit determines if the access will be
a program or data EEPROM memory access. When
EEPGD is clear, any subsequent operations will
operate on the data EEPROM memory. When EEPGD
is set, any subsequent operations will operate on the
program memory.
The CFGS control bit determines if the access will be
to the Configuration/Calibration registers or to program
memory/data EEPROM memory. When CFGS is set,
subsequent operations will operate on Configuration
registers regardless of EEPGD (see Section 26.0
“Special Features of the CPU”). When CFGS is clear,
memory selection access is determined by EEPGD.
The FREE bit allows the program memory erase
operation. When FREE is set, an erase operation is
initiated on the next WR command. When FREE is
clear, only writes are enabled.
The WREN bit, when set, will allow a write operation.
The WREN bit is clear on power-up.
The WRERR bit is set by hardware when the WR bit is
set and cleared when the internal programming timer
expires and the write operation is complete.
Note: During normal operation, the WRERR is
read as ‘1’. This can indicate that a write
operation was prematurely terminated by
a Reset, or a write operation was
attempted improperly.
The WR control bit initiates write operations. The WR
bit cannot be cleared, only set, by firmware. The WR bit
is cleared by hardware at the completion of the write
operation.
Note: The EEIF interrupt flag bit of the PIR2
register is set when the write is complete.
The EEIF flag stays set until cleared by
firmware.

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 PIC18(L)F2X/45K50
7.3 Register Definitions: Memory Control
REGISTER 7-1: EECON1: DATA EEPROM CONTROL 1 REGISTER
R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0
EEPGD CFGS — FREE WRERR WREN WR RD
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit
S = Bit can be set by software, but not cleared U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit

1 = Access Flash program memory
0 = Access data EEPROM memory
bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit
1 = Access Configuration registers
0 = Access Flash program or data EEPROM memory
bit 5 Unimplemented: Read as ‘0’
bit 4 FREE: Flash Row (Block) Erase Enable bit
1 = Erase the program memory block addressed by TBLPTR on the next WR command
(cleared by completion of erase operation)
0 = Perform write-only
bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit(1)
1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal
operation, or an improper write attempt)
0 = The write operation completed
bit 2 WREN: Flash Program/Data EEPROM Write Enable bit
1 = Allows write cycles to Flash program/data EEPROM
0 = Inhibits write cycles to Flash program/data EEPROM
bit 1 WR: Write Control bit
1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle.
(The operation is self-timed and the bit is cleared by hardware once write is complete.
The WR bit can only be set (not cleared) by software.)
0 = Write cycle to the EEPROM is complete
bit 0 RD: Read Control bit
1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared by hardware. The RD bit can only
be set (not cleared) by software. RD bit cannot be set when EEPGD = 1 or CFGS = 1.)
0 = Does not initiate an EEPROM read

Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the
error condition.

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7.3.1 TABLAT – TABLE LATCH REGISTER
The Table Latch (TABLAT) is an 8-bit register mapped
into the SFR space. The Table Latch register is used to
hold 8-bit data during data transfers between program
memory and data RAM.
7.3.2 TBLPTR – TABLE POINTER
REGISTER
The Table Pointer (TBLPTR) register addresses a byte
within the program memory. The TBLPTR is comprised
of three SFR registers: Table Pointer Upper Byte, Table
Pointer High Byte and Table Pointer Low Byte
(TBLPTRU:TBLPTRH:TBLPTRL). These three regis-
ters join to form a 22-bit wide pointer. The low-order
21 bits allow the device to address up to 2 Mbytes of
program memory space. The 22nd bit allows access to
the device ID, the user ID and the Configuration bits.
The Table Pointer register, TBLPTR, is used by the
TBLRD and TBLWT instructions. These instructions can
update the TBLPTR in one of four ways based on the
table operation. These operations on the TBLPTR
affect only the low-order 21 bits.
7.3.3 TABLE POINTER BOUNDARIES
TBLPTR is used in reads, writes and erases of the
Flash program memory.
When a TBLRD is executed, all 22 bits of the TBLPTR
determine which byte is read from program memory
directly into the TABLAT register.
When a TBLWT is executed the byte in the TABLAT
register is written, not to Flash memory but, to a holding
register in preparation for a program memory write. The
holding registers constitute a write block which varies
depending on the device (see Table 7-1).The six LSbs
of the TBLPTRL register determine which specific
address within the holding register block is written to.
The MSBs of the Table Pointer have no effect during
TBLWT operations.
When a program memory write is executed (WR = 1),
the entire holding register block is written to the Flash
memory at the address determined by the MSbs of the
TBLPTR. The six LSBs are ignored during Flash mem-
ory writes. For more detail, see Section 7.6 “Writing
to Flash Program Memory”.
When an erase of program memory is executed, the
16 MSbs of the Table Pointer register (TBLPTR<21:6>)
point to the 64-byte block that will be erased. The Least
Significant bits (TBLPTR<5:0>) are ignored.
Figure 7-3 describes the relevant boundaries of
TBLPTR based on Flash program memory operations.

TABLE 7-1: TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS
Example Operation on Table Pointer
TBLRD*
TBLPTR is not modified
TBLWT*
TBLRD*+
TBLPTR is incremented after the read/write
TBLWT*+
TBLRD*-
TBLPTR is decremented after the read/write
TBLWT*-
TBLRD+*
TBLPTR is incremented before the read/write
TBLWT+*

FIGURE 7-3: TABLE POINTER BOUNDARIES BASED ON OPERATION

21 TBLPTRU 16 15 TBLPTRH 8 7 TBLPTRL 0

TABLE ERASE/WRITE TABLE WRITE

TBLPTR<21:n+1>(1) TBLPTR<n:0>(1)

TABLE READ – TBLPTR<21:0>

Note 1: n = 5 for block sizes of 64 bytes.

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7.4 Reading the Flash Program
Memory
The TBLRD instruction retrieves data from program
memory and places it into data RAM. Table reads from
program memory are performed one byte at a time.
TBLPTR points to a byte address in program space.
Executing TBLRD places the byte pointed to into
TABLAT. In addition, TBLPTR can be modified
automatically for the next table read operation.
The internal program memory is typically organized by
words. The Least Significant bit of the address selects
between the high and low bytes of the word. Figure 7-4
shows the interface between the internal program
memory and the TABLAT.

FIGURE 7-4: READS FROM FLASH PROGRAM MEMORY

Program Memory

(Even Byte Address) (Odd Byte Address)

TBLPTR = xxxxx1 TBLPTR = xxxxx0

Instruction Register TABLAT

FETCH TBLRD
(IR) Read Register

EXAMPLE 7-1: READING A FLASH PROGRAM MEMORY WORD

MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base
MOVWF TBLPTRU ; address of the word
MOVLW CODE_ADDR_HIGH
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW
MOVWF TBLPTRL
READ_WORD
TBLRD*+ ; read into TABLAT and increment
MOVF TABLAT, W ; get data
MOVWF WORD_EVEN
TBLRD*+ ; read into TABLAT and increment
MOVFW TABLAT, W ; get data
MOVF WORD_ODD

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7.5 Erasing Flash Program Memory 7.5.1 FLASH PROGRAM MEMORY
ERASE SEQUENCE
The minimum erase block is 32 words or 64 bytes. Only
through the use of an external programmer, or through The sequence of events for erasing a block of internal
ICSP control, can larger blocks of program memory be program memory is:
bulk erased. Word erase in the Flash array is not 1. Load Table Pointer register with address of
supported. block being erased.
When initiating an erase sequence from the 2. Set the EECON1 register for the erase operation:
microcontroller itself, a block of 64 bytes of program • set EEPGD bit to point to program memory;
memory is erased. The Most Significant 16 bits of the • clear the CFGS bit to access program memory;
TBLPTR<21:6> point to the block being erased. The
• set WREN bit to enable writes;
TBLPTR<5:0> bits are ignored.
• set FREE bit to enable the erase.
The EECON1 register commands the erase operation.
3. Disable interrupts.
The EEPGD bit must be set to point to the Flash
program memory. The WREN bit must be set to enable 4. Write 55h to EECON2.
write operations. The FREE bit is set to select an erase 5. Write 0AAh to EECON2.
operation. 6. Set the WR bit. This will begin the block erase
The write initiate sequence for EECON2, shown as cycle.
steps 4 through 6 in Section 7.5.1 “Flash Program 7. The CPU will stall for duration of the erase
Memory Erase Sequence”, is used to guard against (about 2 ms using internal timer).
accidental writes. This is sometimes referred to as a 8. Re-enable interrupts.
long write.
A long write is necessary for erasing the internal Flash.
Instruction execution is halted during the long write
cycle. The long write is terminated by the internal
programming timer.

EXAMPLE 7-2: ERASING A FLASH PROGRAM MEMORY BLOCK

MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base
MOVWF TBLPTRU ; address of the memory block
MOVLW CODE_ADDR_HIGH
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW
MOVWF TBLPTRL
ERASE_BLOCK
BSF EECON1, EEPGD ; point to Flash program memory
BCF EECON1, CFGS ; access Flash program memory
BSF EECON1, WREN ; enable write to memory
BSF EECON1, FREE ; enable block Erase operation
BCF INTCON, GIE ; disable interrupts
Required MOVLW 55h
Sequence MOVWF EECON2 ; write 55h
MOVLW 0AAh
MOVWF EECON2 ; write 0AAh
BSF EECON1, WR ; start erase (CPU stall)
BSF INTCON, GIE ; re-enable interrupts

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7.6 Writing to Flash Program Memory
The programming block size is 64 bytes. Word or byte
programming is not supported.
Table writes are used internally to load the holding
registers needed to program the Flash memory. There
are only as many holding registers as there are bytes
in a write block (64 bytes).
Since the Table Latch (TABLAT) is only a single byte,
the TBLWT instruction needs to be executed 64 times
for each programming operation. All of the table write
operations will essentially be short writes because only
the holding registers are written. After all the holding
registers have been written, the programming
operation of that block of memory is started by
configuring the EECON1 register for a program
memory write and performing the long write sequence.
FIGURE 7-5: TABLE WRITES TO FLASH PROGRAM MEMORY
TABLAT
Write Register
8 8
TBLPTR = xxxx00 TBLPTR = xxxx01 TBLPTR = xxxx02
Holding Register Holding Register
Program Memory
Note 1: YY = 3Fh for 64 byte write blocks.
7.6.1 FLASH PROGRAM MEMORY WRITE
SEQUENCE
The sequence of events for programming an internal
program memory location should be:
1. Read 64 bytes into RAM.
2. Update data values in RAM as necessary.
3. Load Table Pointer register with address being
erased.
4. Execute the block erase procedure.
5. Load Table Pointer register with address of first
byte being written.
6. Write the 64-byte block into the holding registers
with auto-increment (TBLWT*+ or TBLWT+*).
7. Set the EECON1 register for the write operation:
• set EEPGD bit to point to program memory;
• clear the CFGS bit to access program memory;
• set WREN to enable writes.
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The long write is necessary for programming the
internal Flash. Instruction execution is halted during a
long write cycle. The long write will be terminated by
the internal programming timer.
The EEPROM on-chip timer controls the write time.
The write/erase voltages are generated by an on-chip
charge pump, rated to operate over the voltage range
of the device.
Note: The default value of the holding registers on
device Resets and after write operations is
FFh. A write of FFh to a holding register
does not modify that byte. This means that
individual bytes of program memory may
be modified, provided that the change does
not attempt to change any bit from a ‘0’ to a
‘1’. When modifying individual bytes, it is
not necessary to load all holding registers
before executing a long write operation.
8 8
TBLPTR = xxxxYY(1)
Holding Register Holding Register
8. Disable interrupts.
9. Write 55h to EECON2.
10. Write 0AAh to EECON2.
11. Set the WR bit. This will begin the write cycle.
12. The CPU will stall for duration of the write (about
2 ms using internal timer).
13. Re-enable interrupts.
14. Verify the memory (table read).
This procedure will require about 6 ms to update each
write block of memory. An example of the required code
is given in Example 7-3.
Note: Before setting the WR bit, the Table
Pointer address needs to be within the
intended address range of the bytes in the
holding registers.
DS30000684B-page 101
PIC18(L)F2X/45K50
EXAMPLE 7-3: WRITING TO FLASH PROGRAM MEMORY
MOVLW D'64’ ; number of bytes in erase block
MOVWF COUNTER
MOVLW BUFFER_ADDR_HIGH ; point to buffer
MOVWF FSR0H
MOVLW BUFFER_ADDR_LOW
MOVWF FSR0L
MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base
MOVWF TBLPTRU ; address of the memory block
MOVLW CODE_ADDR_HIGH
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW
MOVWF TBLPTRL
READ_BLOCK
TBLRD*+ ; read into TABLAT, and inc
MOVF TABLAT, W ; get data
MOVWF POSTINC0 ; store data
DECFSZ COUNTER ; done?
BRA READ_BLOCK ; repeat
MODIFY_WORD
MOVLW BUFFER_ADDR_HIGH ; point to buffer
MOVWF FSR0H
MOVLW BUFFER_ADDR_LOW
MOVWF FSR0L
MOVLW NEW_DATA_LOW ; update buffer word
MOVWF POSTINC0
MOVLW NEW_DATA_HIGH
MOVWF INDF0
ERASE_BLOCK
MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base
MOVWF TBLPTRU ; address of the memory block
MOVLW CODE_ADDR_HIGH
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW
MOVWF TBLPTRL
BSF EECON1, EEPGD ; point to Flash program memory
BCF EECON1, CFGS ; access Flash program memory
BSF EECON1, WREN ; enable write to memory
BSF EECON1, FREE ; enable Erase operation
BCF INTCON, GIE ; disable interrupts
MOVLW 55h
Required MOVWF EECON2 ; write 55h
Sequence MOVLW 0AAh
MOVWF EECON2 ; write 0AAh
BSF EECON1, WR ; start erase (CPU stall)
BSF INTCON, GIE ; re-enable interrupts
TBLRD*- ; dummy read decrement
MOVLW BUFFER_ADDR_HIGH ; point to buffer
MOVWF FSR0H
MOVLW BUFFER_ADDR_LOW
MOVWF FSR0L
WRITE_BUFFER_BACK
MOVLW BlockSize ; number of bytes in holding register
MOVWF COUNTER
MOVLW D’64’/BlockSize ; number of write blocks in 64 bytes
MOVWF COUNTER2
WRITE_BYTE_TO_HREGS
MOVF POSTINC0, W ; get low byte of buffer data
MOVWF TABLAT ; present data to table latch
TBLWT+* ; write data, perform a short write
; to internal TBLWT holding register.

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 PIC18(L)F2X/45K50
EXAMPLE 7-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED)
DECFSZ COUNTER ; loop until holding registers are full
BRA WRITE_WORD_TO_HREGS
PROGRAM_MEMORY
BSF EECON1, EEPGD ; point to Flash program memory
BCF EECON1, CFGS ; access Flash program memory
BSF EECON1, WREN ; enable write to memory
BCF INTCON, GIE ; disable interrupts
MOVLW 55h
Required MOVWF EECON2 ; write 55h
Sequence MOVLW 0AAh
MOVWF EECON2 ; write 0AAh
BSF EECON1, WR ; start program (CPU stall)
DCFSZ COUNTER2 ; repeat for remaining write blocks
BRA WRITE_BYTE_TO_HREGS ;
BSF INTCON, GIE ; re-enable interrupts
BCF EECON1, WREN ; disable write to memory

7.6.2 WRITE VERIFY 7.6.4 PROTECTION AGAINST

Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
SPURIOUS WRITES
To protect against spurious writes to Flash program
memory, the write initiate sequence must also be
followed. See Section 26.0 “Special Features of the
CPU” for more detail.

7.6.3 UNEXPECTED TERMINATION OF 7.7 Flash Program Operation During

WRITE OPERATION
Code Protection
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory See Section 26.5 “Program Verification and Code
location just programmed should be verified and Protection” for details on code protection of Flash
reprogrammed if needed. If the write operation is program memory.
interrupted by a MCLR Reset or a WDT Time-out Reset
during normal operation, the WRERR bit will be set
which the user can check to decide whether a rewrite
of the location(s) is needed.
TABLE 7-2: REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on page
TBLPTRU — — Program Memory Table Pointer Upper Byte (TBLPTR<21:16>) —
TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) —
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) —
TABLAT Program Memory Table Latch —
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF 114
EECON2 EEPROM Control Register 2 (not a physical register) —
EECON1 EEPGD CFGS — FREE WRERR WREN WR RD 97
IPR2 OSCFIP C1IP C2IP EEIP BCLIP HLVDIP TMR3IP CCP2IP 124
PIR2 OSCFIF C1IF C2IF EEIF BCLIF HLVDIF TMR3IF CCP2IF 118
PIE2 OSCFIE C1IE C2IE EEIE BCLIE HLVDIE TMR3IE CCP2IE 121
Legend: — = unimplemented, read as ‘0’. Shaded bits are not used during Flash/EEPROM access.

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PIC18(L)F2X/45K50
8.0 DATA EEPROM MEMORY
The data EEPROM is a nonvolatile memory array,
separate from the data RAM and program memory,
which is used for long-term storage of program data. It
is not directly mapped in either the register file or
program memory space but is indirectly addressed
through the Special Function Registers (SFRs). The
EEPROM is readable and writable during normal
operation over the specified VDD range.
Four SFRs are used to read and write to the data
EEPROM as well as the program memory. They are:
• EECON1
• EECON2
• EEDATA
• EEADR
The data EEPROM allows byte read and write. When
interfacing to the data memory block, EEDATA holds
the 8-bit data for read/write, and the EEADR register
holds the address of the EEPROM location being
accessed.
The EEPROM data memory is rated for high erase/write
cycle endurance. A byte write automatically erases the
location and writes the new data (erase-before-write).
The write time is controlled by an on-chip timer; it will
vary with voltage and temperature as well as from chip-
to-chip. Please refer to the Data EEPROM Memory
parameters in Section 29.0 “Electrical Specifica-
tions” for limits.
8.1 EEADR Register
The EEADR register is used to address the data
EEPROM for read and write operations. The 8-bit
range of the register can address a memory range of
256 bytes (00h to FFh).
DS30000684B-page 104
8.2 EECON1 and EECON2 Registers
Access to the data EEPROM is controlled by two
registers: EECON1 and EECON2. These are the same
registers which control access to the program memory
and are used in a similar manner for the data
EEPROM.
The EECON1 register (Register 8-1) is the control
register for data and program memory access. Control
bit EEPGD determines if the access will be to program
or data EEPROM memory. When the EEPGD bit is
clear, operations will access the data EEPROM
memory. When the EEPGD bit is set, program memory
is accessed.
Control bit, CFGS, determines if the access will be to
the Configuration registers or to program memory/data
EEPROM memory. When the CFGS bit is set,
subsequent operations access Configuration registers.
When the CFGS bit is clear, the EEPGD bit selects
either program Flash or data EEPROM memory.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear.
The WRERR bit is set by hardware when the WR bit is
set and cleared when the internal programming timer
expires and the write operation is complete.
Note: During normal operation, the WRERR
may read as ‘1’. This can indicate that a
write operation was prematurely termi-
nated by a Reset, or a write operation was
attempted improperly.
The WR control bit initiates write operations. The bit
can be set but not cleared by software. It is cleared only
by hardware at the completion of the write operation.
Note: The EEIF interrupt flag bit of the PIR2
register is set when the write is complete.
It must be cleared by software.
Control bits, RD and WR, start read and erase/write
operations, respectively. These bits are set by firmware
and cleared by hardware at the completion of the
operation.
The RD bit cannot be set when accessing program
memory (EEPGD = 1). Program memory is read using
table read instructions. See Section 7.1 “Table Reads
and Table Writes” regarding table reads.
The EECON2 register is not a physical register. It is
used exclusively in the memory write and erase
sequences. Reading EECON2 will read all ‘0’s.
 2012-2014 Microchip Technology Inc.
 PIC18(L)F2X/45K50

REGISTER 8-1: EECON1: DATA EEPROM CONTROL 1 REGISTER

R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0
EEPGD CFGS — FREE WRERR WREN WR RD
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit
S = Bit can be set by software, but not cleared U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit

1 = Access Flash program memory
0 = Access data EEPROM memory
bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit
1 = Access Configuration registers
0 = Access Flash program or data EEPROM memory
bit 5 Unimplemented: Read as ‘0’
bit 4 FREE: Flash Row (Block) Erase Enable bit
1 = Erase the program memory block addressed by TBLPTR on the next WR command
(cleared by completion of erase operation)
0 = Perform write-only
bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit(1)
1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal
operation, or an improper write attempt)
0 = The write operation completed
bit 2 WREN: Flash Program/Data EEPROM Write Enable bit
1 = Allows write cycles to Flash program/data EEPROM
0 = Inhibits write cycles to Flash program/data EEPROM
bit 1 WR: Write Control bit
1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle.
(The operation is self-timed and the bit is cleared by hardware once write is complete.
The WR bit can only be set (not cleared) by software.)
0 = Write cycle to the EEPROM is complete
bit 0 RD: Read Control bit
1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared by hardware. The RD bit can only
be set (not cleared) by software. RD bit cannot be set when EEPGD = 1 or CFGS = 1.)
0 = Does not initiate an EEPROM read

Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the
error condition.

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PIC18(L)F2X/45K50
8.3 Reading the Data EEPROM
Memory
To read a data memory location, the user must write the
address to the EEADR register, clear the EEPGD con-
trol bit of the EECON1 register and then set control bit,
RD. The data is available on the very next instruction
cycle; therefore, the EEDATA register can be read by
the next instruction. EEDATA will hold this value until
another read operation, or until it is written to by the
user (during a write operation).
The basic process is shown in Example 8-1.
8.4 Writing to the Data EEPROM
Memory
To write an EEPROM data location, the address must
first be written to the EEADR register and the data writ-
ten to the EEDATA register. The sequence in
Example 8-2 must be followed to initiate the write cycle.
The write will not begin if this sequence is not exactly
followed (write 55h to EECON2, write 0AAh to
EECON2, then set WR bit) for each byte. It is strongly
recommended that interrupts be disabled during this
code segment.
Additionally, the WREN bit in EECON1 must be set to
enable writes. This mechanism prevents accidental
writes to data EEPROM due to unexpected code
execution (i.e., runaway programs). The WREN bit
should be kept clear at all times, except when updating
the EEPROM. The WREN bit is not cleared by
hardware.
After a write sequence has been initiated, EECON1,
EEADR and EEDATA cannot be modified. The WR bit
will be inhibited from being set unless the WREN bit is
set. Both WR and WREN cannot be set with the same
instruction.
At the completion of the write cycle, the WR bit is
cleared by hardware and the EEPROM Interrupt Flag
bit, EEIF, is set. The user may either enable this
interrupt or poll this bit. EEIF must be cleared by
software.
8.5 Write Verify
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.

EXAMPLE 8-1: DATA EEPROM READ

MOVLW DATA_EE_ADDR ;
MOVWF EEADR ; Data Memory Address to read
BCF EECON1, EEPGD ; Point to DATA memory
BCF EECON1, CFGS ; Access EEPROM
BSF EECON1, RD ; EEPROM Read
MOVF EEDATA, W ; W = EEDATA

EXAMPLE 8-2: DATA EEPROM WRITE

MOVLW DATA_EE_ADDR_LOW ;
MOVWF EEADR ; Data Memory Address to write
MOVLW DATA_EE_ADDR_HI ;
MOVWF EEADRH ;
MOVLW DATA_EE_DATA ;
MOVWF EEDATA ; Data Memory Value to write
BCF EECON1, EEPGD ; Point to DATA memory
BCF EECON1, CFGS ; Access EEPROM
BSF EECON1, WREN ; Enable writes
BCF INTCON, GIE ; Disable Interrupts
MOVLW 55h ;
Required MOVWF EECON2 ; Write 55h
Sequence MOVLW 0AAh ;
MOVWF EECON2 ; Write 0AAh
BSF EECON1, WR ; Set WR bit to begin write
BSF INTCON, GIE ; Enable Interrupts

; User code execution

BCF EECON1, WREN ; Disable writes on write complete (EEIF set)

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8.6 Operation During Code-Protect
Data EEPROM memory has its own code-protect bits in
Configuration Words. External read and write
operations are disabled if code protection is enabled.
The microcontroller itself can both read and write to the
internal data EEPROM, regardless of the state of the
code-protect Configuration bit. Refer to Section 26.0
“Special Features of the CPU” for additional
information.
8.7 Protection Against Spurious Write
There are conditions when the user may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been implemented. On power-up, the WREN bit is
cleared. In addition, writes to the EEPROM are blocked
during the Power-up Timer period (TPWRT).
PIC18(L)F2X/45K50
The write initiate sequence and the WREN bit together
help prevent an accidental write during brown-out,
power glitch or software malfunction.
8.8 Using the Data EEPROM
The data EEPROM is a high-endurance, byte
addressable array that has been optimized for the
storage of frequently changing information (e.g.,
program variables or other data that are updated often).
When variables in one section change frequently, while
variables in another section do not change, it is possible
to exceed the total number of write cycles to the
EEPROM without exceeding the total number of write
cycles to a single byte. Refer to the Data EEPROM
Memory parameters in Section 29.0 “Electrical
Specifications” for write cycle limits. If this is the case,
then an array refresh must be performed. For this
reason, variables that change infrequently (such as
constants, IDs, calibration, etc.) should be stored in
Flash program memory.
A simple data EEPROM refresh routine is shown in
Example 8-3.
Note: If data EEPROM is only used to store
constants and/or data that changes rarely,
an array refresh is likely not required. See
specification.

EXAMPLE 8-3: DATA EEPROM REFRESH ROUTINE

CLRF EEADR ; Start at address 0
BCF EECON1, CFGS ; Set for memory
BCF EECON1, EEPGD ; Set for Data EEPROM
BCF INTCON, GIE ; Disable interrupts
BSF EECON1, WREN ; Enable writes
Loop ; Loop to refresh array
BSF EECON1, RD ; Read current address
MOVLW 55h ;
MOVWF EECON2 ; Write 55h
MOVLW 0AAh ;
MOVWF EECON2 ; Write 0AAh
BSF EECON1, WR ; Set WR bit to begin write
BTFSC EECON1, WR ; Wait for write to complete
BRA $-2
INCFSZ EEADR, F ; Increment address
BRA LOOP ; Not zero, do it again

BCF EECON1, WREN ; Disable writes

BSF INTCON, GIE ; Enable interrupts

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PIC18(L)F2X/45K50

TABLE 8-1: REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY

Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF 114
EEADR EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 —
EEDATA EEPROM Data Register —
EECON2 EEPROM Control Register 2 (not a physical register) —
EECON1 EEPGD CFGS — FREE WRERR WREN WR RD 105
IPR2 OSCFIP C1IP C2IP EEIP BCLIP HLVDIP TMR3IP CCP2IP 124
PIR2 OSCFIF C1IF C2IF EEIF BCLIF HLVDIF TMR3IF CCP2IF 118
PIE2 OSCFIE C1IE C2IE EEIE BCLIE HLVDIE TMR3IE CCP2IE 121
Legend: — = unimplemented, read as ‘0’. Shaded bits are not used during EEPROM access.

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 PIC18(L)F2X/45K50
9.0 8 x 8 HARDWARE MULTIPLIER EXAMPLE 9-1: 8 x 8 UNSIGNED
MULTIPLY ROUTINE
9.1 Introduction MOVF ARG1, W ;
MULWF ARG2 ; ARG1 * ARG2 ->
All PIC18 devices include an 8 x 8 hardware multiplier ; PRODH:PRODL
as part of the ALU. The multiplier performs an unsigned
operation and yields a 16-bit result that is stored in the
product register pair, PRODH:PRODL. The multiplier’s EXAMPLE 9-2: 8 x 8 SIGNED MULTIPLY
operation does not affect any flags in the STATUS ROUTINE
register.
MOVF ARG1, W
Making multiplication a hardware operation allows it to MULWF ARG2 ; ARG1 * ARG2 ->
be completed in a single instruction cycle. This has the ; PRODH:PRODL
advantages of higher computational throughput and BTFSC ARG2, SB ; Test Sign Bit
reduced code size for multiplication algorithms and SUBWF PRODH, F ; PRODH = PRODH
allows the PIC18 devices to be used in many applica- ; - ARG1
MOVF ARG2, W
tions previously reserved for digital signal processors.
BTFSC ARG1, SB ; Test Sign Bit
A comparison of various hardware and software
SUBWF PRODH, F ; PRODH = PRODH
multiply operations, along with the savings in memory ; - ARG2
and execution time, is shown in Table 9-1.

9.2 Operation
Example 9-1 shows the instruction sequence for an 8 x 8
unsigned multiplication. Only one instruction is required
when one of the arguments is already loaded in the
WREG register.
Example 9-2 shows the sequence to do an 8 x 8 signed
multiplication. To account for the sign bits of the
arguments, each argument’s Most Significant bit (MSb)
is tested and the appropriate subtractions are done.

TABLE 9-1: PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS

Program Time
Cycles
Routine Multiply Method Memory
(Max) @ 48 MHz @ 40 MHz @ 10 MHz @ 4 MHz
(Words)
Without hardware multiply 13 69 5.7 s 6.9 s 27.6 s 69 s
8 x 8 unsigned
Hardware multiply 1 1 83.3 ns 100 ns 400 ns 1 s
Without hardware multiply 33 91 7.5 s 9.1 s 36.4 s 91 s
8 x 8 signed
Hardware multiply 6 6 500 ns 600 ns 2.4 s 6 s
Without hardware multiply 21 242 20.1 s 24.2 s 96.8 s 242 s
16 x 16 unsigned
Hardware multiply 28 28 2.3 s 2.8 s 11.2 s 28 s
Without hardware multiply 52 254 21.6 s 25.4 s 102.6 s 254 s
16 x 16 signed
Hardware multiply 35 40 3.3 s 4.0 s 16.0 s 40 s

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PIC18(L)F2X/45K50
Example 9-3 shows the sequence to do a 16 x 16 EQUATION 9-2: 16 x 16 SIGNED
unsigned multiplication. Equation 9-1 shows the MULTIPLICATION
algorithm that is used. The 32-bit result is stored in four ALGORITHM
registers (RES<3:0>). RES3:RES0 = ARG1H:ARG1L  ARG2H:ARG2L
= (ARG1H  ARG2H  216) +
EQUATION 9-1: 16 x 16 UNSIGNED (ARG1H  ARG2L  28) +
MULTIPLICATION (ARG1L  ARG2H  28) +
(ARG1L  ARG2L) +
ALGORITHM
(-1  ARG2H<7>  ARG1H:ARG1L  216) +
RES3:RES0 = ARG1H:ARG1L  ARG2H:ARG2L
(-1  ARG1H<7>  ARG2H:ARG2L  216)
= (ARG1H  ARG2H  216) +
(ARG1H  ARG2L  28) +
(ARG1L  ARG2H  28) + EXAMPLE 9-4: 16 x 16 SIGNED
(ARG1L  ARG2L) MULTIPLY ROUTINE
MOVF ARG1L, W
EXAMPLE 9-3: 16 x 16 UNSIGNED MULWF ARG2L ; ARG1L * ARG2L ->
MULTIPLY ROUTINE ; PRODH:PRODL
MOVFF PRODH, RES1 ;
MOVF ARG1L, W
MOVFF PRODL, RES0 ;
MULWF ARG2L ; ARG1L * ARG2L->
; PRODH:PRODL
MOVF ARG1H, W
MOVFF PRODH, RES1 ;
MULWF ARG2H ; ARG1H * ARG2H ->
MOVFF PRODL, RES0 ;
; PRODH:PRODL
MOVFF PRODH, RES3 ;
MOVF ARG1H, W
MOVFF PRODL, RES2 ;
MULWF ARG2H ; ARG1H * ARG2H->
; PRODH:PRODL
MOVF ARG1L, W
MOVFF PRODH, RES3 ;
MULWF ARG2H ; ARG1L * ARG2H ->
MOVFF PRODL, RES2 ;
; PRODH:PRODL
MOVF PRODL, W ;
MOVF ARG1L, W
ADDWF RES1, F ; Add cross
MULWF ARG2H ; ARG1L * ARG2H->
MOVF PRODH, W ; products
; PRODH:PRODL
ADDWFC RES2, F ;
MOVF PRODL, W ;
CLRF WREG ;
ADDWF RES1, F ; Add cross
ADDWFC RES3, F ;
MOVF PRODH, W ; products
ADDWFC RES2, F ;
MOVF ARG1H, W ;
CLRF WREG ;
MULWF ARG2L ; ARG1H * ARG2L ->
ADDWFC RES3, F ;
; PRODH:PRODL
MOVF PRODL, W ;
MOVF ARG1H, W ;
ADDWF RES1, F ; Add cross
MULWF ARG2L ; ARG1H * ARG2L->
MOVF PRODH, W ; products
; PRODH:PRODL
ADDWFC RES2, F ;
MOVF PRODL, W ;
CLRF WREG ;
ADDWF RES1, F ; Add cross
ADDWFC RES3, F ;
MOVF PRODH, W ; products
ADDWFC RES2, F ;
BTFSS ARG2H, 7 ; ARG2H:ARG2L neg?
CLRF WREG ;
BRA SIGN_ARG1 ; no, check ARG1
ADDWFC RES3, F ;
MOVF ARG1L, W ;
SUBWF RES2 ;
Example 9-4 shows the sequence to do a 16 x 16 MOVF ARG1H, W ;
signed multiply. Equation 9-2 shows the algorithm SUBWFB RES3
used. The 32-bit result is stored in four registers
(RES<3:0>). To account for the sign bits of the argu- SIGN_ARG1
ments, the MSb for each argument pair is tested and BTFSS ARG1H, 7 ; ARG1H:ARG1L neg?
BRA CONT_CODE ; no, done
the appropriate subtractions are done.
MOVF ARG2L, W ;
SUBWF RES2 ;
MOVF ARG2H, W ;
SUBWFB RES3

CONT_CODE
:

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10.0 INTERRUPTS
The PIC18(L)F2X/45K50 devices have multiple
interrupt sources and an interrupt priority feature that
allows most interrupt sources to be assigned a high or
low priority level (INT0 does not have a priority bit, it is
always a high priority). The high priority interrupt vector
is at 0008h and the low priority interrupt vector is at
0018h. A high priority interrupt event will interrupt a low
priority interrupt that may be in progress.
There are 13 registers used to control interrupt
operation.
These registers are:
• INTCON, INTCON2, INTCON3
• PIR1, PIR2, PIR3
• PIE1, PIE2, PIE3
• IPR1, IPR2, IPR3
• RCON
It is recommended that the Microchip header files
supplied with MPLAB® IDE be used for the symbolic bit
names in these registers. This allows the assembler/
compiler to automatically take care of the placement of
these bits within the specified register.
In general, interrupt sources have three bits to control
their operation. They are:
• Flag bit to indicate that an interrupt event
occurred
• Enable bit that allows program execution to
branch to the interrupt vector address when the
flag bit is set
• Priority bit to select high priority or low priority
10.1 Mid-Range Compatibility
When the IPEN bit is cleared (default state), the interrupt
priority feature is disabled and interrupts are compatible
with PIC microcontroller mid-range devices. In
Compatibility mode, the interrupt priority bits of the IPRx
registers have no effect. The PEIE/GIEL bit of the
INTCON register is the global interrupt enable for the
peripherals. The PEIE/GIEL bit disables only the
peripheral interrupt sources and enables the peripheral
interrupt sources when the GIE/GIEH bit is also set. The
GIE/GIEH bit of the INTCON register is the global
interrupt enable which enables all non-peripheral
interrupt sources and disables all interrupt sources,
including the peripherals. All interrupts branch to
address 0008h in Compatibility mode.
 2012-2014 Microchip Technology Inc.
PIC18(L)F2X/45K50
10.2 Interrupt Priority
The interrupt priority feature is enabled by setting the
IPEN bit of the RCON register. When interrupt priority
is enabled the GIE/GIEH and PEIE/GIEL global inter-
rupt enable bits of Compatibility mode are replaced by
the GIEH high priority, and GIEL low priority, global
interrupt enables. When set, the GIEH bit of the INT-
CON register enables all interrupts that have their
associated IPRx register or INTCONx register priority
bit set (high priority). When clear, the GIEH bit disables
all interrupt sources including those selected as low pri-
ority. When clear, the GIEL bit of the INTCON register
disables only the interrupts that have their associated
priority bit cleared (low priority). When set, the GIEL bit
enables the low priority sources when the GIEH bit is
also set.
When the interrupt flag, enable bit and appropriate
Global Interrupt Enable (GIE) bit are all set, the
interrupt will vector immediately to address 0008h for
high priority, or 0018h for low priority, depending on
level of the interrupting source’s priority bit. Individual
interrupts can be disabled through their corresponding
interrupt enable bits.
10.3 Interrupt Response
When an interrupt is responded to, the Global Interrupt
Enable bit is cleared to disable further interrupts. The
GIE/GIEH bit is the global interrupt enable when the
IPEN bit is cleared. When the IPEN bit is set, enabling
interrupt priority levels, the GIEH bit is the high priority
global interrupt enable and the GIEL bit is the low
priority global interrupt enable. High priority interrupt
sources can interrupt a low priority interrupt. Low
priority interrupts are not processed while high priority
interrupts are in progress.
The return address is pushed onto the stack and the
PC is loaded with the interrupt vector address (0008h
or 0018h). Once in the Interrupt Service Routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits in the INTCONx and PIRx
registers. The interrupt flag bits must be cleared by
software before re-enabling interrupts to avoid
repeating the same interrupt.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine and sets the GIE/GIEH bit (GIEH
or GIEL if priority levels are used), which re-enables
interrupts.
For external interrupt events, such as the INT pins or
the PORTB interrupt-on-change, the interrupt latency
will be three to four instruction cycles. The exact
latency is the same for one-cycle or two-cycle
instructions. Individual interrupt flag bits are set,
regardless of the status of their corresponding enable
bits or the Global Interrupt Enable bit.
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PIC18(L)F2X/45K50

Note: Do not use the MOVFF instruction to

modify any of the interrupt control
registers while any interrupt is enabled.
Doing so may cause erratic
microcontroller behavior.

FIGURE 10-1: PIC18 INTERRUPT LOGIC

Wake-up if in
INT0IF Idle or Sleep modes
INT0IE
TMR0IF
TMR0IE
TMR0IP
(1)
IOCIF
IOCIE
IOCIP
INT1IF Interrupt to CPU
PIR1<7:0> INT1IE Vector to Location
PIE1<7:0> INT1IP 0008h
IPR1<7:0> INT2IF
PIR2<7:0> INT2IE
PIE2<7:0> INT2IP
IPR2<7:0>
GIEH/GIE
PIR3<7:0>
PIE3<7:0>
IPR3<7:0> IPEN

IPEN
GIEL/PEIE
IPEN

High Priority Interrupt Generation

Low Priority Interrupt Generation

PIR1<7:0>
PIE1<7:0>
IPR1<7:0>
PIR2<7:0>
PIE2<7:0>
IPR2<7:0>
PIR3<7:0>
PIE3<7:0>
IPR3<7:0> Interrupt to CPU
TMR0IF Vector to Location
TMR0IE 0018h
TMR0IP
(1)
IOCIF
IOCIE
IOCIP GIEH/GIE
GIEL/PEIE
INT1IF
INT1IE
INT1IP

INT2IF
INT2IE
INT2IP

Note 1: The IOCIF interrupt also requires the individual pin IOCB enables.

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 PIC18(L)F2X/45K50
10.4 INTCON Registers
The INTCON registers are readable and writable
registers, which contain various enable, priority and
flag bits.

10.5 PIR Registers

The PIR registers contain the individual flag bits for the
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are three Peripheral Interrupt
Request Flag registers (PIR1, PIR2 and PIR3).

10.6 PIE Registers

The PIE registers contain the individual enable bits for
the peripheral interrupts. Due to the number of
peripheral interrupt sources, there are three Peripheral
Interrupt Enable registers (PIE1, PIE2 and PIE3). When
IPEN = 0, the PEIE/GIEL bit must be set to enable any
of these peripheral interrupts.

10.7 IPR Registers

The IPR registers contain the individual priority bits for the
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are three Peripheral Interrupt
Priority registers (IPR1, IPR2 and IPR3). Using the priority
bits requires that the Interrupt Priority Enable (IPEN) bit be
set.

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PIC18(L)F2X/45K50
10.8 Register Definitions: Interrupt Control
REGISTER 10-1: INTCON: INTERRUPT CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE/GIEH PEIE/GIEL TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 GIE/GIEH: Global Interrupt Enable bit

When IPEN = 0:
1 = Enables all unmasked interrupts
0 = Disables all interrupts including peripherals
When IPEN = 1:
1 = Enables all high priority interrupts
0 = Disables all interrupts including low priority
bit 6 PEIE/GIEL: Peripheral Interrupt Enable bit
When IPEN = 0:
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
When IPEN = 1:
1 = Enables all low priority interrupts
0 = Disables all low priority interrupts
bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 overflow interrupt
0 = Disables the TMR0 overflow interrupt
bit 4 INT0IE: INT0 External Interrupt Enable bit
1 = Enables the INT0 external interrupt
0 = Disables the INT0 external interrupt
bit 3 IOCIE: Interrupt-On-Change (IOCx) Interrupt Enable bit(2)
1 = Enables the IOCx port change interrupt
0 = Disables the IOCx port change interrupt
bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared by software)
0 = TMR0 register did not overflow
bit 1 INT0IF: INT0 External Interrupt Flag bit
1 = The INT0 external interrupt occurred (must be cleared by software)
0 = The INT0 external interrupt did not occur
bit 0 IOCIF: Interrupt-On-Change (IOCx) Interrupt Flag bit(1)
1 = At least one of the IOC pins changed state (must be cleared by software)
0 = None of the IOC pins have changed state

Note 1: A mismatch condition will continue to set the IOCIF bit. Reading PORTB/PORTC will end the
mismatch condition and allow the bit to be cleared.
2: Port change interrupts also require the individual pins IOCBx/IOCCx enables.

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit. User software should ensure
the appropriate interrupt flag bits are clear
prior to enabling an interrupt. This feature
allows for software polling.

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 PIC18(L)F2X/45K50

REGISTER 10-2: INTCON2: INTERRUPT CONTROL 2 REGISTER

R/W-1 R/W-1 R/W-1 R/W-1 U-0 R/W-1 U-0 R/W-1
RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — IOCIP
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 RBPU: PORTB Pull-up Enable bit

1 = All PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled provided that the pin is an input and the corresponding WPUB bit is
set.
bit 6 INTEDG0: External Interrupt 0 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 5 INTEDG1: External Interrupt 1 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 4 INTEDG2: External Interrupt 2 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 3 Unimplemented: Read as ‘0’
bit 2 TMR0IP: TMR0 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1 Unimplemented: Read as ‘0’
bit 0 IOCIP: Port Change Interrupt Priority bit
1 = High priority
0 = Low priority

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit. User software should ensure
the appropriate interrupt flag bits are clear
prior to enabling an interrupt. This feature
allows for software polling.

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PIC18(L)F2X/45K50

REGISTER 10-3: INTCON3: INTERRUPT CONTROL 3 REGISTER

R/W-1 R/W-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0
INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 INT2IP: INT2 External Interrupt Priority bit

1 = High priority
0 = Low priority
bit 6 INT1IP: INT1 External Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5 Unimplemented: Read as ‘0’
bit 4 INT2IE: INT2 External Interrupt Enable bit
1 = Enables the INT2 external interrupt
0 = Disables the INT2 external interrupt
bit 3 INT1IE: INT1 External Interrupt Enable bit
1 = Enables the INT1 external interrupt
0 = Disables the INT1 external interrupt
bit 2 Unimplemented: Read as ‘0’
bit 1 INT2IF: INT2 External Interrupt Flag bit
1 = The INT2 external interrupt occurred (must be cleared by software)
0 = The INT2 external interrupt did not occur
bit 0 INT1IF: INT1 External Interrupt Flag bit
1 = The INT1 external interrupt occurred (must be cleared by software)
0 = The INT1 external interrupt did not occur

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit. User software should ensure
the appropriate interrupt flag bits are clear
prior to enabling an interrupt. This feature
allows for software polling.

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 PIC18(L)F2X/45K50

REGISTER 10-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1

R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
ACTIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 ACTIF: Active Clock Tuning Interrupt Flag bit

1 = An Active Clock Tuning Event generated an interrupt (must be cleared in software)
0 = No Active Clock Tuning interrupt is pending
bit 6 ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed (must be cleared by software)
0 = The A/D conversion is not complete or has not been started
bit 5 RCIF: EUSART Receive Interrupt Flag bit
1 = The EUSART receive buffer, RCREG1, is full (cleared when RCREG1 is read)
0 = The EUSART receive buffer is empty
bit 4 TXIF: EUSART Transmit Interrupt Flag bit
1 = The EUSART transmit buffer, TXREG1, is empty (cleared when TXREG1 is written)
0 = The EUSART transmit buffer is full
bit 3 SSPIF: Master Synchronous Serial Port Interrupt Flag bit
1 = The transmission/reception is complete (must be cleared by software)
0 = Waiting to transmit/receive
bit 2 CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared by software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared by software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode
bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared by software)
0 = No TMR2 to PR2 match occurred
bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared by software)
0 = TMR1 register did not overflow

Note 1: Interrupt flag bits are set when an

interrupt condition occurs, regardless of
the state of its corresponding enable bit
or the Global Interrupt Enable bit, GIE/
GIEH of the INTCON register.
2: User software should ensure the appro-
priate interrupt flag bits are cleared prior
to enabling an interrupt and after servic-
ing that interrupt.

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PIC18(L)F2X/45K50

REGISTER 10-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
OSCFIF C1IF C2IF EEIF BCLIF HLVDIF TMR3IF CCP2IF
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit

1 = Device oscillator failed, clock input has changed to HFINTOSC (must be cleared by software)
0 = Device clock operating
bit 6 C1IF: Comparator C1 Interrupt Flag bit
1 = Comparator C1 output has changed (must be cleared by software)
0 = Comparator C1 output has not changed
bit 5 C2IF: Comparator C2 Interrupt Flag bit
1 = Comparator C2 output has changed (must be cleared by software)
0 = Comparator C2 output has not changed
bit 4 EEIF: Data EEPROM/Flash Write Operation Interrupt Flag bit
1 = The write operation is complete (must be cleared by software)
0 = The write operation is not complete or has not been started
bit 3 BCLIF: MSSP Bus Collision Interrupt Flag bit
1 = A bus collision occurred (must be cleared by software)
0 = No bus collision occurred
bit 2 HLVDIF: Low-Voltage Detect Interrupt Flag bit
1 = A low-voltage condition occurred (direction determined by the VDIRMAG bit of the
HLVDCON register)
0 = A low-voltage condition has not occurred
bit 1 TMR3IF: TMR3 Overflow Interrupt Flag bit
1 = TMR3 register overflowed (must be cleared by software)
0 = TMR3 register did not overflow
bit 0 CCP2IF: CCP2 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared by software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared by software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode.

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 PIC18(L)F2X/45K50

REGISTER 10-6: PIR3: PERIPHERAL INTERRUPT (FLAG) REGISTER 3

U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — — CTMUIF USBIF TMR3GIF TMR1GIF
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-4 Unimplemented: Read as ‘0’

bit 3 CTMUIF: CTMU Interrupt Flag bit
1 = CTMU interrupt occurred (must be cleared in software)
0 = No CTMU interrupt occurred
bit 2 USBIF: USB Interrupt Flag bit
1 = USB requested an interrupt (must be cleared in software)
0 = No USB interrupt request
bit 1 TMR3GIF: TMR3 Gate Interrupt Flag bit
1 = TMR gate interrupt occurred (must be cleared in software)
0 = No TMR gate occurred
bit 0 TMR1GIF: TMR1 Gate Interrupt Flag bit
1 = TMR gate interrupt occurred (must be cleared in software)
0 = No TMR gate occurred

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PIC18(L)F2X/45K50

REGISTER 10-7: PIE1: PERIPHERAL INTERRUPT ENABLE (FLAG) REGISTER 1

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ACTIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 ACTIE: Active Clock Tuning Interrupt Enable bit

1 = Enables Active Clock Tuning interrupt
0 = Disables Active Clock Tuning interrupt
bit 6 ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D interrupt
0 = Disables the A/D interrupt
bit 5 RCIE: EUSART Receive Interrupt Enable bit
1 = Enables the EUSART receive interrupt
0 = Disables the EUSART receive interrupt
bit 4 TXIE: EUSART Transmit Interrupt Enable bit
1 = Enables the EUSART transmit interrupt
0 = Disables the EUSART transmit interrupt
bit 3 SSPIE: Master Synchronous Serial Port Interrupt Enable bit
1 = Enables the MSSP interrupt
0 = Disables the MSSP interrupt
bit 2 CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt

DS30000684B-page 120  2012-2014 Microchip Technology Inc.