Department of Electrical and Computer Engineering

Successive Approximation ADCs

Vishal Saxena

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Successive Approximation ADC

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 Data Converter Architectures

1 word/OSR*Tclk
Resolution 1 level/Tclk
[Bits]
1 bit/Tclk
20

Integrating Partial word/Tclk

Oversampling
15
Successive Approximation
Algorithmic 1 word/Tclk
Subranging
10 Pipeline
Folding & Interpolating
Interleaving
Flash
5 Nyquist
Oversampling

0
1k 10k 100k 1M 10M 100M 1G 10G 100G
Sample Rate [Hz]

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Successive Approximation ADC
Vi VX

VDAC b1

...

...
DAC Do

bN
Shift
Register
• Binary search over DAC inputs
• N*Tclk to complete N bits
• successive approximation register or SAR
• High accuracy achievable (16+ bits)
• Relies on highly accurate comparator
• Moderate speeds (typically 0.1-10 MHz parts)

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 Binary Search Algorithm

VDAC
Vi
Vi VX
VFS
VDAC b1

VFS
...

...

DAC Do
2
bN
Shift
Register
1 0 0 1 1 0
0 t
MSB LSB
Tclk

• DAC output gradually approaches the input voltage

• Comparator differential input gradually approaches zero

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Binary Search Algorithm contd.

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High Performance Example

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Charge Redistribution SAR ADC
Φ1e

VX

SAR
8C 4C 2C C C

Do

VR
Φ1 Φ1 Φ1 Φ1 Φ1
Vi

• 4-bit binary-weighted capacitor array DAC (aka charge scaling DAC)

• Capacitor array samples input when Φ1 is asserted (bottom-plate)
• Comparator acts as a zero crossing detector
• Practical implementation is fully-differential

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Charge Redistribution (MSB)
Φ1e

VX

SAR
8C 4C 2C C C

Do

VR
Φ1 Φ1 Φ1 Φ1 Φ1
Vi

• Start with C4 connected to VR and others to 0 (i.e. SAR=1000)

VR  8C - Vi 16C VR
Vi 16C =  VR - VX  C4 - VX  C3 + C2 + C1 + C0   VX   - Vi
16C 2

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Comparison (MSB)

VX
1
0 t

Sample 1
MSB

VR
MSB TEST : VX   Vi
2

• If VX < 0, then Vi > VR/2, and MSB = 1, C4 remains connected to VR

• If VX > 0, then Vi < VR/2, and MSB = 0, C4 is switched to ground

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Charge Redistribution (MSB–1)
Φ1e

VX

SAR
8C 4C 2C C C

Do

VR
Φ1 Φ1 Φ1 Φ1 Φ1
Vi

• SAR=1100
VR 12C  Vi 16C 3
Vi 16C   VR  VX  12C  VX  4C  VX   VR  Vi
16C 4

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Comparison (MSB–1)

VX
1 2
0 t

Sample 1 0
MSB

3
MSB -1 TEST : VX  VR  Vi
4

• If VX < 0, then Vi > 3VR/4, and MSB-1 = 1, C3 remains connected to VR

• If VX > 0, then Vi < 3VR/4, and MSB-1 = 0, C3 is switched to ground

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Charge Redistribution (Other Bits)
Φ1e

VX

SAR
8C 4C 2C C C

Do

VR
Φ1 Φ1 Φ1 Φ1 Φ1
Vi

• SAR=1010, and so on…

Test completes when all four bits are determined w/ four charge
redistributions and comparisons

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After Four Clock Cycles…

VX
1 2 3 4
0 t

Sample 1 0 0 1
MSB LSB

• Usually, half Tclk is allocated for charge redistribution and half for
comparison + digital logic
• VX always converges to 0 (Vos if comparator has nonzero offset)

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Summing-Node Parasitics
Φ1e CP

Vos
SAR
8C 4C 2C C C

Do

VR
Φ1 Φ1 Φ1 Φ1 Φ1
Vi

• If Vos = 0, CP has no effect eventually; otherwise, CP attenuates VX

• Auto-zeroing can be applied to the comparator to reduce offset

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SAR ADC Considerations
•Power efficiency – only comparator consumes DC power
•Conversion rate typically limited by finite bandwidth of RC network
during sampling and bit-tests
•For high resolution, the binary weighted capacitor array can become
quite large
•E.g. 16-bit resolution, Ctotal~100pF for reasonable kT/C noise contribution
•If matching is an issue, an even larger value may be needed
•E.g. if matching dictates Cmin=10fF, then 216Cmin=655pF

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SAR ADC Considerations contd.
•Comparator offset Vos introduces an input-referred offset ~
(1+CP/ΣCj)*Vos
•CP in general has little effect on the conversion (VX→0 at the end of the
search)
•however, VX is always attenuated due to charge sharing of CP
•Binary search is sensitive to intermediate errors made during search –
if an intermediate decision is wrong, the digitization process cannot
recover
•DAC must settle into ±½ LSB bound within the time allowed
•Comparator offset must be constant (no hysteresis or time-dependent
offset)
•Non-binary search algorithm can be used (Kuttner, ISSCC’02)

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SAR ADC Considerations contd.
•Commonly used techniques
•Implement "two-stage" or "multi-stage" capacitor network to reduce array
size [Yee, JSSC 8/79]
•Split DAC or C-2C network
•Calibrate capacitor array to obtain precision beyond raw technology
matching [Lee, JSSC 12/84]

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SAR ADC Speed Estimation
• Model RC network when VIN is charged
• Replace switches with R’s
• Assume switches are sized proportional to capacitors

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SAR ADC Speed Estimation contd.
• Speed limited by RC time constant of capacitor array and switches

• For better than 0.5 LSB accuracy

• Sets minimum value for the charging time T

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Fully-differential Implementation

Vishal
© Vishal Saxena andSaxena
Venkatesh Acharya -21-
21
Recap: Advantages of SAR ADC

• Mostly digital components

• good for technology scaling
•No linear, high precision amplification is required
• fast, low power
•Minimal hardware
•1 comparator is needed

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SAR Evolution

•Digital friendly architecture in scaled CMOS has renewed interest in

SAR innovation

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Limitations of Synchronous SAR

•Cost
•High-speed internal clock needed 

•Speed Limitation
•Worst-case cycle time 
•Margin for clock jitter 

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Asynchronous SAR Concept

•Self-timed Asynchronous comparisons

•Master clock used for synchronizing with the sample rate

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 How much comparison time is saved?

•Conv. time between sync. and async. SAR, assuming regenerative

comparator is used.

•It varies with residue voltage profile

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 Asynchronous SAR ADC Concept

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Asynchronous SAR ADC Concept

• Dynamic to save power and generate ready signal

• Reset switches for fast recovery
• Ready signal is generated by NAND gate!

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Monotonic Capacitor Switching
•Monotonic switching procedure
•Input-common mode voltage
gradually converges to ground
•Exploit differential configuration
•Asynchronous comparisons
•Switching energy reduced by
81%

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Monotonic Capacitor Switching contd.
•

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Monotonic Capacitor Switching contd.
•Conventional switching procedure

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 Monotonic Capacitor Switching contd.
•Monotonic switching procedure

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Monotonic Capacitor Switching contd.
•

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Loop-unrolled SAR ADC

•Use N comparators for

each bit of conversion

•“loop unrolling”

•Asynchronous individual
comparisons

•1.25Gbps 6-bit
•Serial links application

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 Loop-unrolled SAR ADC contd.

•High speed comparator

•IDAC for offset cancellation

•Metastability detection

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Time Interleaving

• Sampling rate scale proportionally

to the number of interleaved
channels
• Calibration is required for inter-
channel mismatch
• Relaxed clock distribution
• For example:
• 8bit 56GS/s
• 320 of 175MS/s SAR
(Fujitsu)

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90GS/s 8bit with 64x Time Interleave

• Two comparators ‘ping-pong’ in two consecutive conversions

implemented in 32nm SOI

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References
1. Rudy van de Plassche, “CMOS Integrated Analog-to-Digital and Digital-to-Analog
Converters,” 2nd Ed., Springer, 2005..
2. Y. Chiu, Data Converters Lecture Slides, UT Dallas 2012.
3. B. Boser, Analog-Digital Interface Circuits Lecture Slides, UC Berkeley 2011.

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