‫أجهزة قياس طبية وحيوية‬

Biomedical Instrumentation (ECE396)

Lecture 4: D/A and A/D Converters
Assoc. Prof. Hossam El-Din Moustafa
Mansoura University, Egypt

Oct 11th, 2017 1

 GENERAL BLOCK DIAGRAM OF BIOMEDICAL INSTRUMENTATION
(6) Feedback Controller

(1) Stimulus
(3) Transducer
(5)
Transducer (4) Signal Processing,
Conditioning Display,
Equipment data
Transducer recording
(2) Man/Subject

oSignal conditioning equipment: receives the electrical signal from the transducer and
perform tasks of amplification, linearization, ADC, etc., in order to condition the signal for
recording and display 2
CONTENTS
1. Digital to analog converter (DAC)
2. Analog to digital converter (ADC)

3
REFERENCES
1. R. Anandanatarajan, “Biomedical Instrumentation and Measurements,” PHI Learning, Delhi,
2013.
2. M. Singh, “Introduction to biomedical instrumentation, 2nd Edition,” PHI Learning, Delhi,
2014.
3. D. Hinckley, L. Huynh, D. Kim, “Digital to Analog Converters, 2006.
ume.gatech.edu/mechatronics_course/DAC_S05.ppt
4. C. Woodin, A. AlSaibie, E. Maleki, “Analog-to-Digital Converter (ADC)”, Fall 2012.
ume.gatech.edu/mechatronics_course/ADC_F12.pptx

4
SIGNAL TYPES
Analog Signals
Continuos-varying quantity with time 𝑡
oAny continuous signal that a time varying
variable of the signal is a representation of
some other time varying quantity

Digital Signals t
oDiscrete in time
oDiscrete in amplitude

5
 EXAMPLE OF DIGITAL SIGNAL
Binary Signals
oConsist of only two states
Binary States 1
On „1‟ and off „0‟
oComputers can only perform processing
on digitized signals 0

Examples:
 Light switch can be either on or off
 Door to a room is either open or closed

6
WHAT IS A DAC?
o A digital to analog converter (DAC) converts a digital signal to an analog output

100101…
DAC

7
 DAC CHARACTERISTICS (INPUT VS. OUTPUT)
4-bit D/A converter
Analog Output Signal 𝑉𝑟𝑒𝑓 =16 volt
𝑛 = 4 bit 8v
2n distinct analog levels

4v

2v
1v
For 𝑛-bit DAC:

𝑉𝑟𝑒𝑓
o LSB: 𝑏𝑜 = 2𝑛
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011
b3b2b1bo Digital Input Signal
𝑉𝑟𝑒𝑓
o MSB: 𝑏𝑛−1 = 2
8
TYPES OF DACS
oMany types of DACs available
oUsually switches, resistors, and op-amps used to
implement conversion
oTwo Main Types:
 Binary Weighted Resistor
 R-2R Ladder

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BINARY WEIGHTED RESISTOR
oUtilizes a summing op-amp circuit
oWeighted resistors are used to distinguish each bit:
 from the most significant (attached to the lowest resistor 𝑅)
 to the least significant (attached to 2n−1𝑅 )
oTransistors (e.g., Mosfet) can be used to switch between Vref and
ground (bit high or low)

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 BINARY WEIGHTED RESISTOR
oAssume Ideal op-amp Vref
MSB (𝑏𝑛−1
oNo current into op-amp R

oVirtual ground at inverting input 2R I Rf

4R
Vout= -IRf - Vout
+
2n-1R
LSB (bo)

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 BINARY WEIGHTED RESISTOR
o Voltages V1 through Vn are Vref
either Vref if corresponding bit V1 R
is high or ground (zero) if
V2 I Rf
corresponding bit is low 2R
V3 4R
- Vout
o V1 is most significant bit +
Vn 2n-1R
o Vn is least significant bit
MSB

LSB
 V1 V2 V3 Vn 
Vout   IRf   Rf      n -1 
 R 2R 4R 2 R 12
BINARY WEIGHTED RESISTOR
If Rf=R/2
 V1 V2 V3 Vn 
Vout   IRf       n 
2 4 8 2 
For example, a 4-Bit converter yields

 1 1 1 1
Vout  Vref  b3  b2  b1  b0 
 2 4 8 16 
Where b3 corresponds to Bit-3, b2 to Bit-2, etc.

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BINARY WEIGHTED RESISTOR
Advantages
o Simple Construction/Analysis
o Fast Conversion
Disadvantages
o Requires large range of resistors (2048(211):1 for 12-bit DAC) with
necessary high precision for low resistors
o Requires low switch resistances in transistors
o Can be expensive. Therefore, usually limited to 8-bit resolution.

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R-2R LADDER
o Each bit corresponds to a
Vref
switch

o If the bit is high, the

LSB (bo) corresponding switch is
connected to the inverting
input of the op-amp

Bit: 0 0 0 0 o If the bit is low, the

Vout
4-Bit Converter corresponding switch is
connected to ground

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R-2R LADDER
V3
Vref V1 V2 V3
Ideal Op-amp

2R 2R

Req 
2 R 2 R 
R
2R  2R 

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R-2R LADDER
Vref V1 V2 V3 V2 V3

R R

 R  1
V3   V2  V2
 RR 2
I
Likewise,
1
V2  V1
Vout 2
1
V1  Vref
2
Vout   IR

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R-2R LADDER
Results:
Vref V1 V2 V3 1 1 1
V3  Vref , V2  Vref , V1  Vref
8 4 2

 Vref Vref Vref Vref 

Vout   R b3  b2  b1  b0 
 2R 4R 8R 16 R 

Where b3 corresponds to bit 3,

b2 to bit 2, etc.
Vout
If bit n is set, bn=1

If bit n is clear, bn=0

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R-2R LADDER
For a 4-Bit R-2R Ladder

 1 1 1 1
Vout  Vref  b3  b2  b1  b0 
 2 4 8 16 
For general n-Bit R-2R Ladder or Binary Weighted Resister DAC

n
1
Vout  Vref  bn i i
i 1 2
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R-2R LADDER
Advantages
o Only two resistor values (R and 2R)
o Does not require high precision resistors
Disadvantage
o Lower conversion speed than binary weighted DAC

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SPECIFICATIONS OF DACS
oResolution
oSpeed
oSettling time
oLinearity
oErrors (e.g., offset error)

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RESOLUTION
oSmallest analog output that can be measure
oSmallest analog increment corresponding to 1 LSB change
oAn n-bit DAC can resolve 2n distinct analog levels

Vref
Resolution  VLSB 
2n
where n  number of bits

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SPEED
oRate of conversion of a single digital input to its analog equivalent
oConversion rate depends on
 Clock speed of input signal
 Settling time of converter (Time required for the output signal to settle
within +/- ½ LSB of its final value after a given change in input scale)
oWhen the input changes rapidly, the DAC conversion speed must be high

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SETTLING TIME
o Time required for the output signal to settle within +/- ½ LSB of its final value after a given
change in input scale
o Ideally, an instantaneous change in analog voltage would occur when a new binary word
enters into DAC

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LINEARITY
Ideally, a DAC should produce a linear relationship between the digital
input and analog output

Linearity (Ideal) Non-Linearity

Analog Output Signal

Analog Output Signal

0000 0001 0010 0011 0100 0101 0000 0001 0010 0011 0100 0101
Digital Input Signal Digital Input Signal

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OFFSET ERROR

.
o Occurs when there is a

Analog Output
constant offset between the
actual output and the ideal
output

Digital Input

Ideal Output Positive Offset Errorr Negative Offset Error

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CONTENTS
1. Digital to analog converter (DAC)
2. Analog to digital converter (ADC)

27
WHAT IS AN ANALOG-DIGITAL CONVERTER (ADC)?
oAn electronic integrated circuit which converts a signal from
analog (continuous) to digital (discrete) form
oProvides a link between the analog world of transducers and the
digital world of signal processing and data handling

t 28t
 ADC CONVERSION PROCESS
Two main steps of process
1. Sampling
2. Quantization and Encoding
Analog-to-Digital Converter

Quantizing
and
Encoding
Sampling and
Hold
t
Input: Analog Signal t
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ADC PROCESS: SAMPLING & HOLD

Continuous Signal

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 ADC PROCESS: SAMPLING & HOLD
Measuring analog signals at uniform time Continuous
intervals Signal
oIdeally twice as fast as what we are
sampling (sampling rate fs = 2fmax )
t
Nyquist (sampling) theory: A bandlimited analog signal
that has been sampled can be perfectly reconstructed
from an infinite sequence of samples if the sampling rate
fs exceeds 2fmax samples per second, where fmax is the
highest frequency in the original signal

o You must sample more than ten times fmax in order for
the reconstructed digital samples to represent the t
original signal Sampling interval
 practically: fs > 2fmax 1
𝑇 =𝑠 31
𝑓𝑠
 ADC PROCESS: SAMPLING & HOLD
Measuring analog signals at uniform time
intervals
oIdeally twice as fast as what we are
sampling (sampling rate fs = 2fmax )

Digital system works with discrete time events

oTaking samples from each location
t

Reflects sampled and hold signal

oDigital approximation
32
 ADC PROCESS
Quantizing Encoding
Separating the input signal into a Assigning a unique digital code to each
discrete states with 𝐾 increments state for input
(levels)
𝐾 = 2𝑛
o 𝑛 is the number of bits of the ADC
Analog quantization size
o 𝑄 = (𝑉𝑚𝑎𝑥 − 𝑉𝑚𝑖𝑛)/2𝑛
o 𝑄 is the Resolution

33
 QUANTIZATION & CODING EXAMPLE: 2-BIT
Use original analog signal
11
Apply 2 bit coding
10

01

00
K=22 00
01
10
11

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 QUANTIZATION & CODING EXAMPLE: 3-BIT
Use original analog signal
Apply 3 bit coding

K=23 000
001
010
011
100
101
110
111 35
 QUANTIZATION & CODING EXAMPLE: 3-BIT
Use original analog signal
Apply 3 bit coding
Better representation of input
information with additional bits
Example:
MCS12 has max of 10 bits K=23 000 K=16 0000 K=…
001 .
010 .
011 .
100 1111
101
110
111 36
 QUANTIZING: EXAMPLE
Output Discrete Voltage
States Ranges (V)
You have 0-10V signals 0 0.00-1.25
o Separate them into a set of discrete 1 1.25-2.50
states with 1.25V increments (why
2 2.50-3.75
select 1.25?)
3 3.75-5.00
4 5.00-6.25
5 6.25-7.50
6 7.50-8.75
7 8.75-10.0
37
 SOLUTION
o The number of possible states that the converter can
output is:
𝐾 = 2𝑛
where 𝑛 is the number of bits in the AD converter

oExample: For a 3 bit A/D converter, 𝐾 = 23 = 8

oAnalog quantization size:

𝑄 = (𝑉𝑚𝑎𝑥 − 𝑉𝑚𝑖𝑛)/𝐾 = (10V – 0V)/8 = 1.25V

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ENCODING
Output Output Binary Equivalent
Here we assign the States
digital value (binary 0 000
number) to each state for 1 001
the computer to read.
2 010
3 011
4 100
5 101
6 110
7 111

39
ACCURACY OF A/D CONVERSION
There are two ways to best improve accuracy of A/D conversion:

o increasing the resolution which improves the accuracy in measuring the

amplitude of the analog signal

o increasing the sampling rate which increases the maximum frequency

that can be measured fmax ≤ 0.5 fs

40
 RESOLUTION
o Resolution= Analog Quantization size (Q)
𝑉range
o𝑄 =
2𝑛

where 𝑉range is the range of analog voltages which can be represented

o In our previous example: Q = 1.25V, this is a high resolution

o A lower resolution would be if we used a 2-bit converter, then the resolution
would be 10/ 22 = 2.50V

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TYPES OF ADC
oSuccessive Approximation A/D Converter
oFlash A/D Converter
oDual Slope A/D Converter
oDelta-Sigma A/D Converter

42
SUCCESSIVE APPROXIMATION ADC
Elements
oS/H = Sample and Hold Circuit
oComparator
oDAC = Digital to Analog Converter
oSAR = Successive Approximation Register

Definitions:
oEOC = End of Conversion
oVin = Input Voltage
oVref = Reference Voltage
43
SUCCESSIVE APPROXIMATION ADC
Algorithm: uses an 𝑛 − 𝑏𝑖𝑡 DAC and original analog results
1. Performs a binary comparison of VDAC and Vin
2. MSB is initialized at 1 and all other bits to 0 for DAC
 If Vin < VDAC (VREF / 2) then MSB is reset to 0
 If Vin > VDAC (VREF /2) then successive (next) bit set to 1

3. Algorithm is repeated up to LSB

4. At end DAC in = ADC out
Hint: 𝑛 − 𝑏𝑖𝑡 conversion requires 𝑛 comparison cycles

44
SUCCESSIVE APPROXIMATION ADC – EXAMPLE I
5-bit ADC, Vin=0.6V, Vref=1V
DAC bit/voltage
Cycle 1 => MSB=1
SAR = 1 0 0 0 0 Bit 4 3 2 1 0
VDAC = Vref/2^1 = .5 Vin > VDAC SAR unchanged = 1 0 0 0 0
Voltage .5 .25 .125 .0625 .03125
Cycle 2
SAR = 1 1 0 0 0
VDAC = .5 +.25 = .75 Vin < VDAC SAR bit3 reset to 0 = 1 0 0 0 0

Cycle 3
SAR = 1 0 1 0 0
VDAC = .5 + .125 = .625 Vin < VDAC SAR bit2 reset to 0 = 1 0 0 0 0

Cycle 4
SAR = 1 0 0 1 0
VDAC = .5+.0625=.5625 Vin > VDAC SAR unchanged = 1 0 0 1 0

Cycle 5
SAR = 1 0 0 1 1
VDAC = .5+.0625+.03125= .59375
Vin > VDAC SAR unchanged = 1 0 0 1 1 45
 SUCCESSIVE APPROXIMATION EXAMPLE II
10 bit resolution or 0.0009765625V
of Vref
Vin= .6 volts
Vref=1volts
Find the digital value of Vin

46
SUCCESSIVE APPROXIMATION
MSB (bit 9)
oDivided Vref by 2
oCompare Vref /2 with Vin
 If Vin is greater than Vref /2 , turn MSB on (1)
 If Vin is less than Vref /2 , turn MSB off (0)
oVin =0.6V and V=0.5
oSince Vin>V, MSB = 1 (on)

47
SUCCESSIVE APPROXIMATION
Next Calculate MSB-1 (bit 8)
 Compare Vin=0.6 V to V=Vref/2 + Vref/4= 0.5+0.25 =0.75V
 Since 0.6<0.75, MSB is turned off
Calculate MSB-2 (bit 7)
 Go back to the last voltage that caused it to be turned on (Bit 9) and
add it to Vref/8, and compare with Vin
 Compare Vin with (0.5+Vref/8)=0.625
 Since 0.6<0.625, MSB is turned off

48
SUCCESSIVE APPROXIMATION
Calculate the state of MSB-3 (bit 6)
oGo to the last bit that caused it to be turned on (In this case MSB-1) and add it to
Vref/16, and compare it to Vin
oCompare Vin to V= 0.5 + Vref/16= 0.5625
oSince 0.6>0.5625, MSB-3=1 (turned on)

49
SUCCESSIVE APPROXIMATION
This process continues for all the remaining bits.

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 FLASH ADC
oAlso known as parallel ADC
oElements
 Encoder – Converts output of comparators to binary
 Comparators

51
 FLASH ADC
Algorithm
oVin value lies between two comparators
𝑉𝑟𝑒𝑓
oResolution ∆𝑉 = 𝑛
2
o𝑛= Encoder Output bits
oNo. of comparators =NC= 2𝑛 − 1

Example: Vref = 8V, Encoder 3-bit

8
o Resolution ∆𝑉 = = 1.0V
23
o Comparators 23-1=7

1 additional encoder bit

o we need around 2 x NC 52
 FLASH ADC EXAMPLE
0
Vin = 5.5V, Vref= 8V
0

Vin lies in between Vcomp5 & Vcomp6 1

Vcomp5 = Vref*5/8 = 5V 1
Vcomp6 = Vref*6/8 = 6V
1

1
Comparator 1 - 5 => output 1
Comparator 6 - 7 => output 0 1
5.5V

Encoder Octal Input = sum(0011111) = 5

Encoder Binary Output = 1 0 1
53
 DUAL SLOPE A/D CONVERTER
Also known as an Integrating ADC

+
_

Control
Logic
Start Stop
Clock Counter
54
DELTA-SIGMA A/D CONVERTER
Analog Delta-Sigma Low-Pass Digital
Input Modulator Filter Output

55
 DELTA-SIGMA ADC – HOW IT WORKS
oInput over sampled, goes to integrator
oIntegration compared with ground
oIteration drives integration of error to zero
oOutput is a stream of serial bits

56
 COMPARISON OF ADC’S
Speed Cost Resolution
Type
(relative) (relative) (bits) ADC Resolution Comparison
Dual Slope
Dual Slope Slow Med 12-16 Flash

Flash Very Fast High 4-12 Successive Approx

Sigma-Delta
Successive Medium –
Low 8-16 0 5 10 15 20 25
Approx Fast Resolution (Bits)

Sigma –
Slow Low 12-24
Delta

57
QUESTIONS

58