Analogue VLSI Design

Dr. I. Fletcher
 Analogue Circuit Design
Analogue circuits generally use :
• Passive Technology
Resistors, Capacitors and Inductors i.e. filters

Waste silicon area

Difficult to construct/Accuracy
 Double Poly Capacitors
• Active Technology
Diodes, Transistors i.e. Logic, op-amps
 CMOS/BiCMOS construction

Switching frequency
 Digital to Analogue Conversion
DAC’s produce an analogue output which is
proportional to an n-bit digital code input :
Voltage Vref Scaling D.Vref Output Vout
Reference Network Amplifier

Binary
Most Significant Bit (MSB) Latches Least Significant Bit (LSB)
represents the largest switched represents the smallest switched
level that can take place level that can take place
b1 b2 b3 bn
n–bit Digital Signal

As 2n digital codes represent the analogue range, VRange :

VRange VRange 2 n −1VRange VRange
LSB : ≅ MSB : ≅
2n − 1 2n 2n − 1 2
Hence from LSB to MSB then (in voltage terms) : bi ≅ 2bi −1
 Worked Example
A DAC produces an output between 0 and 10V.
How many bits would be needed if its resolution
(LSB Value) was to be ≤ 0.1% of its range ?

Solution : VRange = 10 – 0 = 10V

VRange  0.1 
LSB Value : ≤ VRange  
2n  100 

100
Hence : 2n ≥ n ≥ 10
0.1
 Binary Weighted DAC
b1 I1
VRef R Remember for ‘ideal’ op-amps :
b2 I2 • Virtual Earth V+ = V-
2R
b3 I3 • Zero Input Current
4R
b4 I4
8R
b5 I5 Rf
16R
b6 I6
32R I _
b7 I7
64R Vo
b8 I8 +
128R

As each bit switches in an input of 0 or VRef then :

VO  b1 b2 b3 b 
I =− = + + + L + 8 VRef
R f  R 2R 4R 128R 

By making Rf = R/2 then : VO = − 1 +

b b2 b3 b 
+ + L + nn VRef
2 4 8 2 
 Binary Weighted DAC Issues
The main issue is not just the silicon area required
to implement a resistor but the wide range of
resistor values needed to implement it !
Requiring greater area/accuracy of construction
Possible Solutions include :
• Parallel/Serial Hybrid
Sacrifices speed for size, still accuracy issues
• Matched Parallel Transistor Switching Current
Matching transistor currents for accuracy
• R/2R Ladder Conversion
 R/2R Ladder DAC
i i/2 I1 The bit currents are formed
b1
VRef 2R I2 irrespective of the bit values as
R i/4 b2
2R I3
• b=0 Switched to Ground
R i/8 b3 • b=1 Virtual Earth Ground
2R I4
As the switch will be R i/16 b4
grounded irrespective 2R I5
R i/32 b5 Rf
of the bit values then as 2R I6
R i/64 b6 I
• 2R’s in parallel are R 2R I7 _
• R’s in series are 2R R i/128 b7
2R I8
Vo
then : R i/256 b8 +
V 2R
i=
Ref

R 2R

As each bit switches in then the bit currents are

switched through to the amplifier if b=1 (else ‘0A’) :
 Rf  b1 b2 b3 b 
VO = −VRef   + + + L + nn 
 R  2 4 8 2 
More transistors, power consumption, floating nodes !
 Switched Voltage DAC
VRef
R
R
R
n-bit
MUX Vo

R
R

b1 b2 b3 bn-1 bn

The input switching network is the limiting factor as :

• 2n-1 identical R’s needed to produce 2n voltage levels
• Maximum output voltage is VRef (No Gain)
• nR << Input impedance of MUX
Again, avoiding floating nodes avoids speed
reduction due to parasitic capacitance !
 Switched Capacitor DAC
+
C/2n-1 C/2n-1 C/2 C _ Vo

φ1 φ2.bn φ2.b2 φ2.b1

VRef
φ2.bn φ1 φ2.b2 φ1 φ2.b1 φ1

During phase 1 of the clock ( φ1 ) :

System reset by discharging all capacitors via S/C
During phase 2 of the clock ( φ2 ) :
 CC 
bi = 0 Ci remains uncharged VO =  VRef
 2C 
bi = 1 Ci charged to VRef Where CC is the total
charged capacitance.
 Worked Example
Prove the output voltage equation for the switched
capacitor DAC.
Solution :
C C C
Total Capacitance : As in parallel n −1
+ n −1
+ L + + C = 2C
2 2 2
During φ2 : 2C-CC CC
Vo
Where CC is the sum of all
the charged capacitors
(as in parallel)
0V VRef
As charge will balance (in series) :
Q = CV = (CC )(VRef − VO ) = (2C − CC )(VO − 0)
C 
Hence : (CC )VRef = (2C )VO VO =  C VRef
 2C 
 Charge Redistribution DAC
bi.clk clk

VRef bi.clk C1 VC1 C2 VC2 Reset VO

Reset discharges
During the clock low ( clk ) : VC2 and hence VO
prior to conversion!
bi = 0 C1 discharged to 0V
bi = 1 C1 charged to VRef
During the clock high ( clk ) :
Charge shared between C1 and C2 VO = VC2
After n clocks the
Linear and ‘halved’ if C1 = C2 ! conversion is complete
 Charge Redistribution Operation
bi.clk clk

VRef bi.clk C1 VC1 C2 VC2 Reset VO

b1 (1) b2 (0) b3 (1) b4 (0)

Consider the Serial data entered
conversion of the CLK LSB to MSB as last
4-bit digital word bit adds the most to
0101 (MSB-LSB) 1.00 the final value !
when C1 = C2 0.75
VC1/VRef 0.50
Theoretically : 0.25
( 0 +1 + 0 + 1 )V 0.00 time
2 4 8 16 Ref
0.3125VRef 1.00
0.75
VC2/VRef 0.50
0.25
0.00
0.3125VRef
time

 Worked Example
Develop an expression for the charge sharing and
hence show that if C1 = C2 it is halved !
Solution :
Total charge when CLK=‘0’ :
QT = QC1 + QC2 = C1Vbi + C2VOi−1
Total charge when CLK=‘1’ : As C1 and C2 in parallel !
QT = (C1 + C2 )VOi
If C1 = C2 then :
Hence :
C1Vbi + C2VOi−1 Vbi VOi−1
VOi = = +
C1 + C2 2 2
A nonlinear conversion if C1 ≠ C2 !
 Algorithmic DAC
A 1/2 B 1/2 C 1/2
0 Σ Z -1 Σ Z -1 Σ Z -1 Σ Z -1 VO

LSB b4 b3 b2 MSB b1

-Vref
+Vref

Which uses the Z-transform notation, where :

One clock Delay ≡ z −1 Clock not needed provided
sufficient time for LSB to
n − clock Delays ≡ z − n reach VO allowed !

Hence it takes n-clocks for the LSB to reach VO and :

 −1 b2 − 2 b3 −3 b4 − 4 bn − n 
Vo( z ) =  b1.z + .z + 2 .z + 3 .z + ..... + n −1 .z Vref
 2 2 2 2 
2n − 1 2n − 1
where − 1 ≤ bi ≤ +1 and − n −1 .Vref ≤ VO ≤ + n −1 .Vref
2 2
 Worked Example
Show how the Algorithmic DAC performs the
conversion 0111 (MSB to LSB)
A 1/2 B 1/2 C 1/2
0 Σ Z-1 Σ Z-1 Σ Z-1 Σ Z-1 VO

LSB b14 b13 b12 MSB b01

-Vref
+Vref

Clock
Solution : 1 2 3 4
A +VRef +VRef +VRef +VRef
B +VRef +3VRef /2 +3VRef /2 +3VRef /2
C +VRef +3VRef /2 +7VRef /4 +7VRef /4
VO -VRef -VRef /2 -VRef /4 -VRef /8
 Analogue to Digital Conversion
Analogue to Digital Conversion (ADC) requires
control logic to determine the equivalent digital
code to the current analogue input :
Analogue
Input
Vin + Error Control
_ Logic

n-bit
digital
word
Vd
DAC
Analogue version of
the digital equivalent

The negative feedback structure allows

the control logic to minimise the error !
 Counter ADC
Simplest ADC uses a reset counter to determine
the digital equivalent :
100% Error changes
sign !
Vin + Error Reset
Counter 75% Vin
_

50%
Vd 1 LSB
Vd DAC 25%
1 clock

0%
Time (clock Pulses)

Simple Control Strategy

Slow as LSB at a time !
Must allow a full count to guarantee
conversion so slower as n increases !
 Tracker ADC
By using an up-down counter then the ADC can be
used to ‘track’ the analogue input signal :
100% Error changes
sign !
Vin + Error Up/Down 75% Vin
_ Counter

50%
Vd 1 LSB
Vd DAC 25%
1 clock

0%
Time (clock Pulses)

Provided the clock speed allows the analogue signal to be

tracked then a conversion can take place whenever desired !
 Vspan  dV
i.e.  n . fc > in
 2  dt max
 Successive Approximation ADC
For greater conversion speed the control logic
decides on the bit values from MSB to LSB :
100%
Error -ve so
Vin b2 bit not set
+ Error Bit Select 75% Vin
_ & Storage Vd
b4
MSB b3
50%
b1
Error +ve
Vd DAC 25% so bit set

0%
Time (clock Pulses)

So converter requires n-clocks to guarantee conversion !

Conversion time takes n/fc
Extra hardware for control reduces fc
 SAC ADC
Electronic hardware circuit :
start Shift register recognises each bit
clk n-bit shift register in turn from MSB to LSB
AND gates make the decision for
& & & the currently identified bit
start
'0'
K clr J K clr J K clr J Flip-flops store bit value if error for
the current bit is +ve ( JK = 10 )
clk
1 1 1 OR gates pass any previously stored bits
and the currently identified bit to DAC
MSB LSB
DAC

Vin Vd DAC and comparator generate the

_ conversion error ( +ve if Vin > Vd )
+

Error Prior to start the shift register is

initialised to 1000…00 and the
flip-flops are cleared !
 Worked Example
Design the successive approximation (SAC) ADC
shift register logic using D-Type flip-flops (you may
assume that preset/clear operation is active low).
Solution :
Preset/Clear operations PR CLR Qn Qn
are independent of clock 0 1 1 0
Start = ‘0’
and active low operation 1 0 0 1
means : 1 1 Disabled Start = ‘1’
MSB LSB
‘0' D1 Q1 D2 Q2 D3 Q3 Dn Qn
Pre Clr Pre Clr Pre Clr Pre Clr
Start
‘1'
Clk

All zero contents can be used to signal conversion end !

 Serial Slope ADC’s
Slope ADC’s integrate the analogue input so that
the subsequent rate of change is timed using a
counter whose output, ncount, is equivalent to VADC :
Vin Accuracy a function of :
Single VRef
Slope RC
• Integrator Gain ( RC )
ADC • Reference Voltage ( VRef )
ncount / f C
• Counter Frequency ( fC )
Hence :
Dual Vin − VRef
 1   2 − 1   1   ncount
n

Slope RC RC  Vin   = Vref  
 RC   f c   RC   f c 
ADC  Vin 
(2 n
)
− 1 / fC ncount / f C
( n
)
ncount ≈ 2 − 1 
V 

 ref 
Accuracy requires VRef = Vin max!
 Algorithmic ADC
b1 b2 b3 b4
MSB LSB
+ + + +
_ _ _ _

2 2 2
Vin Σ Z -1 Σ Z -1 Σ Z -1

+1 -1 +1 -1 +1 -1
where − 1 ≤ bi ≤ +1 and
-Vref
+Vref range − VRef ≤ VADC ≤ +VRef

Hence it requires n-1 clocks for Vin to reach the LSB

decision comparator before the conversion is complete !
Accuracy a function of :
• Multiplier Gain’s ( 2 )
• Comparator’s zero switching
 Worked Example
Show how the Algorithmic ADC performs the
conversion of -2V ( VRef = 10V ) .
b1 b2 b3 b4
MSB LSB
+ + + +
_ _ _ _

2 2 2
-2V
Vin Σ Z -1 Σ Z -1 Σ Z-1

+1 -1 +1 -1 +1 -1
-Vref
+Vref

Solution : -2V < 0V b1 = 0 2(-2) + 10 = +6V

+6V > 0V b2 = 1 2(+6) - 10 = +2V
+2V > 0V b3 = 1 2(+2) - 10 = -6V
-6V < 0V b4 = 0 -3/16VRef = -1.875V
 Serial Algorithmic ADC
A clocked device for timing purposes that cannot
be free-ran like the previous convertors.
Vb
Z -1 x2 Digital

+
_ output
Va
+VRef
+1
+VRef
Σ -1
Vin -1 Gnd

The above converter is unipolar ( 0 ≤ Vin ≤ VRef ) !

For a bipolar device then you
must compare with respect to 0V
and switch to +/- VRef !
 Worked Example
Show how a unipolar serial 8-bit ADC converts the
analogue input of 3.5V, given VRef = 10V.
Vb
Z -1 x2 Digital

+
_ output
Va
+VRef
+1
+VRef
Σ -1
Vin -1 Gnd

Clock No. 1 2 3 4 5 6 7 8
Solution : Va/Vref 0.35 0.70 0.40 0.80 0.60 0.20 0.40 0.80
Vb/Vref 0.70 1.40 0.80 1.60 1.20 0.40 0.80 1.60
Output 0 1 0 1 1 0 0 1
0 1 0 1 1 0 0 1 
Vin = 10 + + + + + + +  ≅ 3.477V
*
Check :
 2 4 8 16 32 64 128 256 
 Parallel ADC
VRef Vin

R
+_
R
+_
R
+_
R Digital
Encoding
Shift Digital
Network
Register output
R
+_
R
+_
R

• Fastest Conversion
• Large Area : Doubling every bit
2n Identical Resistors
• Accuracy requires : 2n-1 Identical Comparators
 Switched Capacitors
Previous lessons have shown the problems
associated with implementing resistors in VLSI
technology.
One alternative approach is to use high
frequency switched capacitor circuits :
φ1 φ2
I I
R
Vin Vout Vin C Vout

Vin − Vout
Ohm’s Law : I =
R
 Switched Capacitor
φ
Analysis
φ1 φ2
I

Vin C Vout

Analysing the average current/clock cycle :

1 dq (t )  dq (t ) 
T T T
1
() ∫ T ∫
I= it =
dt = dt  T 
T 0 0
dt  0
Assuming that the voltages are constant over the clock
period, T : φ (0 to T/2) : [dq (t )]T/2 = C (V − V )
1 0 in out C (Vin − Vout )
I=
φ2 (T/2 to T) : [dq (t )]TT/2 = 0 T

T 1
Reff = =
C f C .C
 Alternative SC Circuits - 1
The previous SC network is a parallel realisation.
Alternative forms used are :
φ1 φ2

Series SC : 1
Vin Vout Reff =
C fCC

φ1 φ2

Series-Parallel 1
Reff =
f C (C1 + C2 )
SC : Vin Vout
C1 C2
 Alternative SC Circuits - 2
φ1 φ2

C 1
Bilinear SC : Vin Vout Reff =
4f C C
φ2 φ1

φ1 φ2
C

Stray-Insensitive 1
Vin φ2 φ1 Vout Reff =
SC : fCC

This structure prevents the stray capacitances of

the transistors from contributing charge to C
and hence does not affect the circuits accuracy !
 ‘Analogue’ SC Filters
Passive analogue filters can be constructed using
SC’s in RC networks.
For example consider a first order LPF :
φ1 φ2

R
Vin C Vout Vin CR C Vout

RC Time Constant Accuracy CMOS

Filter (τ) Implementation
Passive δR δC
R.C + 5 → 20%
R C
SC C δC δC R δf C
f C .C R C
−
CR
−
fC
≅ 0.1%
 Frequency Response
The ability of the SC networks to approximate
their continuous time counterparts is best shown
by analysing their frequency responses.
For example consider the 1 1 1
H (s ) = = =
Previous first order LPF : sRC + 1 sτ + 1 s / ω0 + 1
1.0
Normalised 0.9
ω0 = 1 )
Normalised (ω
st
1 order LPF
Filter’s 0.8
Magnitude 0.7 ωc/ω
ωo = 10
0.6
0.5
0.4
0.3
0.2
0.1 ωc/ω
ωo = 100
0.0
10 -1 10 0 ω/ω
ωc 10 1 10 2
 ‘Active’ SC Filters
Operational amplifiers can also be used to
construct ‘Analogue’ filters using SC’s.
For example consider an integrator :
φ1 φ2
C C
R _ _
+

+
Vin Vout Vin CR Vout

Where :
Vout ( s) 1 1 f C .CR
=− =−
Vin ( s) sReff C s C
 ‘Active’ SC Filters Feedback
Certain SC circuits are no good for resistive
feedback in op-amp circuits as the input-output
connection must be present at all times.
For example consider φ1 φ2
a differentiator :
R
C
_
CR

C

+
_
Vin Vout
φ1
+

Vin Vout

C
_ CR

+
Vin Vout
 Worked Example
R1 R2
Sketch a non-inverting 1st
_
order active LPF filter using R

+
Vin C Vout
Bilinear SC circuits.
Solution : φ1 φ2 φ1 φ2
OK as feedback
Vout (s )  R1 + R2   1  C1 C2 present during both
=    
Vin (s )  R1   sRC +1  clock phases !

  φ2 φ1 φ2 φ1
 
 C + C2   1 
=  1    _
 C 
  s C  CR
 

+
  4f C  + 1 
2

  C R  Vin C Vout
φ1 φ2
 Tutorial Questions
1. Design the Algorithmic DAC to perform a
unipolar conversion from 0 to VRef
2. How long would an 8-bit Counter DAC take to
convert a 2V input if the DAC output is in the
range -10V to +10V and fC = 2MHz.
3. Develop an expression for the clock speed that
is required to allow the tracking ADC to follow
an input of bandwidth ωS.
4. Derive the effective resistance of :
i) Series SC
ii) Parallel-Series SC
 Tutorial Solution – Q1
A 1/2 B 1/2 C 1/2
0 Σ Z -1 Σ Z -1 Σ Z -1 Σ Z -1 VO

LSB b4 b3 b2 MSB b1

VIN(-)
VIN(+)

 b b b b 
Where : VO ( z ) =  b1.z −1 + 2 .z − 2 + 32 .z −3 + 43 .z − 4 + ..... + nn−1 .z − n VIN
 2 2 2 2 
 2n − 1 
If b’s all Zero’s : VO ( z ) =  n −1 VIN (− ) = ‘0’ VIN(-) = 0
 2 
 2n − 1 
If b’s all One’s : VO ( z ) =  n −1 VIN (+ ) = ‘VRef ’ VIN(+) ≅ VRef
 2 
 2 n −1 
Exactly : VIN (+ ) =  n .VRef → VRef !
 2 −1 
n →∞
 Tutorial Solution – Q2
+10V Error changes
sign !
5V
2V
0V
Vd 1 LSB
-5V
1 clock
-10V
Time (clock Pulses)

Where Vin is a fraction of the DAC range of :

 Vin − VDACmin   2 − (− 10 ) 
=  =
*
Vin  = 0 .6
 VDAC − VDAC   10 − (− 10 ) 
 max min 
2n 28
which covers the full range in : Tmax = = = 128 µsec
fC 2 × 10 6

Hence time to
TC = Vin Tmax = 76.8 = 77 µsec
*

convert is :
 Tutorial Solution – Q3
System of bandwidth ωS has a maximum rate of change of
dA sin(ωS t )
= AωS cos(ωS t ) ω =0 = AωS volts/sec
dt S

to fit the ADC range then : 2 A = Vrange

Vrange VrangeωS 2 n ωS
hence : n
≥ fC ≥ = 2n π f S
2 / fC 2 2
10

Normalised sine 8
Using 8-Bit
wave ( ωS = 1 ) 7
Conversion :
6
fC=128Hz
5

4
fC=96Hz
3
fC=64Hz
2

0
0 1 2 3 4 5 6
 Tutorial Solution – Q4(i)
φ1 φ2

 dq (t ) 
T

Series SC : I= 
Vin Vout  T 0
C

Assuming that the voltages are constant over the clock

period, T :
φ1 (0 to T/2) : [dq (t )]T/2
0 =0 C (Vin − Vout )
I=
φ2 (T/2 to T) : [dq (t )]TT/2 = C (Vin − V0 ) T

T 1
Reff = =
C f C .C
 Tutorial Solution – Q4(ii)
φ1 φ2

 dq (t ) 
T
Series-Parallel
I= 
SC : Vin Vout  T 0
C1 C2

Assuming that the voltages are constant over the clock

period, T :
φ1 (0 to T/2) : [dq (t )]T/2
0 = C 2Vin (C1 + C2 )(Vin −Vout )
I=
φ2 (T/2 to T) : [dq (t )]TT/2 = C1 (Vin − Vout ) − C2Vout T

T 1
Reff = =
C1 + C 2 f C .(C1 + C 2 )