ADC Architectures

EE247
Lecture 19
ADC Converters
– ADC architectures and design (continued)
• Flash ADC and its sources of error: comparator offset,
sparkle code & meta-stability
– Comparator design
• Single-stage open-loop amplifier
• Cascade of open-loop amplifiers
• Problem associated with DC offset
– Cascaded output series cancellation
– Input series cancellation
– Offset cancellation through additional input pair plus offset
storage capacitors
• Latched comparators
• Comparator examples
EECS 247 Lecture 19: Data Converters- Flash ADC- Comparator Design © 2009 Page 1
ADC Architectures
• Slope type converters
• Successive approximation
• Flash
• Time-interleaved / parallel converter
• Folding
• Residue type ADCs
– Two-step
– Pipeline
–…
• Oversampled ADCs
Flash ADC
• B-bit flash ADC:
– DAC generates all possible 2B -1
levels VREF VIN fs
– 2B-1 comparators compare VIN to +

DAC outputs -
+
-
– Comparator output:
• If VDAC < VIN Æ 1 D +
• If VDAC > VIN Æ0 - 2B-1ÆB
A Digital
Encoder Output
– Comparator outputs form C
thermometer code +
-
+
– Encoder converts thermometer to -
binary code
• Application example: 6-bit Flash
ADC in Disk Drives with Gs/s
conversion rate
Flash ADC Converter

Example: 3-bit Conversion Ther
mom
VIN et
VIN VREF fs code er
VREF
0
Binary
0 B-bits
1 1
Encoder
0
1
1
1
Ts 1
Time
Flash Converter Characteristics
VIN VREF fs
• Very fast: only 1 clock cycle
per conversion
– ½ clock cycleÆ VIN & VDAC
comparison
– ½ clock cycleÆ 2B -1 to B
Encoder
encoding
• High complexity:
2B-1 comparators
• Input capacitance of 2B-1

comparators connected to the B-bits
input node:
Æ High capacitance @ input Thermometer
node code
Flash Converter Sources of Error

VREF VIN fs • Comparator input:
R/2
– DC offset
– Nonlinear input capacitance
R – Feedthrough of input signal to
R
reference ladder
– Kickback noise (disturbs
.. Digital
Encoder
.. Output reference)
. – Signal dependent sampling
R time
R
• Comparator output:
R/2 – Sparkle codes (… 0001011111)
– Metastability
Flash ADC Converter
Example: 8-bit ADC Comparator Offset Considerations
VREF VIN fs
• 8-bitÆ 255 comparators
R/2
• VREF=1V Æ 1LSB=4mV R
R
• DNL<1/2LSB Æ
Comparator input referred .. Digital
Encoder
offset < 2mV .. Output
.
• Assuming close to 100% R
yield, 2mV =6σoffset
R
Æ σoffset < 0.33mV
R/2
Flash ADC Converter

Example: 8-bits ADC (continued)
Æ 1σOffset < 0.33mV
• Let us assume in the technology used:
– Voffset-per-unit-sqrt(WxL)=3 mVx μ
3mV
V0 ffset = = 0.33mV → W × L = 83μ 2
W ×L
2
Assuming: Cox = 9 fF / μ 2 → CGS = CoxW × L = 496 fF
3
→ Total max. input capacitance: 255 × 0.496 = 126.5 pF !
– Issues:
• Si area quite large
• Large ADC input capacitance
• Since depending on input voltage level different number of comparator input
transistors would be on/off- total input capacitance varies as input varies
Æ Nonlinear input capacitance could give rise to signal distortion
Ref: M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, "Matching properties of MOS
transistors," IEEE Journal of Solid-State Circuits, vol. 24, pp. 1433 - 1439, October 1989.
Flash ADC Converter
Example (continued)
Trade-offs:
– Allowing larger DNL e.g. 1LSB instead of 0.5LSB:
• Increases the maximum allowable input-referred offset voltage by
a factor of 2
• Decreases the required device WxL by a factor of 4
• Reduces the input device area by a factor of 4
• Reduces the input capacitance by a factor of 4!
– Reducing the ADC resolution by 1-bit
• Increases the maximum allowable input-referred offset voltage by
a factor of 2
• Decreases the required device WxL by a factor of 4
• Reduces the input device area by a factor of 4
• Reduce the input capacitance by a factor of 4
Flash Converter
Maximum Tolerable Comparator Offset versus ADC Resolution
Assumption:
Maximum Comparator Voffset [mV]
102
DNL=0.5LSB
Note:
Graph shows 10 VREF=2V
max. tolerable
offset, note that VREF=1V
depending on min
1
acceptable yield,
the derived offset
numbers are
associated with 10-1
2σ to 6σ offset 4 6 8 10
voltage ADC Resolution
Typical Flash Output Encoder
VDD
Thermometer b3 Binary
code b2
1-of-n b1 B-bits
code b0
0 • Thermometer code
0 Æ 1-of-n decoding
0
• Final encoding Æ
1 NOR ROM
1
0 • Ideally, for each
1 code, only one ROM
row is on
0
1 b3 b2 b1 b0
Thermometer to Binary encoder ROM OutputÆ 0 0 1 1
Sparkle Codes
VDD
b3
Erroneous 0 b2
(comparator offset?) b1
b0
Correct Output:
0 1000
1
1 Problem: Two rows
0 are on
0
1 Erroneous Output:
1 1110
0
1
Æ Up to ~ ½ FS
error!!
Sparkle Tolerant Encoder
0 0
0 1
1 0
0 0
1 0
• Protects against a single sparkle.

• Possible to improve level of sparkle protection by increasing # of NAND
gate inputs
Ref: C. Mangelsdorf et al, “A 400-MHz Flash Converter with Error Correction,” JSSC February
1990, pp. 997-1002
Meta-Stability
Different gates interpret
0 metastable output X differently
0
0 Correct output: 1000
1
X Erroneous output: 0000
1
1 Solutions:
0 –Add latches to comparator
1 outputs (high power)
–Gray encoding
Ref: C. Portmann and T. Meng, “Power-Efficient Metastability Error Reduction in CMOS Flash
A/D Converters,” JSSC August 1996, pp. 1132-40
Gray Encoding
Example: 3bit ADC
Thermometer Code Gray Binary
T7 T6 T5 T4 T3 T2 T1 G3 G2 G1 B3 B2 B1
0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 1 0 0 1 0 0 1 G1 = T1T3 + T5 T7
0 0 0 0 0 1 1 0 1 1 0 1 0
0 0 0 0 1 1 1 0 1 0 0 1 1
G2 = T2 T6
0 0 0 1 1 1 1 1 1 0 1 0 0 G3 = T4
0 0 1 1 1 1 1 1 1 1 1 0 1
0 1 1 1 1 1 1 1 0 1 1 1 0
1 1 1 1 1 1 1 1 0 0 1 1 1
• Each Ti affects only one Gi

Æ Avoids disagreement of interpretation by multiple gates
• Protects also against sparkles
• Follow Gray encoder by (latch and) binary encoder
Voltage Comparators
VDD
Vi+ +
Vout (Digital Output)
Vi- -
Play an important role in majority of ADCs

Function: Compare the instantaneous value of two analog signals &
generate a digital output voltage based on the sign of the
difference:
If Vi+ -Vi- > 0 Æ Vout=“1”

If Vi+ -Vi- < 0 Æ Vout=“0”
Voltage Comparator
Architectures
Comparator architectures:
• High gain amplifier with differential analog input & single-ended large
swing output
– Output swing has to be compatible with driving digital logic circuits
– Open-loop amplificationÆ no frequency compensation required
– Precise gain not required
• Latched comparators; in response to a strobe (clock edge), input stage

disabled & digital output stored in a latch till next strobe
– Two options for implementation :
• Latch-only comparator
• Low-gain preamplifier + high-sensitivity latch
• Sampled-data comparators
– T/H input
– Offset cancellation
Comparator Built with High-Gain Amplifier
Amplify Vin(min) to VDD

Æ Vin(min) determined by ADC
resolution
Example: 12-bit ADC with:

- VFS= 1.5VÆ 1LSB=0.36mV
- VDD=1.8V
Æ For 1.8V output & 0.5LSB

precision:
1.8V
Av Mi n = ≈ 10,000
0.18mV
Comparator Design
1-Single-Stage Amplification
• Amplifier maximum Gain-Bandwidth product (fu) for a given technology,
typically a function of maximum device ft
f
fu = un i t y-g a i n f r e q uency, fo=- 3d B f r eq u en cy fo = u
AV
Example: fu=10 GHz & AV = 10,000
Magnitude
1 0GH z
fo = ≈ 1MHz
1 0,0 00 Av
1
τ set t li ng = = 0 . 16 μ s ec
2π fo fu=0.1-10GHz
A l l o w a f ew τ f or ou t p u t t o s et t l e
1 f0 fu freq.
fCMax.
l ock → ≈ 1 .2 6MHz
5τ s ett li ng Assumption: Single pole amplifier
Too slow for majority of applications!
Æ Try cascade of lower gain stages to broaden frequency of operation
Comparator Design
2- Cascade of Open Loop Amplifiers
The stages identical Æ small-signal model for the cascades:
One stage:
Open Loop Cascade of Amplifiers
Example: N=4, AT=10000Æ ωoN=430 ωo1

For |AT(DC)|=10,000
Example:
N=3, fu=10GHz & AT ( 0 ) = 10000
10GHz
foN = 21/ 3−1 ≈ 237MHz
(10,000 )1/ 3
1
τ settling = = 0.7n sec
2π fo
Allow a few τ for output to settle
Max. 1
fClock → ≈ 290MHz
5τ settling
fmax improved from 1.26MHz to 290MHz Æ X236
Offset Voltage
• From offset point

of view: high
gain/stage is
preferred
• Choice of # of
stage
Æbandwidth vs
offset tradeoff
Input-referred offset Æ

Step Response
• Assuming linear behavior (not slew limited)
Step Response
•Assuming linear behavior

Delay/(C/gm)
Delay/(C/gm)
1/ N
C ⎡ ⎤
τ D = ⎛⎜ ⎞⎟ ⎢( N ! ) ⎛⎜ out ⎞⎟⎥
V
g
⎝ m ⎠⎣ V
⎝ i n ⎠⎦
• Minimum total delay broad

function of N
• Relationship between # of stages
resulting in minimize delay (Nop)
and gain (Vout/Vin) approximately:
No p t ≈ 1 + l og2 AT f or A < 1000
No p t ≈ 1.2l n AT for A ≥ 1000
Ref: J.T. Wu, et al., “A 100-MHz pipelined CMOS comparator ” IEEE Journal of Solid-State
Circuits, vol. 23, pp. 1379 - 1385, December 1988.
Offset Cancellation
• Offset cancellation for sampled-data cascade of

amplifiers can be performed by:
1. Store offset on ac-coupling caps in series with amp stages:
Offset associated with a specific amp can be cancelled by
storing it in series with either the input or the output of that
stage
2. Offset can be cancelled by adding a pair of auxiliary inputs
to the amplifier and storing the offset on capacitors
connected to the aux. inputs during offset cancellation
phase
Offset Cancellation
Output Series Cancellation
• Amp modeled as ideal
+ Vos (input referred)
1- Store offset:
• S1, S4Î open
• S2, S3Æ closed
Æ VC=AxVOS
Offset Cancellation
2- Amplification phase:
• S2, S3Æ open
• S1, S4Î closed
ÆVC=AxVOS
Circuit requirements:
• Amp not saturate during offset
storage
• High-impedance (C) load Æ Cc not
discharged
• Cc >> CL to avoid attenuation
• Cc >> Cswitch avoid excessive
additional offset due to charge
injection
Offset Cancellation
Cascaded Output Series Cancellation
Note: Offset storage

capacitors in series with the
amplifier outputs
Offset Cancellation
1- S1Æ open, S2,3,4,5 closed
VC1=A1xVos1
VC2=A2xVos2
VC3=A1xVos3
Offset Cancellation
2- S3Æ open first

• Feedthrough from S3 Æ offset on X
• Switch offset , ε3 induced on node X
• Since S4 remains closed, offset associated with ε3 Æ stored on C2
VX= ε3
VC1=A1xVos1- ε3
VC2=A2x(Vos2+ ε3)
Offset Cancellation
3- S4Æ open
• Feedthrough from S4 Æ offset on Y
• Switch offset , ε4 induces error on node Y
• Since S5 remains closed, offset associated with ε4 Æ stored on C3
VY= ε4
VC2=A2x(Vos2+ ε3) – ε4
VC3=A3x(Vos3+ ε4)
Offset Cancellation
4- S2Æ open, S5Æ open , S1Æ closed

• S2 open & S1 closed Æ since input connected to low impedance
source charge injection not of major concern
• Switch offset , ε5 introduced due to S5 opening
VX = A1x(Vin+Vos1) – VC1
= A1x(Vin+Vos1) – (A1.Vos1- ε3)
=A1.Vin+ ε3
Offset Cancellation
Vy = A2x(Vx+Vos2) – VC2
= A2x(A1Vin + ε3 + Vos2) – [A2.(Vos2+ε3) - ε4]
=A1.A2.Vin + ε4
Vout = A3x(Vy+Vos3) – VC3

= A3.(A2xA1Vin + ε4 + Vos3) – [A3.(Vos3+ε4) - ε5]
= A1.A2.A3.Vin + ε5
Offset Cancellation
Vout = A1.A2.A3.(Vin + ε5 /A1.A2.A3)

Input-Referred Offset = ε5 /A1.A2.A3
Example:
3-stage open-loop differential amplifier with series offset cancellation +
output amplifier (see Ref.)
ATotal(DC) = 2x106 = 126dB

Input-referred offset < 5μV
Ref: :R. Poujois and J. Borel, "A low drift fully integrated MOSFET operational amplifier," IEEE
Journal of Solid-State Circuits, vol. 13, pp. 499 - 503, August 1978.
Offset Cancellation
• Advantages:
– Almost compete cancellation
– Closed-loop stability not required
• Disadvantages:
– Gain per stage must be small
– Offset storage C in the signal path Æ could slow
down overall performance
Offset Cancellation
Input Series Cancellation
Offset Cancellation
1- Store offset
Note: Mandates
closed-loop
stability
Offset Cancellation
2- Amplify
S2, S3 Æ open
S1Æ closed
Example: A=4
ÆInput-referred
offset =Vos/5
Offset Cancellation
Cascaded Input Series Cancellation
⎡ Vos2 ε ⎤
Vout = A1A 2 ⎢ Vin + − 4⎥
⎣ A1 ( A 2 + 1) A1⎦
Vos2 ε
Input referred offset: − 4
A1 ( A 2 + 1) A1
ε4 Æcharge injection associated with

opening of S4
Offset Cancellation
• Advantages:
– In applications such as C-array successive
approximation ADCs can use C-array to store
offset
• Disadvantages:
– Cancellation not complete
– Requires closed loop stability
– Offset storage C in the signal path- could slow
down overall performance
CMOS Comparators
Cascade of Gain Stages
Fully differential gain stages Æ 1st order cancellation of switch
feedthrough offset
1- Output series offset cancellation
2- Input series offset cancellation
CMOS Comparators
Cascade of Gain Stages
3-Combined input & output series offset cancellation
Offset Cancellation
• Cancel offset by additional pair of inputs
+ offset storage Cs + an extra clock
phase for offset storage (Lecture 18
slide 28 thru 30)
Latched Comparators
Vi+ Vi+ - Vi-
+ Vout
Vi - - (Digital Output)
t
Latch
Latch
Compares two input voltages
at time tx & generates a digital
output:
tx t
Vout
If Vi+ -Vi- > 0 Æ Vout=“1” “1”
If Vi+ -Vi- < 0 Æ Vout=“0”
“0”
t
CMOS Latched Comparators
Comparator amplification need not be linear
Æ can use a latch Æ regeneration
LatchÆ Amplification + positive feedback
Simplest Form of CMOS Latch
VDD VDD
M3 M4
M1 M2 M1 M2
Small Signal Model
Latch can be modeled as a:
Æ Single-pole amp + positive feedback
Small signal ac half circuit
CMOS Latched Comparator

Latch Delay
V dV
g mV = +C
RL dt
gm ⎛ 1 ⎞ dV gm ⎛ 1 ⎞ dV
1− V= 1− dt =
C ⎜⎝ g m RL ⎟⎠ dt C ⎜⎝ g m RL ⎟⎠ V
gm ⎛ 1 ⎞ t2 V2 1 ⎛ a1 a⎞
g m RL ⎟⎠ ∫t1
dt = ∫ ⎜ ∫b dx = ln x b = ln a − ln b = ln ⎟
a
Integrating both sides: 1− dV
C ⎜⎝ V1 V ⎝ x b⎠
Latch Delay:
C ⎛ 1 ⎞ ⎛ V2 ⎞
tD = t2 − t1 = ⎟ ln ⎜ V ⎟
gm ⎜ 1 − 1
⎜⎜ ⎟⎟ ⎝ 1 ⎠
⎝ g m RL ⎠
For g m RL >> 1
C ⎛ V2 ⎞
tD ≈ ln
g m ⎜⎝ V1 ⎟⎠
Normalized Latch Delay
C ⎛ V2 ⎞ V2 tD
tD ≈ ln AL =
g m ⎜⎝ V1 ⎟⎠ V1 C
gm
V2
→ Latch Gain = AL
V1
τD(3-stage amp)=
C 18.2(C/gm)
→ tD ≈ ln AL
gm
Compared to a 3-stage open-loop

cascade of amps for equal overall gain
of 1000
ÆLatch faster by about x3
Latch-Only Comparator
• Much faster compared to cascade of open-
loop amplifiers
• Main problem associated with latch-only

comparator topology:
– High input-referred offset voltage (as high
as 100mV!)
• Solution:
– Use preamplifier to amplify the signal and
reduce overall input-referred offset
Pre-Amplifier + Latch
Overall Input-Referred Offset
fs
VosPreamp VosLatch
Vi+ Do+
Vi-
Av Latch
Do-
Preamp
Latch offset attenuated by preamp gain when referred to preamp input.

Assuming the two offset sources are uncorrelated:
2 1 2
σ Input − Re ferred _ Offset = σ Vos _ Pr eamp + 2
σ Vos _ Latch
APr eamp
Example : σ Vos _ Pr eamp = 4mV & σ Vos _ Latch = 50mV & APr eamp = 10
1
σ Input − Re ferred _ Offset = 42 + 502 = 6.4mV
102
Pre-Amplifier Tradeoffs
fs
Vi+ Do+
Vi-
Av Latch
Do-
Preamp
• Example:
– Latch offset 50 to 100mV
– Preamp DC gain 10X
– Preamp input-referred latch offset 5 to 10mV
– Input-referred preamplifier offset 2 to 10mV
– Overall input-referred offset 5.5 to 14mV
Æ Addition of preamp reduces the latch input-referred offset

reduced by ~7 to 9X Æ ~allows extra 3-bit resolution for ADC!
Comparator Preamplifier Gain-Speed Tradeoffs
• Amplifier maximum Gain-Bandwidth product (fu) or a given technology, typically a
function of maximum device ft
fu =unity gain frequency, f 0 = −3dB frequency & τ 0 = settling time
fu
f0 =
Apreamp
Magnitude
For example assuming preamp has a gain of 10:
fu 1GHz Av
f0 = = = 100 MHz
Apreamp 10 fu=0.1-10GHz
1 Apreamp
τ0 = = = 1.6n sec f0 fu freq.
2π f 0 2π fu
- Tradeoff:
• To reduce the effect of latch offset Æ high preamp gain desirable
• Fast comparator Æ low preamp gain
Æ Choice of preamp gain: compromise speed v.s. input-referred latch offset
Latched Comparator
fs
Vi+ Do+
Av Latch
Vi- Do-
Preamp
Important features:
– Maximum clock rate fs Æ settling time, slew rate, small signal bandwidth
– ResolutionÆ gain, offset
– Overdrive recovery
– Input capacitance (and linearity of input capacitance!)
– Power dissipation
– Input common-mode range and CMR
– Kickback noise
–…
Comparator Overdrive Recovery
Linear model for a single-pole amplifier:
UÆ amplification after time ta
During reset amplifier settles

exponentially to its zero input Example: Worst case input/output waveforms
condition with τ0=RC
Previous input Æ max. possible e.g. VFS
Assume Vm Æ maximum input Current input Æ min. input-referred signal
normalized to 1/2Lsb (=1) (0.5LSB)
Comparators Overdrive Recovery
Example: Worst case input/output

waveforms
If recovery time is not long enough to allow output to discharge (recover) from
previous state- then it may not be able to resolve the current input Æ error
To minimize this effect:
1. Passive clamp
2. Active restore
3. Low gain/stage
Comparators Overdrive Recovery
Limiting Output Voltage
Active Restore
Clamp
After outputs are latched by following stage
Adds parasitic capacitance
Æ Activate φR & equalize output nodes
CMOS Preamplifier + Latched Comparator

Delay in Response
Latch delay previously found:
C ⎛ V2 ⎞
τD ≈ ln
g m ⎜⎝ V1 ⎟⎠
Assuming gain of Av for the preamplifier then :V1 = Av × Vin
C ⎛ V0 ⎞
τD ≈ ln
g m ⎜⎝ AvVin ⎟⎠
Latched Comparator Including Preamplifier
Example
VDD
M5 M3 M4 M6
-
Vo
CLK +
Preamplifier gain:
M1 M2
g mM 1 (VGS − Vth ) +
M3 M3
Av = = Vin M9
g mM 3 (VGSM 1 − VthM 1 ) -
bias M7 M8
Comparator delay:
(for simplicity, preamp delay ignored)
C ⎛ V0 ⎞
τD ≈ ln
g m ⎜⎝ AvVin ⎟⎠ Preamp Latch
Comparator Dynamic Behavior

Comparator Reset Comparator Decision
CLK
TCLK
vO+
τdelay
vOUT
vO-
Comparator Resolution
CLK
VIN =10mV
1mV
0.1mV
vOUT 10μV
Δt = (gm/C).ln(Vin1/Vin2)
Note: For small Vin the comparator may not be able to make a
decision within the allotted time Æoutput ambiguous
Comparator Voltage Transfer Function

Non-Idealities
Vout
ε
VOffset
-0.5LSB 0.5LSB
Vin
VOffset Æ Comparator offset voltage

ε Æ Meta-Stable region (output ambiguous)

ADC Architectures

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EE247

– 2B-1 comparators compare VIN to +

Flash ADC Converter

• Input capacitance of 2B-1

Flash Converter Sources of Error

Flash ADC Converter

• Protects against a single sparkle.

• Each Ti affects only one Gi

Play an important role in majority of ADCs

If Vi+ -Vi- > 0 Æ Vout=“1”

• Latched comparators; in response to a strobe (clock edge), input stage

Comparator Built with High-Gain Amplifier

Amplify Vin(min) to VDD

Example: 12-bit ADC with:

Æ For 1.8V output & 0.5LSB

The stages identical Æ small-signal model for the cascades:

Example: N=4, AT=10000Æ ωoN=430 ωo1

Open Loop Cascade of Amplifiers

fmax improved from 1.26MHz to 290MHz Æ X236

• From offset point

Open Loop Cascade of Amplifiers

Open Loop Cascade of Amplifiers

• Minimum total delay broad

No p t ≈ 1 + l og2 AT f or A < 1000

No p t ≈ 1.2l n AT for A ≥ 1000

• Offset cancellation for sampled-data cascade of

Note: Offset storage

1- S1Æ open, S2,3,4,5 closed

2- S3Æ open first

4- S2Æ open, S5Æ open , S1Æ closed

Vout = A3x(Vy+Vos3) – VC3

Vout = A1.A2.A3.(Vin + ε5 /A1.A2.A3)

ATotal(DC) = 2x106 = 126dB

ε4 Æcharge injection associated with

1- Output series offset cancellation

2- Input series offset cancellation

LatchÆ Amplification + positive feedback

Simplest Form of CMOS Latch

Small signal ac half circuit

CMOS Latched Comparator

Compared to a 3-stage open-loop

• Main problem associated with latch-only

Latch offset attenuated by preamp gain when referred to preamp input.

Æ Addition of preamp reduces the latch input-referred offset

UÆ amplification after time ta

During reset amplifier settles

Comparators Overdrive Recovery

Example: Worst case input/output

CMOS Preamplifier + Latched Comparator

Latch delay previously found:

Assuming gain of Av for the preamplifier then :V1 = Av × Vin

Comparator Dynamic Behavior

Comparator Voltage Transfer Function

VOffset Æ Comparator offset voltage

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