DA Converters

D I G I TA L E L E C T R O N I C S I I C O U R S E

SCHOOL OF ELECTRONIC ENGINEERING

U P T C S O G AM O S O FAC U LT Y

1
 Digital-to-Analog Conversion Methods

a) Binary-weighted-input DAC:
The binary-weighted-input DAC is a basic DAC in which the input current in
each resistor is proportional to the column weight in the binary numbering
system. It requires very accurate resistors and identical HIGH level voltages
for accuracy.

LSB 8R
D0 Rf
The MSB is represented by + –
I0
the largest current, so it has 4R If
the smallest resistor. To D1
I1 –
simplify analysis, assume all 2R Vou
D2 t
current goes through R f and I=0
+
I2 Analog
none into the op-amp. R output
D3
MSB I3

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 6. Digital-to-Analog Conversion Methods

Example A certain binary-weighted-input DAC has a binary input of 1101.

If a HIGH = +3.0 V and a LOW = 0 V, what is Vout?
120 k
Rf
20 +3.0 V
60 k 10 k
21 0V
–
30 k
22 +3.0 V Vout
+
15 k
23 +3.0 V

Solution Iout = −(I 0 + I1 + I 2 + I3 )

= −  3.0 V 3.0 V 
3.0V
+0V+ +  = −0.325 mA
 120 k 30 k 15 k 
Vout = Iout Rf = (−0.325 mA)(10 k) = −3.25 V

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 6. Digital-to-Analog Conversion Methods

b) R-2R Ladder:
The R-2R ladder requires only two values of resistors. By calculating a
Thevenin equivalent circuit for each input, you can show that the output is
proportional to the binary weight of inputs that are HIGH.

VS
Each input that is HIGH contributes to the output: Vout = −
where VS = input HIGH level voltage
2n−i
n = number of bits Inputs
i = bit number D D1 D2 D3
0

For accuracy, the resistors R1 R3 R5 R7 Rf = 2R

must be precise ratios, 2R 2R 2R 2R
R2 R4 R6 R8
which is easily done in –
integrated circuits. 2R R R R Vout
+

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 6. Digital-to-Analog Conversion Methods

Example An R-2R ladder has a binary input of 1011. If a HIGH = +5.0 V

and a LOW = 0 V, what is Vout?
D0 D1 D2 D3
+5 v +5 v 0v +5 v

R1 R3 R5 R7 Rf
Calculate the 50K
50K 50K 50K 50K
Thévenin equivalent
R2 R4 R6 R8
–
50K 25K 25K 25K Vout
+

Solution Apply Vout = − Vn−i

S to all inputs that are HIGH, then sum the results.
2
5V 5V
Vout (D0 ) = − 4−0
= −0.3125 V Vout (D1 ) = − 4−1 = −0.625 V
2 2
5V
Vout (D3 ) = − 4−3 = −2.5V Applying superposition, V out = −3.43 V
2
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 7. Resolution and Accuracy of DACs

The R-2R ladder is relatively easy to manufacturer and is available in IC

packages. DACs based on the R-2R network are available in 8, 10, and 12-bit
versions.
The resolution is an important specification, defined as the reciprocal of the
number of steps in the output.

Question What is the resolution of the BCN31 R-2R

ladder network, which has 8-bits?

Answer (28 – 1)-1 = 1/255 = 0.39%

The accuracy is another important specification and is derived from a

comparison of the actual output to the expected output.
For the BCN31, the accuracy is specified as ±½ LSB = 0.2%.

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 8. DACs Errors

Monotonicity

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 8. DACs Errors

Settling Time

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 8. DACs Errors

Gain error

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 8. DACs Errors

Offset Error

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 8. Reconstruction Filter

After converting a digital signal to analog, it is passed through a low-pass

“reconstruction filter” to smooth the stair steps in the output.
The cutoff frequency of the reconstruction filter is often set to the same limit as
the anti-aliasing filter, to block higher harmonics due to the digitizing process.

Reconstruction
Filter

Output of the DAC Final analog output

Low Pass
Filter
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 9. Digital Signal Processing

A digital signal processor (DSP) is optimized for speed and working in real time
(as events happen). It is basically a specialized microprocessor with a reduced
instruction set (RISC).
After filtering and converting the analog signal to digital, the DSP takes over.
It may enhance the signal in some predetermined way (reducing noise or
echoes, improving images, encrypting the signal, etc.).
The signal can then be converted back to analog form if desired.

10110 10110
01101 01101
00011 00011
11100 11100 Enhanced
Analog Anti-aliasing Sample-and- Reconstruction
signal filter hold circuit ADC DSP DAC filter analog
signal

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 9. Digital Signal Processing

Program cache/program memory

Because speed is (32-bit address, 256-bit data)
important in DSP
applications, assembly
language is frequently CPU (DSP coer)

used because in general Program fetch

Control
it executes faster. Instruction dispatch registers

Instruction decode
DMA
EMIF Control
Data pathA Data pathB logic

Register fileA Register fileB

Test

Evaluation
.L1 .S1 .M1 .D1 .D2 .M2 .S2 .L2 Interrupts

Data cache/data memory Additional

(32-bit address, 8-, 16-, 32-. 64-bit data) peripherals

A general block diagram of the TMS320C6000 series DSP

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 Selected Key Terms

Nyquist frequency The highest signal frequency that can be sampled at a specified
sampling frequency; a frequency equal or less than half the
sampling frequency.

Quantization The process whereby a binary code is assigned to each sampled

value during analog-to-digital conversion.

Analog-to-digital A circuit used to convert an analog signal to digital form.

converter (ADC)

DSP Digital signal Processor; a special type of microprocessor that

processes data in real time.

Digital-to-analog A circuit used to convert a digital signal to analog form.

converter (DAC)

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 Quiz

1.If an anti-aliasing filter is not used in digitizing a signal the recovery

process
a. is slowed
b. may include alias signals
c. will have less noise
d. all of the above

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 Quiz

2. An anti-aliasing filter should have

a. fc more than 2 times the Nyquist frequency
b. fc equal to the Nyquist frequency
c. fc more than ½ fsample
d. fc less than ½ fsample

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 Quiz

3. The number of comparators required in a 10-bit flash ADC is

a. 255

b. 511
c. 1023
d. 4095

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 Quiz

4. The block diagram is for a successive-approximation ADC.

The top block is ?
a. an SAR Vout

b. a DAC
?
c. an ADC D0
D1 Parallel
d. a comparator binary
D2 output
–
Input + D3
signal (MSB) (LSB)
D Serial
binary
output
CLK C

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 Quiz

5. The ADC804 integrated circuit signals a completed conversion by

VCC
a. INTR goes LOW
(20)
b. CS goes LOW CS
(1) (5)
ADC0804 INTR
(2) (19)
c. RD goes LOW RD
(3) (18) CLK R (out)
WR
(4) (17) D0
d. CLK R goes HIGH CLK IN
(6) (16)
D1
Analog Vin+ D2
(7) (15) Digital
input Vin– D3
(9) (14) data
REF/2 D4
(13) output
D5
(12)
D6
(11)
D7

(8) (10)

ANLG DGTL
GND GND

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 Quiz

6. A sigma-delta circuit is a form of

a. DSP
b. DAC
c. ADC
d. SAR

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 Quiz

7. The circuit shown is a

a. DSP
8R
b. DAC Rf
+ –
I0
c. ADC 4R If
d. SAR
I1 – Vout
2R
I=0
I2 +
R

I3

AD/DA Converters. School of Electronic Engineering, UPTC Wilson Javier Perez H. - 2018 77
 Quiz

8. For the circuit shown, the input on the far left is for the
a. Analog input
b. Clock
Inputs
c. LSB
d. MSB
R1 R3 R5 R7 Rf = 2R
2R 2R 2R 2R
R2 R4 R6 R8
–
2R R R R Vout
+

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 Quiz

9. A reconstruction filter
a. is a low-pass filter
b. can have the same response as an anti-aliasing filter
c. smoothes the output from a DAC
d. all of the above

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 Quiz

10. A DSP is a specialized microprocessor that

a. has a very large instruction set
b. is designed to be very fast
c. has internal anti-aliasing and reconstruction filters
d. all of the above

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