analogangle By Ron Mancini

Adding hysteresis
to comparators
y last column (“Designing with comparators,”

M
for illustrative purposes. Normally,
the amplitude of the noise on the
EDN, March 29, 2001, pg 56) discussed basic signal determines the hysteresis
voltage. A more normal hysteresis
comparator theory, and this column adds hys- voltage is closer to 22.6 mV, and
when you increase the value of R2
teresis to comparators to eliminate multiple switching on to 2 MV to reduce the hysteresis,
the approximate equation now
the output. Comparators have very high open-loop gain, yields an adequate solution.
Hysteresis prevents multiple
and, without some type of positive The hysteresis voltage is the dif- switching, but there is no free
feedback, they have no noise ference voltage between the equa- lunch, because hysteresis intro-
immunity. A slow or dc input sig- tions, or duces a “dead zone” in which the
nal spends too much time in the (VCC1VCES )R1 comparator cannot sense an input
comparator threshold, where noise ∆V+ = . voltage. The dead zone is the range
immunity is zero, so any noise on R1 + R 2 of voltages within DV+. It is equal
the input signal causes the output
voltage to switch almost randomly. HYSTERESIS IS POSITIVE FEEDBACK THAT PULLS
Hysteresis is positive feedback that
pulls the input signal through the THE INPUT SIGNAL THROUGH THE THRESHOLD
threshold when the output switch-
es, thus preventing multiple
WHEN THE OUTPUT SWITCHES, THUS PREVENTING
switching. MULTIPLE SWITCHING.
In the circuit in Figure 1, RL (the
load resistor) forms a voltage And, when VCESP0 and R2..R1, to the hysteresis voltage, and it
divider with the pullup resistor, R3; you can approximate the hysteresis limits the accuracy of the com-
hence, RL’s value must be much voltage by parator. If the application is unidi-
greater than R3 to keep the output VCC R 1 rectional (the input-voltage direc-
voltage high. R1 and R2 are the hys- ∆V+ = . tion to the trip point is always
teresis components. When VIN R2 from the same direction), the dead
transitions from some value Selecting R1=10 kV, R2=200 kV, zone does not matter, but, in bidi-
greater than V+ toward some value R3=2 kV, RL=200 kV, and a TLC- rectional applications, such as
less than V+, the output voltage 339 comparator yields VOUT= ADCs, the dead zone limits the
switches from VOUT=VCE P0 to 4.95V, VCES=0.2V, and a hysteresis converter’s ultimate accuracy.
VOUT=VCC2ILR3PVCC. The change voltage of DV+=0.226V. This hys- When you want to use a string of
in the output voltage establishes a teresis voltage is unusually large comparators as an ADC (a flash
current through R1, and the volt- converter), the dead zone limits
age drop across R1 increases, caus- VCC=5V
the best accuracy the ADC can
ing V+ to increase. The have. A 9-bit ADC referenced to
increase in V+ pulls the Figure 1 10V full-scale has a least signifi-
threshold voltage above the input R3 cant bit of 19.5 mV. The hysteresis
2k
voltage, preventing multiple VIN _
VOUT voltage is 22.6 mV, and this dead
switching. The following switching V+ zone equates to more than a least
equations assume that R2..R3 +
RL significant bit for a 9-bit ADC, so
,,RL. 200k
the best ADC this comparator cir-
When VIN.VREF, cuit can make has 8-bit accuracy.k
R2
VREFR 2 VCESR1 R1 200k
V+ = + . 10k
R1 + R 2 R1 + R 2
When VIN,VREF, VREF=1.5V Ron Mancini is staff scientist
at Texas Instruments. You can
VREF R 2 VCC R 1
V+ = + . R2 and R1 add hysteresis to the compara- reach him at 1-352-568-1040,
R1 + R 2 R1 + R 2 tor to prevent multiple switching. rmancini@ti.com.
22 edn | May 3, 2001 www.ednmag.com