Digital to Analog

Converters
Conversores de Sinal -2022/2023
Nuno Paulino – DEEC- FCT/UNL
DAC architectures
1. Resistive string DACs
2. Scaled current DACs
• Binary weighted resistor structures
• R-2R ladder structures
3. Current steering DACs
• Binary weighted current sources
• Unit current sources
• Segmented architectures
4. Charge distribution DACs
5. Hybrid structure DACs (between 1 and 4)

Nuno Paulino - DEEC 2

 Resistive string DACs
Vref
b1
b1 b0 o0 o1 o2 o3
R X/Y b0 Digital
0 0 1 0 0 0 o3 decoder
0 1 0 1 0 0
R o2
1 0 0 0 1 0
1 1 0 0 0 1
+ Vout
R
o1
-
2 N   R  Vref
INL MAX i  2 N / 2     R
4  R  2N o0
 R  1 Analog
INL   0 . 5 LSB     N 2
 R  2 multiplexer

•Inherently monotonic
•The number of resistors grows exponentially with the resolution
•Static errors are dependent on the resistive string.
•Maximum conversion frequency determined by the time constant: Rmax.C

Nuno Paulino - DEEC 3

Settling error of the DAC

 
Vref
R1 t
R Vout (t )  Vref   1 e 
R2 R1  R2
R

R
+   R1 R2  C p
Cp Vout
R1 -
R1  code  R
R

R2  (2nbits  code)  R

error 
Vref 
R1
R1  R2
 Vref 
R1
R1  R2  T
 1 e  t
e 
R1
Vref 
R1  R2

Nuno Paulino - DEEC 4

Binary weighted resistor DAC
Isum

Isum RF
-
I3 I2 I1 I0 Vout
b3 b2 b1 b0 +
R3 R2 R1 R0
-Vref

RF=(1/16).Ru R0=1.Ru R1=(1/2).Ru R2=(1/4).Ru R3=(1/8).Ru (Ru: unit resistor)

The resistors (Ri) are obtained by connecting in parallel unit resistors (Ru)

Non-monotonic (can have missing codes)

The resistance values increases exponentially with the resolution
The maximum conversion frequency is dependent of the amplifier.
Nuno Paulino - DEEC 5
The problem with binary weighted
resistors (weights)
Ru1 Ru2 Ru3 Ru4 Ru5 Ru6 Ru7 Ru8 Ru9 Ru10 Ru11 Ru12 Ru13 Ru14 Ru15
0.78 1.06 0.71 0.84 0.86 0.76 1.15 0.89 0.77 0.88 1.28 1.27 1.21 1.22 0.97
Iu1 Iu2 Iu3 Iu4 Iu5 Iu6 Iu7 Iu8 Iu9 Iu10 Iu11 Iu12 Iu13 Iu14 Iu15
1.29 0.95 1.41 1.19 1.17 1.31 0.87 1.12 1.30 1.14 0.78 0.79 0.83 0.82 1.03
I1 I2 I3 I4
1.29 2.36 4.54 7.80

In the transition from code 7 to code 8 a large error can occur:

Code 7 -> 1.29 + 2.36 + 4.54 = 8.19

Code 8 -> 7.80

Error = -1.39 lsbs

Nuno Paulino - DEEC 6

Unit resistor (unit current) DAC
Isum

Digital RF
Isum
b1 b0 o0 o1 o2 decoder
0 0 0 0 0 -
Iu Iu Iu Vout
0 1 1 0 0 o1
b1 o0 o2
1 0 1 1 0 b0 X/Y +
1 1 1 1 1
Ru Ru Ru
-Vref
RF=Ru/16 (Ru: unit resistor)

Monotonic (no missing codes)

The number of resistors increases exponentially with the resolution
Requires a digital decoder (can be difficult to build for large resolutions)
The maximum conversion frequency is dependent of the amplifier.
Nuno Paulino - DEEC 7
Typical INLs and DNLs for 8 bit DACs,
using binary weighted and unit resistors

Absolute error of
the unit resistors

The INL maximum error is similar in both DACs

The DNL is much worse in the case of the binary weighted DAC

Nuno Paulino - DEEC 8

Practical example of application of the
2 DACs

binary weighted resistors DAC Unit resistors DAC

Nuno Paulino - DEEC 9

R-2R ladder DAC
Isum

Isum RF
-
b3 b1
Vout
b2 b0
+
R1 R2 R3 R4
-Vref
R5 R6 R7 R8

RF=16.Ru R1=R2=R3=R4=R8=2.Ru R5=R6=R7=Ru (Ru: unit resistor)

Limited dispersion of component values.

Number of resistors increases linearly with the resolution
The maximum conversion frequency is dependent on the amplifier.
Nuno Paulino - DEEC 10
 R-2R calculation

2R 2R 2R 2R Req1  Req 3  Req 5  R

R R R 2R Req 2  Req 4  Req 6  2 R
Vref
Req6 R eq5 R eq4 Req3 Req2 Req1

R 1
V1   Vref   Vref
RR 2
I1 2R I2 2R I3 2R I4 2R R 1 1
V2   V1    Vref
Vref R R R 2R RR 2 2
V1 V2 V3 R 1 1 1
I5 I6 I7 I8 V3   V2     Vref
RR 2 2 2

Vref V1 1 Vref V2 1 1 Vref V3 1 1 1 Vref

I1  I2    I3     I4     
2 R 2 R 2 2 R 2 R 2 2 2 R 2 R 2 2 2 2 R

Nuno Paulino - DEEC 11

Linearity errors of the R-2R DAC

Absolute error of
the unit resistors

Ru 1
 nbits  2
Ru 2

Nuno Paulino - DEEC 12

Voltage mode R-2R DAC
2R R R R
Vout

2R 2R 2R 2R

b0 b0 b1 b1 b2 b2 b3 b3
Vref

The reference voltage is positive (single power supply)

Requires an amplifier with a large input impedance (buffer)
The circuit is sensitive to parasitic capacitances (lower speed)
The switches voltage changes with the input digital code.

Nuno Paulino - DEEC 13

Current source-based DACs

 Eliminates the need of the operational amplifier

 The output current is the sum of 2n-1 currents, and it is

converted into a voltage trough a resistance (Vo=Io.Ro)

 The maximum current value depends on the desired

conversion speed of the DAC ( =Ro.Co)

 The circuit area increases exponentially with the

resolution of the DAC.
 Ex. : For 8-bit resolution 255 transistors are necessary.

Nuno Paulino - DEEC 14

Binary weighted current source DAC

Io=8Iub3+4Iub2+2Iub1+Iub0

b3 b2 b1 b0
The output current is a
function of the reference
8 Iu 4 Iu 2 Iu 1 Iu current and the digital
code

Each current source of weight Iu is implemented by one transistor.

For 8-bit resolution 255 transistors are necessary.
Nuno Paulino - DEEC 15
Segmented architecture
16+1 T
1/16
Io=8Irb7+4Irb6+2Irb5+Irb4
Io=8Irb3+4Irb2+2Irb1+Irb0

b3 b2 b1 b0 b7 b6 b5 b4 1T

8 Ir 4 Ir 2 Ir 1 Ir 8 Ir 4 Ir 2 Ir 1 Ir

1T 8T
8T

15+15+16+1+1 = 48 transistors

Nuno Paulino - DEEC 16

Possible CMOS DAC implementation
VDD
R2
VDD
VDAC
R1
b0 b1 b2 b3
IR
W W Cp0 2W Cp1 4W Cp2 8W Cp3
VR L L L L L

VG

Nuno Paulino - DEEC 17

 Problem with the switching
VDD VDD VDD
VDACN VDACP
R2 R2 R2

VDAC CLoad CLoad

b3 t0 t0
CLoad
Vx
t0 Vx t0
8W Cp3
L Cp3
8W
L t0
t0
The switch is replaced by a differential
When b3 is 0 Cp3 discharges to 0V. pair (current steering). Vx voltage
When b3 changes to 1 Cp3 must can now remain constant.
charge from 0V resulting in a glitch The differential pair transistors also act
and extra delay at the output as cascode devices increasing the
voltage. output impedance.
Nuno Paulino - DEEC 18
Current steering (switching)
In order to have a constant current in the current source it is necessary to steer
the current to another branch instead of simply using a series switch. This
arraignment corresponds to using a differential pair as a switch.

Nuno Paulino - DEEC 19

Mismatch errors (MOS design)

Due to the random variations of VT and b=mCox

There is a difference between the drain currents
Vdd of two equal sized MOS transistors:
Ir Vo I  I u  I 0
Io The variance of the relative error between the
M1
two currents is given by:
M2
VGS
 2 ( I ) 1  2 4. AV2T 
  Ab  
M1=M2
I r2 W. L 
 VGS  VT  
2

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 24, NO. 5, OCTOBER 1989,

Matching Properties of MOS Transistors, MARCEL J. M. PELGROM, C. J. DUINMAIJER,
ANDANTON P. G. WELBERS

The design of the DAC should guaranty that the error is smaller
than the maximum error allowed by the DAC resolution

Nuno Paulino - DEEC 20

Examples of matching parameters
P. R. Kinget, "Device mismatch and tradeoffs in the design of analog circuits," in IEEE Journal of Solid-State
Circuits, vol. 40, no. 6, pp. 1212-1224, June 2005,

Nuno Paulino - DEEC 21

 Current source errors
NIR+I1+...+IN The error in the current of bit N (IbN) has a
variance that is the sum of the variances of the
IR+I 1 IR+I 2 IR+I 3 IR+  I N
error current of each unit transistor:
VG

The largest error occurs for the code transition from 01…11 (N) to 10…00 (N-1):

In order to not have missing codes this means:

To guaranty that 99.97% of the cases :

Nuno Paulino - DEEC 22

 Sizing of the MOS current sources
0.02
0.018
3 value of the relative
0.015
current error in a MOS
3 S.Mi 10 Li transistor for different channel
0.01
3 S.Mi 100 Li lengths (L) and channel
3
510
widths (W). Drain current is
constant
3
3.77710
0
5 10 15 20
5 Li 20

2.5
2.204

(Vgs-Vt) voltage in a MOS transistor 2

for different channel lengths (L) and V.GT  10  Li  1.5

channel widths (W). Drain current is V.GT  100  Li

1

constant 0.5

0.349
0
5 10 15 20
5 Li 20

Nuno Paulino - DEEC 23

Unit current source DAC

 Using binary weighted current sources results in a non-monotonic

characteristic, because for certain code transitions N unit current
sources are disconnected and N+1 unit current sources are
connected.

 In order to solve this problem, it is necessary to connect or

disconnect just one-unit current source for every code transition.

 The resulting circuit is almost same circuit as a binary weighted

DAC, it is only necessary to change the switching scheme and use a
digital decoder. The digital decoder is distributed in order to increase
the speed of the DAC.

Nuno Paulino - DEEC 24

Example of current source based DAC
IEEEJOURNAL OF SOLID-STATECIRCUITS,VOL. SC-21,NO. 6,DECEM8ER 1986, An 80-MHz
8-bit CMOS D/A Converter; TAKAHIRO MIKI, YASUYUKI NAKAMURA, MASAO NAKAYA,
SOTOJU ASAI, YOICHI AKASAKA, ANDYASUTAKA HORIBA

Distributed decoder

Nuno Paulino - DEEC 25

Example #2: DAC0800: Binary weighted currents
generated trough R-2R resistive ladder

Nuno Paulino - DEEC 26

Charge redistribution DAC
F1
-
4C 2C C C Vout
F1 F2 F1 F2 F1 F2 F1 F2 +
b2 b2 b1 b1 b0 b0
Vref

The component dispersion increases exponentially with the resolution.

The reference voltage value can change with the input code, due to
memory effects in the non-ideal reference voltage.

Nuno Paulino - DEEC 27

Charge redistribution DAC calculation
Q =-4.C.V .b -2.C.V .b -C.V .b -C.0
1 ref 2 ref 1 ref 0

- During phase 1 the capacitors are

4C 2C C C Vout charged with the reference
0V
+ voltage multiplied by the digital
code
b2 b2 b1 b1 b0 b0
Vref

Q2=-4.C.Vout-2.C.Vout-C.Vout -C.Vout
- During phase 2 the capacitors are
4C 2C C C Vout
0V
redistribute the charge, causing Vout
+ to be set to the correct voltage

4  b2  2  b1  b0 4  b2  2  b1  b0
Q1  Q2  Vout  Vref   Vref 
4  2 11 2nbits
Hybrid structure DAC

Vref
b0
R X/Y b1 F1
o3 -
4C 2C C C Vout
R o2 F1 F2 F1 F2 F1 F2 F1 F2 +

R b4 b4 b3 b3 b2 b2
o1 Vref

R
o0

The component dispersion increases is reduced due to the

segmentation.
There is added risk for memory effects.
Nuno Paulino - DEEC 29