DEPARTAMENTO DE ENGENHARIA ELECTROTÉCNICA

3º TESTE DE ELECTRÓNICA III (2012/2013)

3 DE JUNHO DE 2013 – SALA 1.17 EDIFÍCIO VII
17:00/18:15H

PROBLEM 1:

Consider a second order PLL with the block diagram depicted in Figure 1. The frequency of the
input frequency is 100 Mrad.s-1. Consider that the output frequency of the VCO as a function of the
( )
 141 + 1 − e −2⋅( vc − 4V ) × 19 if vc > 4 V

control voltage is given by: ωOUT ( vc ) = 1 + 40 × ( vc − 0.5 ) if 0.5V < vc ≤ 4V [Mrad/s]
 1 if vc ≤ 0.5V


ωi I (t) v (t) v (t)

d c
out
PD F(s) VCO
v (t)
in ωout
Figura 1: Block diagram of the PLL

a) Determine the linear model of the VCO for the input frequency value (represent in a graph the
VCO characteristic).
b) Draw the circuit of a 3-state phase-frequency detector with a charge pump current of 10 µA and
determine its linear model.
c) Considering that the loop filter (F(s)) has a pole and a zero, suggest a circuit that is capable of
implementing this transfer function, justify your answer by calculating the circuit transfer
function.
d) Explain why the static phase error of the PLL with this phase detector is 0.
e) Calculate the closed loop transfer function of the PLL and calculate the values of the
components of the loop filter in order to obtain a closed loop bandwidth of 0.1 Mrad/s and a
closed loop system critically damped.
f) Determine the lock-in range of the PLL assuming that the input signal frequency changes slowly
and that the maximum output voltage of the charge pump circuit is 4.5V.
g) If the input signal frequency of the PLL changes from 100 Mrad/s to 150 Mrad/s what is the new
value for the closed loop bandwidth of the PLL?
h) Explain how you would modify the PLL block diagram of figure 1 in order for the PLL to
produce an output frequency equal to 100 Mrad/s from an input frequency equal to 10 Mrad/s.
Calculate any new parameter value of the new block diagram.