Departamento de Engenharia Electrotécnica

1º EXAME DE ELECTRÓNICA III / REPESCAGEM 3º TESTE

19 DE JUNHO DE 2015 – SALA 1.16 EDIFÍCIO VII
17:00/20:00H

Problem 1

Vref b2 Φ Vref b1 Φ Comp0

C C - 1 vout2 C C - 2 vout
2 2 vin0
-Vref Φ2 Φ1 Φ1 Φ2 + -Vref Φ1 Φ2 Φ2 Φ1 +
b2 b1
2 vx2 2 vx1

+
-
vin2 + vin1 +
Comp2 Comp1
- - b0
b2 b1

Consider the pipeline ADC with 3 stages depicted above; assume that all the capacitors have the same value C and that the
 Vref Vref 
amplifiers are ideal. The input voltage range of the circuit is − ,  . This ADC does not have digital correction (Vref=1
 2 2 
V).
a) What is the main advantage and main disadvantage of this type of converter when compared to a flash type
converter?
b) What is the overall resolution of the ADC
c) What is the maximum SNR of this ADC.
d) How many stages would be required in order to have a maximum SNR of at least 60 dB ?
e) Calculate the expression of vout2 as function of vin and vx2
f) Calculate the expression of vout2 as function of vin, Vref and b2.
g) Calculate the 3-bit digital output code of the ADC (and all the internal voltages values during phase Φ2) when the
input voltage (vin2) is equal to 0.05V.
h) Considering that there is an offset voltage of 70mV in the comparator of the first stage, repeat the previous
question.

Problem 2
Consider a 4th order MASH sigma-delta modulator with an architecture composed by a cascade of one second order sigma
delta modulator with two first order sigma delta modulator with one bit output (2+1+1) . This circuit has a reference voltage
equal to 0.9 V. The output of the modulator is applied to digital decimation filter with an output resolution of n bits. This filter
has a bandwidth of 8000 kHz. .

a) Draw the block diagram of the modulator with all of its constituting blocks.
b) Show that the noise transfer function of the modulator is given by (1-z-1)4.Justify all the steps of your answer.
c) Calculate the total noise power at the output of the decimation filter (assuming an ideal filter transfer function).
Justify all the steps of your answer.
d) Assuming that the modulator starts to saturate for signals 3 dB below the reference value calculate the maximum
amplitude of the input signal in Vrms.
e) Assuming that the modulator has no thermal noise calculate the sampling frequency value necessary for to obtain
a SNR value at the output of the system equal to 74 dB for a sine wave signal inside the bandwidth of the system.
(Ignore the quantization noise of the decimator filter in this calculation).
f) Assuming that the thermal noise power is 2 times larger than the quantization noise o the modulator, calculate the
new value of the SNR at the output of the system.
g) Calculate the minimum required number of bits in order to obtain a quantization noise power 8 times smaller than
the total noise from the previous question
h) Assuming that a sine wave signal with 1mV is applied to this A/D channel calculate the output SNR.
Problem 3 (Exam: a) to h), test a) to l) )

Consider a second order PLL where the frequency of the input signal is 50 Mrad.s-1. Consider that the output frequency of the
K
VCO is given by: ωout = , where K= 100 Mrad/s and Vc is the control voltage, that can change between 0 and 1 V, if
9 ⋅VC + 1
the control voltage is larger than these limits, the output frequency is equal to the value at the limit. This PLL uses a XOR gate
with a power supply of VDD=2V and that VSS=0 V as the phase detector circuit.

d 1 1
a) Determine the linear model of the VCO for the input frequency value. (note  =− 2 )
dx  x  x
b) Analyze the XOR gate as a phase detector and determine the linear model of the phase detector, justify your answer.
c) Considering that the loop filter (F(s)) has a pole and a zero and F(0)=1, suggest a circuit that is capable o implementing
this transfer function, justify your answer by calculating the circuit transfer function.
d) Draw the linear model of the PLL.
e) Determine the static phase error of the PLL for the input signal frequency, (assume F(0)=1).
f) Design this loop filter in order to obtain a closed loop bandwidth of 0.5 Mrad/s, (the closed loop system must be stable)
g) Determine the lock in range of the PLL assuming that the input signal frequency changes slowly
h) If the frequency of the input signal is changed to 5 Mrad/s, how can the PLL circuit be changed in order for the output
frequency to remain equal to 50 Mrad/s. Justify your answer by presenting the new block diagram of the PLL.
i) Draw the circuit of a phase frequency detector and calculate its linear model, justify
j) Considering that the phase-frequency detector controls an ideal charge pump circuit, draw the new block diagram of the
PLL, including the new loop filter circuit.
k) Calculate the transfer function of the new PLL circuit.
l) Assuming that the charge pump current is equal to 100 µA determine the values of the loop filter components in order for
the PLL to have a closed loop bandwidth equal to 0.5 Mrad/s (the closed loop system must be stable).