DEPARTAMENTO DE ENGENHARIA

ELECTROTÉCNICA
2º TESTE DE ELECTRÓNICA III
23 DE MAIO DE 2018 – SALA 4.8 ED. VIII
15H30-16H45
VERSION A

PROBLEM 1: A/D CONVERTERS

Vref /2
-Vref /2

b2.F21 F11 b2.F21 b1.F20 F10 b1.F20

FS 2C C C
vx
vin + 3
SAR Logic dout
-

Fig. 1

Consider the SAR ADC with 3 bits of resolution whose block diagram is depicted above. The input voltage
 Vref Vref 
range of the ADC is  2 , 2  . (Vref=1 V).
 
(Carefully justify all the answers)

a) Calculate the value of the lsb voltage of this ADC

b) Draw the ideal transfer function of this ADC
c) What should be the resolution of the ADC, if a SNR value of 30dB is desired for an input signal
with amplitude of 62mV?
d) What is the number of steps required to obtain the correct output code? (do not consider the
sampling step in your answer)
e) Calculate the expression of the charge in the capacitors (vx node) at the end of the sampling
phase (Fs=F11=F10=1) as a function of vin
f) Calculate the expression of the charge in the capacitors (vx node) at the end of the first
conversion step (F21=F10=1) as a function of Vref, vin and b2.
g) Using charge conservation, calculate the expression of vx at the end of the first conversion step,
as a function of Vref, vin and b2
h) Calculate the expression of the charge in the capacitors (vx node) at the end of the second
conversion step (F21=F20=1) as a function of Vref, vin, b1 and b2.
i) Using charge conservation calculate the expression of vx at the end of the second conversion
step, as a function of Vref, vin, b1 and b2
j) Considering that vin=0.2V calculate the values of vx and dout at the end of each of the 3
conversion steps.
k) What is the effect of an offset voltage in the comparator in the transfer function of this ADC,
justify your answer.
 DEPARTAMENTO DE ENGENHARIA
ELECTROTÉCNICA
2º TESTE DE ELECTRÓNICA III
23 DE MAIO DE 2018 – SALA 4.8 ED. VIII
15H30-16H45
VERSION B

PROBLEM 1: A/D CONVERTERS

Vref /2
-Vref /2

b2.F21 F11 b2.F21 b1.F20 F10 b1.F20

FS 2C C C
vx
vin + 3
SAR Logic dout
-

Fig. 2

Consider the SAR ADC with 3 bits of resolution whose block diagram is depicted above. The input voltage
 Vref Vref 
range of the ADC is  2 , 2  . (Vref=2 V).
 
(Carefully justify all the answers)

a) Calculate the value of the lsb voltage of this ADC

b) Draw the ideal transfer function of this ADC
c) What should be the resolution of the ADC, if a SNR value of 24dB is desired for an input signal
with amplitude of 62mV?
d) What is the number of steps required to obtain the correct output code? (do not consider the
sampling step in your answer)
e) Calculate the expression of the charge in the capacitors (vx node) at the end of the sampling
phase (Fs=F11=F10=1) as a function of vin
f) Calculate the expression of the charge in the capacitors (vx node) at the end of the first
conversion step (F21=F10=1) as a function of Vref, vin and b2.
g) Using charge conservation, calculate the expression of vx at the end of the first conversion step,
as a function of Vref, vin and b2
h) Calculate the expression of the charge in the capacitors (vx node) at the end of the second
conversion step (F21=F20=1) as a function of Vref, vin, b1 and b2.
i) Using charge conservation calculate the expression of vx at the end of the second conversion
step, as a function of Vref, vin, b1 and b2
j) Considering that vin=0.2V calculate the values of vx and dout at the end of each of the 3
conversion steps.
k) What is the effect of an offset voltage in the comparator in the transfer function of this ADC,
justify your answer.