Spyder 13.3

1 2 3 4 5 6 7 8
fix
vina
Spyder 13.3" UMA BLOCK DIAGRAM +VCHGR
PAGE 32
+3.3V_ALW/+5V_ALW
A A
PAGE 33
CPU FAN & THERMAL
DDR3-Memory Onboard DDR3 1333 MHZ SMSC1422 +1.5V_SUS/+0.75V_DDR_VTT
PG 28 PAGE 34
H=4.0mm PAGE 15 Sandy Bridge(ULV) 17W
+VCCSA_CORE
BGA 1023 DC PAGE 36
+1.05V_PCH/+1.8V_RUN
DDR3-Memory Onboard DDR3 1333 MHZ 2C GT2
PAGE 35
H=4.0mm
31 mm X 24 mm
PAGE 16 PAGE 3~7 +VCC_CORE/+VCC_GFX_CORE
PAGE 37
FDI LINK DMI LINK

2.7GT /s 5GT /s
SINGLE CHANNEL LVDS LCD CONN

SATA 6G PAGE 19
B B
SSD mSATA -HDD
SATA GEN II PAGE 27 DISPLAY PORT C Mini DP CONN
PAGE 18
Audio Board Mobile Intel Camera
USB2.0 Port / USB Powershare PAGE 19
PAGE 03 SLG55584 x1
Series 6 Chipset
USB2.0
USB2.0
PCH
WLAN/BT 3.0
Speaker 1W Audio Codec IHDA QS67 i6230
ALC275 PAGE 21
PAGE 29
PAGE 04 Couger Point
PCI-E
C
FCBGA 1017 C
AUDIO
Speaker 1W HP+MIC Combo Jack x1
HEADSET
SWITCH
22 mm X 22 mm
-TS3A225E PAGE 04 PAGE 04 USB3.0 Controller
PAGE 29
PAGE 25
Keyboard Conn. LPC

PAGE 24
PAGE 8~14
KBC USB 3.0/2.0 Combo Ports x1
Touch Pad PAGE 20
PAGE 24
ITE 8519 SPI
TPM
25MHz 32.768KHz
SPI ROM
PAGE 23
PAGE 22 32Mbit
PAGE 25
SPI ROM
D PWM FAN D
4Mbit
PAGE 28 PAGE 25
Quanta Computer Inc.

PROJECT : D13
Size Document Number Rev
1A
BLOCK DIAGRAM
1 2 3 http://vinafix.vn
4 5 6
Date: Thursday, October 13, 2011
7
Sheet 1
8
of 41
1 2 3 4 5 6 7 8
fix
vina power SLP_S3# SLP_S4# SLP_S5# ALW_ON +3.3V_ALW +5V_ALW SUS_ON +3.3V_SUS +5V_SUS RUN_ON +3.3V_RUN +5V_RUN AOAC flag
USB2.0
Power share
USB_BAK_EN#
State
S0 H H H H H H H H H H H H L L
A A
S3 L H H H H H H H H L L L L L
S4/S5 AC L L L H H H L L L L L L L L
S4/S5 L L L L L L L L L L L L L L
DC Only
AC/DC L L L L L L L L L L L L L L
No Exist
AOAC(S4) L L L H H H H H H L L L H H
B B
C C
D D

PROJECT : D13
1A
Power Rails
4 5 6
7
Sheet 2
8
of 41
5 4 3 2 1
fix
ina
DP & PEG Compensation
v Sandy Bridge Processor (DMI,PEG,FDI) +1.05V_VCCIO
CPU is i7 in schematic
U25A
G3 PEG_COMP PEG_ICOMPO 12mil
PEG_ICOMPI
PEG_ICOMPO G1
D [8] DMI_TXN0 M2 G4 PEG_ICOMPI, PEG_RCOMPO 4mil, D
DMI_RX#[0] PEG_RCOMPO R189 24.9/F_4 EDP_COMP
[8] DMI_TXN1 P6 DMI_RX#[1]
[8] DMI_TXN2 P1 DMI_RX#[2]
[8] DMI_TXN3 P10 DMI_RX#[3] PEG_RX#[0] H22 eDP_COMPIO and ICOMPO signals should
PEG_RX#[1] J21 be shorted near balls and routed with
[8] DMI_TXP0 N3 B22
P7
DMI_RX[0] PEG_RX#[2]
D21
typical impedance <25 mohms
[8] DMI_TXP1 DMI_RX[1] PEG_RX#[3]
DMI
[8] DMI_TXP2 P3 DMI_RX[2] PEG_RX#[4] A19
[8] DMI_TXP3 P11 DMI_RX[3] PEG_RX#[5] D17
PEG_RX#[6] B14
K1 D13 +1.05V_VCCIO
[8] DMI_RXN0 DMI_TX#[0] PEG_RX#[7]
[8] DMI_RXN1 M8 DMI_TX#[1] PEG_RX#[8] A11
[8] DMI_RXN2 N4 DMI_TX#[2] PEG_RX#[9] B10
[8] DMI_RXN3 R2 DMI_TX#[3] PEG_RX#[10] G8
PEG_RX#[11] A8
[8] DMI_RXP0 K3 DMI_TX[0] PEG_RX#[12] B6
[8] DMI_RXP1 M7 DMI_TX[1] PEG_RX#[13] H8
[8] DMI_RXP2 P4 DMI_TX[2] PEG_RX#[14] E5
T3 K7 R184 24.9/F_4 PEG_COMP
[8] DMI_RXP3 DMI_TX[3] PEG_RX#[15]
PEG_RX[0] K22 PEG_ICOMPI and RCOMPO signals should

PEG_RX[1] K19 be routed within 500 mils
C21
U7
PEG_RX[2]
D19
typical impedance = 43 mohms
[8] FDI_TXN0 FDI0_TX#[0] PEG_RX[3]
[8] FDI_TXN1 W11 FDI0_TX#[1] PEG_RX[4] C19
W1 D16 PEG_ICOMPO signals should
PCI EXPRESS -- GRAPHICS

[8] FDI_TXN2 FDI0_TX#[2] PEG_RX[5]
[8] FDI_TXN3 AA6 FDI0_TX#[3] PEG_RX[6] C13 be routed within 500 mils
[8] FDI_TXN4 W6 D12
V4
FDI1_TX#[0] PEG_RX[7]
C11
typical impedance = 14.5 mohms
C
[8] FDI_TXN5 FDI1_TX#[1] PEG_RX[8] C
[8] FDI_TXN6 Y2 FDI1_TX#[2] PEG_RX[9] C9
Intel(R) FDI
[8] FDI_TXN7 AC9 FDI1_TX#[3] PEG_RX[10] F8
PEG_RX[11] C8
PEG_RX[12] C5
[8] FDI_TXP0 U6 FDI0_TX[0] PEG_RX[13] H6
[8] FDI_TXP1 W10 FDI0_TX[1] PEG_RX[14] F6
[8] FDI_TXP2 W3 FDI0_TX[2] PEG_RX[15] K6
[8] FDI_TXP3 AA7 FDI0_TX[3]
[8] FDI_TXP4 W7 FDI1_TX[0] PEG_TX#[0] G22
[8] FDI_TXP5 T4 FDI1_TX[1] PEG_TX#[1] C23
[8] FDI_TXP6 AA3 FDI1_TX[2] PEG_TX#[2] D23
[8] FDI_TXP7 AC8 FDI1_TX[3] PEG_TX#[3] F21
PEG_TX#[4] H19
[8] FDI_FSYNC0 AA11 FDI0_FSYNC PEG_TX#[5] C17
[8] FDI_FSYNC1 AC12 FDI1_FSYNC PEG_TX#[6] K15
PEG_TX#[7] F17
[8] FDI_INT U11 FDI_INT PEG_TX#[8] F14
PEG_TX#[9] A15
[8] FDI_LSYNC0 AA10 FDI0_LSYNC PEG_TX#[10] J14
[8] FDI_LSYNC1 AG8 FDI1_LSYNC PEG_TX#[11] H13
PEG_TX#[12] M10
PEG_TX#[13] F10
PEG_TX#[14] D9
PEG_TX#[15] J4
eDP_ICOMPO 12mil EDP_COMP
AF3 eDP_COMPIO
AD2 eDP_ICOMPO PEG_TX[0] F22
eDP_COMPIO 4mil AG11 A23
eDP_HPD PEG_TX[1]
PEG_TX[2] D24
PEG_TX[3] E21
B B
AG4 eDP_AUX# PEG_TX[4] G19
AF4 eDP_AUX PEG_TX[5] B18
PEG_TX[6] K17
DP
PEG_TX[7] G17
AC3 eDP_TX#[0] PEG_TX[8] E14
AC4 eDP_TX#[1] PEG_TX[9] C15
AE11 eDP_TX#[2] PEG_TX[10] K13
AE7 eDP_TX#[3] PEG_TX[11] G13
PEG_TX[12] K10
AC1 eDP_TX[0] PEG_TX[13] G10
AA4 eDP_TX[1] PEG_TX[14] D8
AE10 eDP_TX[2] PEG_TX[15] K4
AE6 eDP_TX[3]
IC,SNB_2CBGA,1P0
A A

PROJECT : D13
1A
Sandy Bridge 1/5
5 4 http://vinafix.vn 3 2
Date: Thursday, October 13, 2011 Sheet
1
3 of 41
5 4 3 2 1
f ix
v ina
Sandy Bridge Processor (CLK,MISC,JTAG)
U25B
T81
D T82 D
BCLK J3 CLK_CPU_BCLKP [12]
BCLK# H2 CLK_CPU_BCLKN [12]
CLOCKS
MISC
F49 PROC_SELECT#
AG3 CLK_DP_P_R R188 1K_4
SNB can be floating DPLL_REF_CLK
AG1 CLK_DP_N_R R187 1K_4 +1.05V_VCCIO
DPLL_REF_CLK#
C57 PROC_DETECT#
BCLK_ITP N59
BCLK_ITP# N58
TP_CATERR# C49
T77 CATERR#
THERMAL
R166 43_4 PECI_EC_R A48 AT30 CPU_DRAMRST#
[22] PECI_EC PECI SM_DRAMRST#
BF44 SM_RCOMP_0 R172 140/F_4 +1.05V_VCCIO

R169 56_4 H_PROCHOT# SM_RCOMP[0] SM_RCOMP_1 R174 25.5/F_4
[22,32,37] IMVP7_PROCHOT# C45 BE43
DDR3
MISC
PROCHOT# SM_RCOMP[1] SM_RCOMP_2 R177 200/F_4
SM_RCOMP[2] BG43
IMVP7_PROCHOT# R168 62_4

[13] PM_THRMTRIP# D45 THERMTRIP#
PRDY# N53 T57

N55 XDP_PREQ#
C PREQ# T61 C
L56 XDP_TCLK
TCK T60
L55 XDP_TMS
TMS T56
PWR MANAGEMENT
J58 XDP_TRST#
TRST# T63
JTAG & BPM

C48 M60 XDP_TDI
[8] H_PM_SYNC PM_SYNC TDI T65
L59 XDP_TDO
TDO T64
[13] H_PW RGOOD B46 UNCOREPWRGOOD

DBR# K58 XDP_DBRST# [8]
R167 10K_4
SM_DRAMPW ROK BE45 G58 Boot S3 S3 RSM

T79 SM_DRAMPWROK BPM#[0] T62
BPM#[1] E55 T58
BPM#[2] E59 T67
BPM#[3] G55 T59
BPM#[4] G59 T68
R170 1.5K/F_4 CPU_PLTRST# D44 H60 +1.5V_CPU
[11,20,21,22,23] PLTRST# RESET# BPM#[5] T69
BPM#[6] J59 T70
BPM#[7] J61 T66
DRAM_PWRGD
R171
750/F_4 100 ns after +1.5V_CPU
SYS_PWROK reaches 80%
IC,SNB_2CBGA,1P0 SM_DRAMPWROK
B B
Pin1 Pin2 Pin4

+3.3V_SUS
L L L +1.5V_SUS
L H L
+1.5V_CPU
H L L
R123
C290 H H H Please close System RAM 1K_4
R160 0.1U/16V_4 PMF780SN
200_4
R165 R122 1K_4 DDR3_DRAMRST#_R 3 1 CPU_DRAMRST#
[15,16] DDR3_DRAMRST#
5
U23 200/F_4
2 Q24
[8] PM_DRAM_PW RGD
R163 0_4 4 SM_DRAMPW ROK_R R164 130/F_4 SM_DRAMPW ROK
2
[8] SYS_PW ROK 1 2 1 [12] DDR_HVREF_RST_PCH
[8,22] EC_PW ROK 1 2 74AHC1G09GW R124

3
+3.3V_SUS R81 1K_4 C73 4.99K/F_4

R162 *0_4_NC 0.047U/10V_4
A A

PROJECT : D13
1A
Sandy Bridge 2/5
1
4 of 41
5 4 3 2 1
f ix
vina Sandy Bridge Processor (DDR3)
U25C U25D
[16] M_B_DQ[63..0]
[15] M_A_DQ[63..0]
M_A_DQ0 AG6 M_B_DQ0 AL4
M_A_DQ1 SA_DQ[0] M_B_DQ1 SB_DQ[0]
AJ6 SA_DQ[1] SA_CLK[0] AU36 M_A_CLKP0 [15,17] AL1 SB_DQ[1] SB_CLK[0] BA34 M_B_CLKP0 [16,17]
M_A_DQ2 AP11 AV36 M_B_DQ2 AN3 AY34
SA_DQ[2] SA_CLK#[0] M_A_CLKN0 [15,17] SB_DQ[2] SB_CLK#[0] M_B_CLKN0 [16,17]
D M_A_DQ3 AL6 AY26 M_B_DQ3 AR4 AR22 D
SA_DQ[3] SA_CKE[0] M_A_CKE0 [15,17] SB_DQ[3] SB_CKE[0] M_B_CKE0 [16,17]
M_A_DQ4 AJ10 M_B_DQ4 AK4
AJ8 SA_DQ[5] AK3 SB_DQ[5]
M_A_DQ6 AL8 M_B_DQ6 AN4
AL7 SA_DQ[7] AR1 SB_DQ[7]
M_A_DQ8 AR11 M_B_DQ8 AU4
AP6 SA_DQ[9] SA_CLK[1] AT40 T48 AT2 SB_DQ[9] SB_CLK[1] BA36 T46
M_A_DQ10 AU6 AU40 T49 M_B_DQ10 AV4 BB36 T47
M_A_DQ11 SA_DQ[10] SA_CLK#[1] M_B_DQ11 SB_DQ[10] SB_CLK#[1]
AV9 SA_DQ[11] SA_CKE[1] BB26 T45 BA4 SB_DQ[11] SB_CKE[1] BF27 T80
M_A_DQ12 AR6 M_B_DQ12 AU3
AP8 SA_DQ[13] AR3 SB_DQ[13]
M_A_DQ14 AT13 M_B_DQ14 AY2
AU13 SA_DQ[15] BA3 SB_DQ[15]
M_A_DQ16 BC7 M_B_DQ16 BE9
BB7 SA_DQ[17] SA_CS#[0] BB40 M_A_CS#0 [15,17] BD9 SB_DQ[17] SB_CS#[0] BE41 M_B_CS#0 [16,17]
M_A_DQ18 BA13 BC41 T51 M_B_DQ18 BD13 BE47 T75
M_A_DQ19 SA_DQ[18] SA_CS#[1] M_B_DQ19 SB_DQ[18] SB_CS#[1]
BB11 SA_DQ[19] BF12 SB_DQ[19]
M_A_DQ20 BA7 M_B_DQ20 BF8
BA9 SA_DQ[21] BD10 SB_DQ[21]
M_A_DQ22 BB9 M_B_DQ22 BD14
AY13 SA_DQ[23] BE13 SB_DQ[23]
M_A_DQ24 AV14 AY40 M_B_DQ24 BF16 AT43
SA_DQ[24] SA_ODT[0] M_A_ODT0 [15,17] SB_DQ[24] SB_ODT[0] M_B_ODT0 [16,17]
M_A_DQ25 AR14 BA41 T50 M_B_DQ25 BE17 BG47 T78
M_A_DQ26 SA_DQ[25] SA_ODT[1] M_B_DQ26 SB_DQ[25] SB_ODT[1]
AY17 SA_DQ[26] BE18 SB_DQ[26]
M_A_DQ27 AR19 M_B_DQ27 BE21
BA14 SA_DQ[28] BE14 SB_DQ[28]
M_A_DQ29 AU14 M_B_DQ29 BG14
BB14 SA_DQ[30] M_A_DQSN[7..0] [15] BG18 SB_DQ[30] M_B_DQSN[7..0] [16]
M_A_DQ31 BB17 AL11 M_A_DQSN0 M_B_DQ31 BF19 AL3 M_B_DQSN0
C M_A_DQ32 SA_DQ[31] SA_DQS#[0] M_A_DQSN1 M_B_DQ32 SB_DQ[31] SB_DQS#[0] M_B_DQSN1 C
BA45 SA_DQ[32] SA_DQS#[1] AR8 BD50 SB_DQ[32] SB_DQS#[1] AV3
M_A_DQ33 AR43 AV11 M_A_DQSN2 M_B_DQ33 BF48 BG11 M_B_DQSN2
M_A_DQ34 SA_DQ[33] SA_DQS#[2] M_A_DQSN3 M_B_DQ34 SB_DQ[33] SB_DQS#[2] M_B_DQSN3
AW48 SA_DQ[34] SA_DQS#[3] AT17 BD53 SB_DQ[34] SB_DQS#[3] BD17
M_A_DQ35 M_A_DQSN4 M_B_DQ35 M_B_DQSN4
DDR SYSTEM MEMORY A
BC48 AV45 BF52 BG51
DDR SYSTEM MEMORY B

BC45 SA_DQ[36] SA_DQS#[5] AY51 BD49 SB_DQ[36] SB_DQS#[5] BA59
M_A_DQ37 AR45 AT55 M_A_DQSN6 M_B_DQ37 BE49 AT60 M_B_DQSN6
AT48 SA_DQ[38] SA_DQS#[7] AK55 BD54 SB_DQ[38] SB_DQS#[7] AK59
M_A_DQ39 AY48 M_B_DQ39 BE53
BA49 SA_DQ[40] BF56 SB_DQ[40]
M_A_DQ41 AV49 M_B_DQ41 BE57
BB51 SA_DQ[42] BC59 SB_DQ[42]
M_A_DQ43 AY53 M_B_DQ43 AY60
BB49 SA_DQ[44] M_A_DQSP[7..0] [15] BE54 SB_DQ[44]
M_A_DQ45 AU49 AJ11 M_A_DQSP0 M_B_DQ45 BG54
SA_DQ[45] SA_DQS[0] SB_DQ[45] M_B_DQSP[7..0] [16]
M_A_DQ46 BA53 AR10 M_A_DQSP1 M_B_DQ46 BA58 AM2 M_B_DQSP0
M_A_DQ47 SA_DQ[46] SA_DQS[1] M_A_DQSP2 M_B_DQ47 SB_DQ[46] SB_DQS[0] M_B_DQSP1
BB55 SA_DQ[47] SA_DQS[2] AY11 AW59 SB_DQ[47] SB_DQS[1] AV1
M_A_DQ48 BA55 AU17 M_A_DQSP3 M_B_DQ48 AW58 BE11 M_B_DQSP2
AV56 SA_DQ[49] SA_DQS[4] AW45 AU58 SB_DQ[49] SB_DQS[3] BD18
M_A_DQ50 AP50 AV51 M_A_DQSP5 M_B_DQ50 AN61 BE51 M_B_DQSP4
AP53 SA_DQ[51] SA_DQS[6] AT56 AN59 SB_DQ[51] SB_DQS[5] BA61
M_A_DQ52 AV54 AK54 M_A_DQSP7 M_B_DQ52 AU59 AR59 M_B_DQSP6
M_A_DQ53 SA_DQ[52] SA_DQS[7] M_B_DQ53 SB_DQ[52] SB_DQS[6] M_B_DQSP7
AT54 SA_DQ[53] AU61 SB_DQ[53] SB_DQS[7] AK61
M_A_DQ54 AP56 M_B_DQ54 AN58
AP52 SA_DQ[55] AR58 SB_DQ[55]
M_A_DQ56 AN57 M_B_DQ56 AK58
AN53 SA_DQ[57] AL58 SB_DQ[57]
M_A_DQ58 AG56 M_B_DQ58 AG58
AG53 SA_DQ[59] AG59 SB_DQ[59]
M_A_DQ60 AN55 M_B_DQ60 AM60
B SA_DQ[60] M_A_A[14..0] [15,17] SB_DQ[60] M_B_A[14..0] [16,17] B
M_A_DQ61 AN52 BG35 M_A_A0 M_B_DQ61 AL59 BF32 M_B_A0
M_A_DQ62 SA_DQ[61] SA_MA[0] M_A_A1 M_B_DQ62 SB_DQ[61] SB_MA[0] M_B_A1
AG55 SA_DQ[62] SA_MA[1] BB34 AF61 SB_DQ[62] SB_MA[1] BE33
M_A_DQ63 AK56 BE35 M_A_A2 M_B_DQ63 AH60 BD33 M_B_A2
SA_DQ[63] SA_MA[2] M_A_A3 SB_DQ[63] SB_MA[2] M_B_A3
SA_MA[3] BD35 SB_MA[3] AU30
AT34 M_A_A4 BD30 M_B_A4
SA_MA[4] M_A_A5 SB_MA[4] M_B_A5
SA_MA[5] AU34 SB_MA[5] AV30
BB32 M_A_A6 BG30 M_B_A6
[15,17] M_A_BS0 BD37 SA_BS[0] SA_MA[7] AT32 [16,17] M_B_BS0 BG39 SB_BS[0] SB_MA[7] BD29
BF36 AY32 M_A_A8 BD42 BE30 M_B_A8
[15,17] M_A_BS1 SA_BS[1] SA_MA[8] [16,17] M_B_BS1 SB_BS[1] SB_MA[8]
BA28 AV32 M_A_A9 AT22 BE28 M_B_A9
[15,17] M_A_BS2 SA_BS[2] SA_MA[9] [16,17] M_B_BS2 SB_BS[2] SB_MA[9]
BE37 M_A_A10 BD43 M_B_A10
SA_MA[11] BA30 SB_MA[11] AT28
BC30 M_A_A12 AV28 M_B_A12
[15,17] M_A_CAS# BE39 SA_CAS# SA_MA[13] AW41 [16,17] M_B_CAS# AV43 SB_CAS# SB_MA[13] BD46
BD39 AY28 M_A_A14 BF40 AT26 M_B_A14
[15,17] M_A_RAS# SA_RAS# SA_MA[14] [16,17] M_B_RAS# SB_RAS# SB_MA[14]
[15,17] M_A_W E# AT41 SA_WE# SA_MA[15] AU26 [16,17] M_B_W E# BD45 SB_WE# SB_MA[15] AU22
IC,SNB_2CBGA,1P0 IC,SNB_2CBGA,1P0
[15] M_A_DQ[0..7] [15] M_A_DQ[32..39] [16] M_B_DQ[0..7] [16] M_B_DQ[32..39]

A A

PROJECT : D13
1A
Sandy Bridge 3/5
1
5 of 41
5 4 3 2 1
f ix Sandy Bridge Processor (POWER) Sandy Bridge Processor (GRAPHIC POWER)

ina
U25F
CPU is i7 in schematic U25G
v
8.5A 18A
+1.05V_VCCIO +VCC_GFX_CORE
SNB:33A AF46 C226 10U/6.3V_6 AA46 10mil

VCCIO[1] C288 10U/6.3V_6 VAXG[1]
+VCC_CORE VCCIO[3] AG48 AB47 VAXG[2]
AG50 C262 *10U/6.3V_6_NC AB50
VCCIO[4] C167 10U/6.3V_6 C286 10U/6.3V_6 VAXG[3] +VDDR_REF_CPU
A26 AG51 AB51 AY43 +VDDR_REF_CPU
VCC[1] VCCIO[5] C212 *10U/6.3V_6_NC C257 10U/6.3V_6 VAXG[4] SM_VREF
A29 VCC[2] VCCIO[6] AJ17 AB52 VAXG[5]
A31 AJ21 C166 10U/6.3V_6 C284 *10U/6.3V_6_NC AB53
VCC[3] VCCIO[7] C160 10U/6.3V_6 C287 10U/6.3V_6 VAXG[6]
A34 AJ25 AB55
VCC[4] VCCIO[8] C229 10U/6.3V_6 C258 10U/6.3V_6 VAXG[7]
A35 AJ43 AB56
VCC[5] VCCIO[9] C175 *10U/6.3V_6_NC C261 *10U/6.3V_6_NC VAXG[8]
D
C216 *10U/6.3V_6_NC
A38
VCC[6] VCCIO[10]
AJ47
C162 10U/6.3V_6 C285 *10U/6.3V_6_NC
AB58
VAXG[9] SNB:5A D
A39 AK50 AB59 AJ28 +1.5V_CPU
C211 10U/6.3V_6 VCC[7] VCCIO[11] C164 10U/6.3V_6 C264 *10U/6.3V_6_NC VAXG[10] VDDQ[1]
A42 VCC[8] VCCIO[12] AK51 AC61 VAXG[11] VDDQ[2] AJ33
C206 10U/6.3V_6 C26 AL14 C157 10U/6.3V_6 C239 10U/6.3V_6 AD47 AJ36 C223 10U/6.3V_6
C196 10U/6.3V_6 VCC[9] VCCIO[13] C222 *10U/6.3V_6_NC C283 *10U/6.3V_6_NC VAXG[12] VDDQ[3] C176 10U/6.3V_6
C27 VCC[10] VCCIO[14] AL15 AD48 VAXG[13] VDDQ[4] AJ40
C217 10U/6.3V_6 C32 AL16 C260 *10U/6.3V_6_NC AD50 AL30 C191 10U/6.3V_6
- 1.5V RAILS
VCC[11] VCCIO[15] C265 *10U/6.3V_6_NC VAXG[14] VDDQ[5] C213 10U/6.3V_6
C34 VCC[12] VCCIO[16] AL20 AD51 VAXG[15] VDDQ[6] AL34
C37 AL22 C263 *10U/6.3V_6_NC AD52 AL38 C181 10U/6.3V_6
VCC[13] VCCIO[17] C245 *1U/6.3V_4_NC C227 10U/6.3V_6 VAXG[16] VDDQ[7] C207 10U/6.3V_6
C39 AL26 AD53 AL42
C190 10U/6.3V_6 VCC[14] VCCIO[18] C148 *1U/6.3V_4_NC C238 10U/6.3V_6 VAXG[17] VDDQ[8] C197 10U/6.3V_6
C42 VCC[15] VCCIO[19] AL45 AD55 VAXG[18] VDDQ[9] AM33
C218 10U/6.3V_6 D27 AL48 C147 *1U/6.3V_4_NC C254 10U/6.3V_6 AD56 AM36 C192 *10U/6.3V_6_NC
C180 10U/6.3V_6 VCC[16] VCCIO[20] C237 *1U/6.3V_4_NC C225 10U/6.3V_6 VAXG[19] VDDQ[10]
D32 VCC[17] VCCIO[21] AM16 AD58 VAXG[20] VDDQ[11] AM40
D34 AM17 C232 *1U/6.3V_4_NC C259 10U/6.3V_6 AD59 AN30
C200 *10U/6.3V_6_NC VCC[18] VCCIO[22] C244 *1U/6.3V_4_NC C252 10U/6.3V_6 VAXG[21] VDDQ[12] C209 1U/6.3V_4
D37 VCC[19] VCCIO[23] AM21 AE46 VAXG[22] VDDQ[13] AN34
C201 10U/6.3V_6 C224 1U/6.3V_4 C195 *1U/6.3V_4_NC
POWER
D39 AM43 N45 AN38
VCC[20] VCCIO[24] C161 1U/6.3V_4 VAXG[23] VDDQ[14] C187 1U/6.3V_4
D42 AM47 P47 AR26
C295 *10U/6.3V_6_NC VCC[21] VCCIO[25] C168 1U/6.3V_4 VAXG[24] VDDQ[15] C169 *1U/6.3V_4_NC
E26 AN20 P48 AR28
VCC[22] VCCIO[26] C247 *1U/6.3V_4_NC C248 1U/6.3V_4 VAXG[25] VDDQ[16] C210 *1U/6.3V_4_NC
E28 AN42 P50 AR30
VCC[23] VCCIO[27] C250 1U/6.3V_4 VAXG[26] VDDQ[17] C228 *1U/6.3V_4_NC
E32 AN45 P51 AR32
E34 AN48 P52 AR34
DDR3
E37 P53 AR36
VCC[26] C231 1U/6.3V_4 C256 1U/6.3V_4 VAXG[29] VDDQ[20] C194 1U/6.3V_4
E38 P55 AR40
VCC[27] CORE SUPPLY C235 1U/6.3V_4 VAXG[30] VDDQ[21] C198 *1U/6.3V_4_NC
F25 P56 AV41
C184 1U/6.3V_4 VCC[28] C233 1U/6.3V_4 VAXG[31] VDDQ[22] C178 *1U/6.3V_4_NC
F26 P61 AW26
PEG AND DDR

C299 *1U/6.3V_4_NC VCC[29] C243 *1U/6.3V_4_NC VAXG[32] VDDQ[23]
F28 VCC[30] T48 VAXG[33] VDDQ[24] BA40
GRAPHICS
C204 1U/6.3V_4 F32 C144 *1U/6.3V_4_NC T58 BB28
C221 1U/6.3V_4 VCC[31] C240 1U/6.3V_4 VAXG[34] VDDQ[25]
F34 T59 BG33
C173 *1U/6.3V_4_NC VCC[32] C236 *1U/6.3V_4_NC VAXG[35] VDDQ[26]
F37 AA14 T61
C185 1U/6.3V_4 VCC[33] VCCIO[30] C230 1U/6.3V_4 VAXG[36]
F38 AA15 U46
C205 1U/6.3V_4 F42
VCC[34] VCCIO[31]
AB17 C155 1U/6.3V_4 V47
VAXG[37] +1.5V_SUS 5A +1.5V_CPU
VCC[35] VCCIO[32] C149 *1U/6.3V_4_NC VAXG[38]
G42 AB20 V48 Q26
C296 1U/6.3V_4 VCC[36] VCCIO[33] C154 1U/6.3V_4 VAXG[39]
H25 VCC[37] VCCIO[34] AC13 V50 VAXG[40]
C203 1U/6.3V_4 H26 AD16 C146 *1U/6.3V_4_NC V51 AON7410
C202 *1U/6.3V_4_NC VCC[38] VCCIO[35] C145 *1U/6.3V_4_NC VAXG[41]
H28 VCC[39] VCCIO[36] AD18 V52 VAXG[42]
C172 1U/6.3V_4 H29 AD21 V53 8 3
C
C219 *1U/6.3V_4_NC VCC[40] VCCIO[37] VAXG[43] C
H32 AE14 V55 7 2
C174 1U/6.3V_4 VCC[41] VCCIO[38] VAXG[44]
H34 VCC[42] VCCIO[39] AE15 V56 VAXG[45] 6 1
C220 *1U/6.3V_4_NC H35 AF16 V58 5
C186 1U/6.3V_4 VCC[43] VCCIO[40] VAXG[46]
H37 VCC[44] VCCIO[41] AF18 V59 VAXG[47]
H38 AF20 W50
4
VCC[45] VCCIO[42] VAXG[48]
H40
VCC[46] VCCIO[43]
AG15 W51
VAXG[49] check with power Andy
J25 AG16 W52 [8] PS_S3CNTRL_S
J26 AG17 W53
J28 VCC[49] VCCIO[46] AG20 W55 VAXG[52]
J29 AG21 W56
VCC[50] VCCIO[47] VAXG[53] C241
J32 AJ14 W61
POWER
J34 AJ15 Y48 *4700P/25V/X7R_4_NC

J35 Y61
VCC[53] VAXG[56]
J37
VCC[54]
J38
VCC[55]
J40
VCC[56]
J42
VCC[57] Follow check list of Intel
K26 W16
QUIET RAILS
VCC[58] VCCIO50 R140 10/F_4
K27 W17 +VCC_GFX_CORE AM28 +1.5V_CPU
VCC[59] VCCIO51 VCCDQ[1]
LINES
SENSE
K29 [37] VCC_AXG_SENSE F45 AN26
VCC[60] 10/F_4 R142 VAXG_SENSE VCCDQ[2] C188 1U/6.3V_4
K32 [37] VSS_AXG_SENSE G45
VCC[61] 10/F_4 R143 R141 10/F_4 VSSAXG_SENSE
K34
VCC[62]
K35
VCC[63]
K37
VCC[64]
K39
VCC[66] 3A
1.8V RAIL
K42 BC22 +1.8V_RUN
VCC[67] VCCIO_SEL
L25
VCC[68]
L28 BB3
VCC[69] C309 1U/6.3V_4 VCCPLL[1]
L33 BC1
VCC[70] C310 1U/6.3V_4 VCCPLL[2]
L36 BC4
VCC[71] VCCPLL[3]
L40
QUIET RAILS
VCC[72]
N26
VCC[73]
N30 VCC[74] VCCPQE[1] AM25 +1.05V_VCCIO
N34 VCC[75] VCCPQE[2] AN22 VDDQ_SENSE BC43
B N38 C246 1U/6.3V_4 BA43 B
SENSE LINES
VCC[76] VSS_SENSE_VDDQ
L17
VCCSA[1]
SNB:6A L21
VCCSA[2]
+VCCSA_CORE N16 VCCSA[3]
N20
VCCSA[4]
SA RAIL
C170 10U/6.3V_6 N22
H_CPU_SVIDALRT# C171 *10U/6.3V_6_NC VCCSA[5] R126 100/F_4
A44 P17 +VCCSA_CORE
VIDALERT# VR_SVID_CLK C156 *10U/6.3V_6_NC VCCSA[6]
B43 P20 U10
SVID
VIDSCLK VR_SVID_CLK [37] VCCSA[7] VCCSA_SENSE VCCSA_SENSE [36]

C44 VR_SVID_DATA C163 10U/6.3V_6 R16
VIDSOUT C152 10U/6.3V_6 VCCSA[8]
R18 VCCSA[9]
R21
VCCSA[10]
U15
C158 1U/6.3V_4 VCCSA[11]
V16
C159 1U/6.3V_4 VCCSA[12] VCCSA_VID0
V17 D48 1 R13910K_4
2
C165 1U/6.3V_4 VCCSA[13] VCCSA_VID[0] VCCSA_VID1
V18 D49 VCCSA_VID1 [36]
C151 *1U/6.3V_4_NC VCCSA[14] VCCSA_VID[1]
Follow check list of Intel C150 *1U/6.3V_4_NC
V21 VCCSA[15]
W20
R134 100/F_4 VCCSA[16]
+VCC_CORE Sandy Bridge only:
F43 VCCSA_VID[0] should be pull down
SENSE LINES
VCC_SENSE VCCSENSE [37]

G43 VSSSENSE [37]
VSS_SENSE R135 100/F_4 VCCSA_VID[1] should connect to SA VR
08/11 +VDDR_REF_CPU +1.5V_CPU
IC,SNB_2CBGA,1P0
R127 *10/F_4_NC For CPU cost down plan
+1.05V_VCCIO
AN16 VCCIO_SENSE [35]
C151, C150
VCCIO_SENSE R138
AN17 VSSIO_SENSE [35]
VSS_SENSE_VCCIO R128 *10/F_4_NC
1K/F_4
IC,SNB_2CBGA,1P0
Follow check list of Intel
+1.5V_SUS C179 0.1U/16V_4 +1.5V_CPU R137
C182 0.1U/16V_4
A A
C189 0.1U/16V_4 C234
C193 0.1U/16V_4 1K/F_4 0.1U/16V_4
+1.05V_VCCIO SVID DATA SVID ALERT +1.05V_VCCIO
Place resistor R175 close to CPU

Place resistor R55 close to CPU Quanta Computer Inc.
R173 R175
130/F_4 75_4
PROJECT : D13
http://vinafix.vn
VR_SVID_DATA H_CPU_SVIDALRT# R176 43_4 VR_SVID_ALERT# Size Document Number Rev
VR_SVID_DATA [37] VR_SVID_ALERT# [37]
1A
Sandy Bridge 4/5
Date: Thursday, October 13, 2011 Sheet 6 of 41
5 4 3 2 1
5 4 3 2 1
fix
vina Sandy Bridge Processor (GND)
CPU is i7 in schematic CPU is i7 in schematic
Sandy Bridge Processor (RESERVED, CFG)
U25H U25I
U25E
BG17 VSS[181] VSS[251] M4

A13 VSS[1] VSS[91] AM38 BG21 VSS[182] VSS[252] M58 B50 CFG[0] RSVD28 BE7
D A17 VSS[2] VSS[92] AM4 BG24 VSS[183] VSS[253] M6 C51 CFG[1] RSVD29 BG7 D
A21 AM42 BG28 N1 T72 CFG2 B54
VSS[3] VSS[93] VSS[184] VSS[254] T74 CFG3 CFG[2]
A25 VSS[4] VSS[94] AM45 BG37 VSS[185] VSS[255] N17 D53 CFG[3]
A28 AM48 BG41 N21 T76 CFG4 A51 N42
VSS[5] VSS[95] VSS[186] VSS[256] T73 CFG5 CFG[4] RSVD30
A33 VSS[6] VSS[96] AM58 BG45 VSS[187] VSS[257] N25 C53 CFG[5] RSVD31 L42
A37 AN1 BG49 N28 T71 CFG6 C55 L45
VSS[7] VSS[97] VSS[188] VSS[258] CFG[6] RSVD32
A40 VSS[8] VSS[98] AN21 BG53 VSS[189] VSS[259] N33 H49 CFG[7] RSVD33 L47
A45 VSS[9] VSS[99] AN25 BG9 VSS[190] VSS[260] N36 A55 CFG[8]
A49 VSS[10] VSS[100] AN28 C29 VSS[191] VSS[261] N40 H51 CFG[9]
A53 VSS[11] VSS[101] AN33 C35 VSS[192] VSS[262] N43 K49 CFG[10] RSVD34 M13
A9 VSS[12] VSS[102] AN36 C40 VSS[193] VSS[263] N47 K53 CFG[11] RSVD35 M14
AA1 VSS[13] VSS[103] AN40 D10 VSS[194] VSS[264] N48 F53 CFG[12] RSVD36 U14
AA13 VSS[14] VSS[104] AN43 D14 VSS[195] VSS[265] N51 G53 CFG[13] RSVD37 W14
AA50 VSS[15] VSS[105] AN47 D18 VSS[196] VSS[266] N52 L51 CFG[14] RSVD38 P13
AA51 VSS[16] VSS[106] AN50 D22 VSS[197] VSS[267] N56 F51 CFG[15]
AA52 VSS[17] VSS[107] AN54 D26 VSS[198] VSS[268] N61 D52 CFG[16]
AA53 VSS[18] VSS[108] AP10 D29 VSS[199] VSS[269] P14 L53 CFG[17] RSVD39 AT49
AA55 VSS[19] VSS[109] AP51 D35 VSS[200] VSS[270] P16 RSVD40 K24
AA56 AP55 D4 P18
RESERVED
VSS[20] VSS[110] VSS[201] VSS[271] T55
AA8 VSS[21] VSS[111] AP7 D40 VSS[202] VSS[272] P21 H43 VCC_VAL_SENSE
AB16 AR13 D43 P58 T52 K43 AH2
AB18
AB21
VSS[22]
VSS[23]
VSS[24]
VSS[112]
VSS[113]
VSS[114]
AR17
AR21
D46
D50
VSS[203]
VSS[204]
VSS[205]
VSS VSS[273]
VSS[274]
VSS[275]
P59
P9
VSS_VAL_SENSE RSVD41
RSVD42
RSVD43
AG13
AM14
AB48 AR41 D54 R17 T54 H45 AM15
VSS[25] VSS[115] VSS[206] VSS[276] T53 VAXG_VAL_SENSE RSVD44
AB61 VSS[26] VSS[116] AR48 D58 VSS[207] VSS[277] R20 K45 VSSAXG_VAL_SENSE
AC10 VSS[27] VSS[117] AR61 D6 VSS[208] VSS[278] R4
AC14 VSS[28] VSS[118] AR7 E25 VSS[209] VSS[279] R46 RSVD45 N50
AC46 VSS[29] VSS[119] AT14 E29 VSS[210] VSS[280] T1 F48 VCC_DIE_SENSE
AC6 VSS[30] VSS[120] AT19 E3 VSS[211] VSS[281] T47
C AD17 AT36 E35 T50 C
VSS[31] VSS[121] VSS[212] VSS[282]
AD20 VSS[32] VSS[122] AT4 E40 VSS[213] VSS[283] T51 H48 RSVD6
AD4 AT45 F13 T52 K48
AD61
AE13
VSS[33]
VSS[34]
VSS[35]
VSS VSS[123]
VSS[124]
VSS[125]
AT52
AT58
F15
F19
VSS[214]
VSS[215]
VSS[216]
VSS[284]
VSS[285]
VSS[286]
T53
T55
RSVD7
DC_TEST_A4
DC_TEST_C4
A4
C4
AE8 VSS[36] VSS[126] AU1 F29 VSS[217] VSS[287] T56 BA19 RSVD8 DC_TEST_D3 D3
AF1 VSS[37] VSS[127] AU11 F35 VSS[218] VSS[288] U13 AV19 RSVD9 DC_TEST_D1 D1
AF17 VSS[38] VSS[128] AU28 F40 VSS[219] VSS[289] U8 AT21 RSVD10 DC_TEST_A58 A58
AF21 VSS[39] VSS[129] AU32 F55 VSS[220] VSS[290] V20 BB21 RSVD11 DC_TEST_A59 A59
AF47 VSS[40] VSS[130] AU51 G48 VSS[221] VSS[291] V61 BB19 RSVD12 DC_TEST_C59 C59
AF48 VSS[41] VSS[131] AU7 G51 VSS[222] VSS[292] W13 AY21 RSVD13 DC_TEST_A61 A61
AF50 VSS[42] VSS[132] AV17 G6 VSS[223] VSS[293] W15 BA22 RSVD14 DC_TEST_C61 C61
AF51 VSS[43] VSS[133] AV21 G61 VSS[224] VSS[294] W18 AY22 RSVD15 DC_TEST_D61 D61
AF52 VSS[44] VSS[134] AV22 H10 VSS[225] VSS[295] W21 AU19 RSVD16 DC_TEST_BD61 BD61
AF53 VSS[45] VSS[135] AV34 H14 VSS[226] VSS[296] W46 AU21 RSVD17 DC_TEST_BE61 BE61
AF55 VSS[46] VSS[136] AV40 H17 VSS[227] VSS[297] W8 BD21 RSVD18 DC_TEST_BE59 BE59
AF56 VSS[47] VSS[137] AV48 H21 VSS[228] VSS[298] Y4 BD22 RSVD19 DC_TEST_BG61 BG61
AF58 VSS[48] VSS[138] AV55 H4 VSS[229] VSS[299] Y47 BD25 RSVD20 DC_TEST_BG59 BG59
AF59 VSS[49] VSS[139] AW13 H53 VSS[230] VSS[300] Y58 BD26 RSVD21 DC_TEST_BG58 BG58
AG10 VSS[50] VSS[140] AW43 H58 VSS[231] VSS[301] Y59 BG22 RSVD22 DC_TEST_BG4 BG4
AG14 VSS[51] VSS[141] AW61 J1 VSS[232] BE22 RSVD23 DC_TEST_BG3 BG3
AG18 VSS[52] VSS[142] AW7 J49 VSS[233] BG26 RSVD24 DC_TEST_BE3 BE3
AG47 VSS[53] VSS[143] AY14 J55 VSS[234] BE26 RSVD25 DC_TEST_BG1 BG1
AG52 VSS[54] VSS[144] AY19 K11 VSS[235] BF23 RSVD26 DC_TEST_BE1 BE1
AG61 VSS[55] VSS[145] AY30 K21 VSS[236] BE24 RSVD27 DC_TEST_BD1 BD1
AG7 VSS[56] VSS[146] AY36 K51 VSS[237] VSS_NCTF_1 A5
AH4 VSS[57] VSS[147] AY4 K8 VSS[238] VSS_NCTF_2 A57
AH58 VSS[58] VSS[148] AY41 L16 VSS[239] VSS_NCTF_3 BC61
AJ13 VSS[59] VSS[149] AY45 L20 VSS[240] VSS_NCTF_4 BD3
B IC,SNB_2CBGA,1P0 B
AJ16 AY49 L22 BD59
NCTF
VSS[60] VSS[150] VSS[241] VSS_NCTF_5

AJ20 VSS[61] VSS[151] AY55 L26 VSS[242] VSS_NCTF_6 BE4
AJ22 VSS[62] VSS[152] AY58 L30 VSS[243] VSS_NCTF_7 BE58
AJ26 VSS[63] VSS[153] AY9 L34 VSS[244] VSS_NCTF_8 BG5
AJ30 VSS[64] VSS[154] BA1 L38 VSS[245] VSS_NCTF_9 BG57
AJ34 VSS[65] VSS[155] BA11 L43 VSS[246] VSS_NCTF_10 C3
AJ38 VSS[66] VSS[156] BA17 L48 VSS[247] VSS_NCTF_11 C58
AJ42 VSS[67] VSS[157] BA21 L61 VSS[248] VSS_NCTF_12 D59
AJ45 VSS[68] VSS[158] BA26 M11 VSS[249] VSS_NCTF_13 E1
AJ48 VSS[69] VSS[159] BA32 M15 VSS[250] VSS_NCTF_14 E61
AJ7 VSS[70] VSS[160] BA48 PGB straping pin unused for UMA only
AK1 VSS[71] VSS[161] BA51
AK52 VSS[72] VSS[162] BB53
AL10 VSS[73] VSS[163] BC13 CFG[6:5] (PCIE Port Bifurcation Straps)
AL13 VSS[74] VSS[164] BC5
AL17 BC57 IC,SNB_2CBGA,1P0 11: (Default) x16 - Device 1 functions 1 and 2 disabled
VSS[75] VSS[165]
AL21 VSS[76] VSS[166] BD12 10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
AL25 BD16
AL28
VSS[77] VSS[167]
BD19
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
VSS[78] VSS[168] 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
AL33 VSS[79] VSS[169] BD23
AL36 VSS[80] VSS[170] BD27
AL40 VSS[81] VSS[171] BD32
AL43 VSS[82] VSS[172] BD36
AL47 VSS[83] VSS[173] BD40
AL61 BD44
AM13
VSS[84]
VSS[85]
VSS[174]
VSS[175] BD48 Processor Strapping
AM20 VSS[86] VSS[176] BD52
AM22 VSS[87] VSS[177] BD56
A AM26 VSS[88] VSS[178] BD8 1 0 A
AM30 VSS[89] VSS[179] BE5
AM34 VSS[90] VSS[180] BG13 CFG2
(PCI-E Static x16 Lane Reversal) Normal Operation Lane Reversed
CFG3
IC,SNB_2CBGA,1P0 (PCI-E Static x4 Lane Reversal) Normal Operation Lane Reversed Quanta Computer Inc.
CFG4
PROJECT : D13
Disable; No physical DP attached to eDP Enable; An ext DP device is connected to eDP Size Document Number Rev
(DP Presence Strap) Sandy Bridge 5/5 1A
1
7 of 41
5 4 3 2 1
f ix Cougar Point (DMI,FDI,PM)

ina
PCH Pull-high/low(CLG)
v
U31C
+3.3V_SUS
[3] DMI_RXN0 BL21 DMI0RXN FDI_RXN0 BL13 FDI_TXN0 [3]
BL23 BJ15 RN1
[3] DMI_RXN1 DMI1RXN FDI_RXN1 FDI_TXN1 [3]
BJ19 BD12 PM_BATLOW # 1 2
BL17 BJ11 PCIE_W AKE# 3 4
AY15 PM_RI# 5 6
FDI_RXN4 FDI_TXN4 [3]
BJ21 AY12 SIO_SLP_LAN# 7 8
[3] DMI_RXP0 DMI0RXP FDI_RXN5 FDI_TXN5 [3]
[3] DMI_RXP1 BJ23 DMI1RXP FDI_RXN6 BJ9 FDI_TXN6 [3]
D BL19 BF10 10K D
[3] DMI_RXP2 DMI2RXP FDI_RXN7 FDI_TXN7 [3]
[3] DMI_RXP3 BJ17 RP10
DMI3RXP ME_SUS_PW R_ACK
FDI_RXP0 BJ13 FDI_TXP0 [3] 1 2
BD22 BL15 AC_PRESENT 3 4
[3] DMI_TXN0 DMI0TXN FDI_RXP1 FDI_TXP1 [3]
[3] DMI_TXN1 BB22 DMI1TXN FDI_RXP2 BF12 FDI_TXP2 [3]
[3] DMI_TXN2 BB19 BL11 FDI_TXP3 [3] 10K
DMI2TXN FDI_RXP3
BB17 BB15
DMI
FDI
[3] DMI_TXN3 DMI3TXN FDI_RXP4 FDI_TXP4 [3]
FDI_RXP5 BB12 FDI_TXP5 [3]
[3] DMI_TXP0 BF22 DMI0TXP FDI_RXP6 BL9 FDI_TXP6 [3]
[3] DMI_TXP1 AY22 DMI1TXP FDI_RXP7 BD10 FDI_TXP7 [3]
[3] DMI_TXP2 AY19 DMI2TXP
[3] DMI_TXP3 AY17 DMI3TXP
FDI_INT BB10 FDI_INT [3]
BF19 DMI_ZCOMP FDI_FSYNC0 BH12 FDI_FSYNC0 [3]
+1.05V_PCH R203 49.9/F_4 DMI_COMP BD19 BK8

DMI_IRCOMP FDI_FSYNC1 FDI_FSYNC1 [3]
R202 750/F_4 DMI2RBIAS BK20 BK12 +3.3V_RUN
DMI2RBIAS FDI_LSYNC0 FDI_LSYNC0 [3]
FDI_LSYNC1 BH8 FDI_LSYNC1 [3]

CLKRUN# R194 10K_4
XDP_DBRST# R213 1K_4

F22 DSW VRMEN
DSWVRMEN
System Power Management

ME_SUS_PW R_ACK F15 A21 RSMRST# RSMRST# R225 10K_4
SUSACK# DPWROK
C SYS_PW ROK R214 100K_4 C
XDP_DBRST# L1 D8 PCIE_W AKE# PCIE_W AKE# [22]
[4] XDP_DBRST# SYS_RESET# WAKE#
SYS_PW ROK M10 T2 CLKRUN#

SYS_PWROK CLKRUN# / GPIO32 CLKRUN# [22]
+3V
[4,22] EC_PW ROK M22 PWROK SUS_STAT# / GPIO61 G6
+3V_S5
G3 D3 SUSCLK +RTC_CELL
[22,30] HW PG APWROK SUSCLK / GPIO62 T19
+3V_S5
[4] PM_DRAM_PW RGD B12 DRAMPWROK SLP_S5# / GPIO63 F6 SIO_SLP_S5# [22,34]
+3V_S5 R217
330K_4
T90
RSMRST# B20 K10 SLP_S4# W/O support
[22] RSMRST# RSMRST# SLP_S4# SLP_S4# [20,22,34]
DSW VRMEN
ME_SUS_PW R_ACK C13 D4
[22] ME_SUS_PW R_ACK SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# SIO_SLP_S3# [22,34]
+3V_S5
[22] SIO_PW RBTN# K19 PWRBTN# SLP_A# C7 W/O support iAMT
DSW
AC_PRESENT H19 A15
[22] AC_PRESENT ACPRESENT / GPIO31 SLP_SUS#
DSW W/O support Deep Sx
PM_BATLOW # H10 BB8 H_PM_SYNC [4]
On Die DSW VR Enable
B BATLOW# / GPIO72 PMSYNCH B
W/O support +3V_S5
High = Enable (Default)
PM_RI# F12 A7 SIO_SLP_LAN# T13 W/O support iAMT
RI# SLP_LAN# / GPIO29
+3V_S5 Low = Disable
CougarPoint-H_SFF_Rev_1_0
S3 Power reduce +5V_ALW

S3 Power reduce Copy From GM6 System PWR_OK(CLG) +3.3V_SUS
+15V_ALW
1
R75
10K_4 C71
R73 *0.1U/10V/X7R_4_NC
100K_4
2
5
U7
PS_S3CNTRL [17]
PS_S3CNTRL 2 IMVP_PW RGD [22,28,37]
SYS_PW ROK 4
A PS_S3CNTRL_S [6] [4] SYS_PW ROK A
1 EC_PW ROK
3
Q20
SIO_SLP_S3# 2 PMF780SN TC7SH08FU 3
3
Q19
R74 PMF780SN PS_S3CNTRL 2 C72 R66
1
*10K_4_NC *0.01U/25V_4_NC 100K_4

1
PROJECT : D13
1A
Cougar Point 1/7
1
8 of 41
5 4 3 2 1
f ix Cougar Point (LVDS,DDI) Cougar Point (GND)

ina
U31H
v
U31I G7 VSS[0]
U31D BA25 J18 AA11 AL41
VSS[159] VSS[264] VSS[1] VSS[80]
BA27 VSS[160] VSS[265] J21 AA39 VSS[2] VSS[81] AL43
PANEL_BKEN M44 AU40 BA29 J23 AA41 AL45
[22] PANEL_BKEN L_BKLTEN SDVO_TVCLKINN VSS[161] VSS[266] VSS[3] VSS[82]
ENVDD M42 AU42 BA31 J25 AA43 AL7
[19] ENVDD L_VDD_EN SDVO_TVCLKINP VSS[162] VSS[267] VSS[4] VSS[83]
BA34 VSS[163] VSS[268] J27 AA45 VSS[5] VSS[84] AL9
[19] LCD_PW M L49 L_BKLTCTL SDVO_STALLN AR51 BA36 VSS[164] VSS[269] J29 AA7 VSS[6] VSS[85] AM15
SDVO_STALLP AR49 BA39 VSS[165] VSS[270] J31 AA9 VSS[7] VSS[86] AM19
LCD_DDCCLK L51 BA41 J34 AB17 AM25
[19] LCD_DDCCLK LCD_DDCDAT L_DDC_CLK VSS[166] VSS[271] VSS[8] VSS[87]
D
[19] LCD_DDCDAT K46 L_DDC_DATA SDVO_INTN AT50 BA43 VSS[167] VSS[272] J36 AB2 VSS[9] VSS[88] AM29 D
SDVO_INTP AT48 BA45 VSS[168] VSS[273] L25 AB25 VSS[10] VSS[89] AM31
L_CTRL_CLK R42 BA7 J41 AB33 AM37
L_CTRL_DATA L_CTRL_CLK VSS[169] VSS[274] VSS[11] VSS[90]
M40 L_CTRL_DATA BA9 VSS[170] VSS[275] J45 AB35 VSS[12] VSS[91] AP11
T36 BB4 VSS[171] VSS[276] J7 AB37 VSS[13] VSS[92] AP17
R118 2.37K/F_4 LVDS_IBG AH42 W42 F2 J9 AB4 AP2
LVDS_VBG LVD_IBG SDVO_CTRLCLK VSS[172] VSS[277] VSS[14] VSS[93]
T37 AH40 LVD_VBG SDVO_CTRLDATA R44 BB48 VSS[173] VSS[278] K2 AB48 VSS[15] VSS[94] AP21
T35 BB50 VSS[174] VSS[279] K4 AB50 VSS[16] VSS[95] AP23
AG51 LVD_VREFH BC11 VSS[175] VSS[280] K48 AC11 VSS[17] VSS[96] AP25
AG49 LVD_VREFL DDPB_AUXN AW51 BC13 VSS[176] VSS[281] K50 AC17 VSS[18] VSS[97] AP29
DDPB_AUXP AW49 BC16 VSS[177] VSS[282] L11 AC25 VSS[19] VSS[98] AP31
DDPB_HPD AY42 BC18 VSS[178] VSS[283] L13 AC41 VSS[20] VSS[99] AP33
AK44 BC21 L16 AC43 AP35
LVDS
[19] INT_TXLCLKOUTN LVDSA_CLK# VSS[179] VSS[284] VSS[21] VSS[100]
[19] INT_TXLCLKOUTP AK46 LVDSA_CLK DDPB_0N AY48 BC23 VSS[180] VSS[285] L18 AC45 VSS[22] VSS[101] AP37
DDPB_0P AY50 BC25 VSS[181] VSS[286] L29 AC7 VSS[23] VSS[102] AP4
[19] INT_TXLOUTN0 AR46 LVDSA_DATA#0 DDPB_1N AY44 BC27 VSS[182] VSS[287] L21 AE13 VSS[24] VSS[103] AP41
AN49 AY46 BC29 L23 AE15 AP43
Digital Display Interface

[19] INT_TXLOUTN1 LVDSA_DATA#1 DDPB_1P VSS[183] VSS[288] VSS[25] VSS[104]
[19] INT_TXLOUTN2 AN44 LVDSA_DATA#2 DDPB_2N BB44 BC31 VSS[184] VSS[289] L27 AE17 VSS[26] VSS[105] AP45
AK40 LVDSA_DATA#3 DDPB_2P BB46 BC34 VSS[185] VSS[290] L9 AE25 VSS[27] VSS[106] AP48
DDPB_3N BA49 BC36 VSS[186] VSS[291] L31 AE35 VSS[28] VSS[107] AP50
[19] INT_TXLOUTP0 AR44 LVDSA_DATA0 DDPB_3P BA51 BC39 VSS[187] VSS[292] L34 AE41 VSS[29] VSS[108] AP7
[19] INT_TXLOUTP1 AN51 LVDSA_DATA1 BC41 VSS[188] VSS[293] L36 AE43 VSS[30] VSS[109] AP9
[19] INT_TXLOUTP2 AN46 LVDSA_DATA2 BC43 VSS[189] VSS[294] L39 AE45 VSS[31] VSS[110] AR19
AK42 T50 INT_DP_SCL BC45 L41 AE7 AR21
LVDSA_DATA3 DDPC_CTRLCLK INT_DP_SDA INT_DP_SCL [18] VSS[190] VSS[295] VSS[32] VSS[111]
DDPC_CTRLDATA U44 INT_DP_SDA [18] BE11 VSS[191] VSS[296] L43 AE9 VSS[33] VSS[112] AR31
LCD AH46 Mini DP BE13
BE16
VSS[192] VSS[297] L45
L7
AF19
AF2
VSS[34] VSS[113] AR35
AR37
LVDSB_CLK# VSS[193] VSS[298] VSS[35] VSS[114]
AH44 LVDSB_CLK DDPC_AUXN AU51 INT_DP_AUXN_C [18] BE21 VSS[194] VSS[299] N13 AF25 VSS[36] VSS[115] AT11
DDPC_AUXP AU49 INT_DP_AUXP_C [18] BE23 VSS[195] VSS[300] N21 AF27 VSS[37] VSS[116] AT39
C AM50 BE46 INT_DP_HPD BE27 R37 AF29 AT41 C
LVDSB_DATA#0 DDPC_HPD VSS[196] VSS[301] VSS[38] VSS[117]
AL49 LVDSB_DATA#1 BE29 VSS[197] VSS[302] N23 AF31 VSS[39] VSS[118] AT43
AJ51 LVDSB_DATA#2 DDPC_0N BC49 INT_DP_TXN0_C [18] BE31 VSS[198] VSS[303] N29 AF4 VSS[40] VSS[119] AT45
AH50 LVDSB_DATA#3 DDPC_0P BC51 INT_DP_TXP0_C [18] BE34 VSS[199] VSS[304] N31 AF48 VSS[41] VSS[120] AT7
DDPC_1N BD48 INT_DP_TXN1_C [18] BE36 VSS[200] VSS[305] N34 AF50 VSS[42] VSS[121] AT9
AM48 LVDSB_DATA0 DDPC_1P BD50 INT_DP_TXP1_C [18] BE39 VSS[201] VSS[306] N39 AG11 VSS[43] VSS[122] AU17
AL51 LVDSB_DATA1 DDPC_2N BF46 INT_DP_TXN2_C [18] BE41 VSS[202] VSS[307] N41 AG17 VSS[44] VSS[123] AU37
AJ49 LVDSB_DATA2 DDPC_2P BF45 INT_DP_TXP2_C [18] BE43 VSS[203] VSS[308] N43 AC9 VSS[45] VSS[124] AV2
AH48 LVDSB_DATA3 DDPC_3N BE49 INT_DP_TXN3_C [18] BE45 VSS[204] VSS[309] N45 AE11 VSS[46] VSS[125] AV4
DDPC_3P BE51 INT_DP_TXP3_C [18] BE7 VSS[205] VSS[310] N7 AG19 VSS[47] VSS[126] AV48
BE9 VSS[206] VSS[311] N9 AG29 VSS[48] VSS[127] AV50
BE18 VSS[207] VSS[312] P2 AG31 VSS[49] VSS[128] AW11
T25 M46 CRT_BLUE DDPD_CTRLCLK M48 BF2 VSS[208] VSS[313] P4 AG35 VSS[50] VSS[129] AW13
T29 R46 CRT_GREEN DDPD_CTRLDATA U42 BF4 VSS[209] VSS[314] P48 AG41 VSS[51] VSS[130] AW23
T31 U46 CRT_RED BF48 VSS[210] VSS[315] P50 AG43 VSS[52] VSS[131] AW25
BF50 VSS[211] VSS[316] R17 AG45 VSS[53] VSS[132] AW27
AU46 BH10 R21 AG7 AW29
CRT
DDPD_AUXN VSS[212] VSS[317] VSS[54] VSS[133]

T84 R49 CRT_DDC_CLK DDPD_AUXP AU44 BH14 VSS[213] VSS[318] R31 AG9 VSS[55] VSS[134] AW36
T86 N49 CRT_DDC_DATA DDPD_HPD BK44 BH26 VSS[214] VSS[319] T11 AH2 VSS[56] VSS[135] AW39
BH32 VSS[215] VSS[320] T13 AJ11 VSS[57] VSS[136] AW43
DDPD_0N BG51 BH34 VSS[216] VSS[321] T41 AJ19 VSS[58] VSS[137] AW45
T87 M50 CRT_HSYNC DDPD_0P BG49 BH38 VSS[217] VSS[322] T43 AJ33 VSS[59] VSS[138] AW7
T85 N51 CRT_VSYNC DDPD_1N BF42 BH42 VSS[218] VSS[323] T45 AJ35 VSS[60] VSS[139] AW9
DDPD_1P BD42 BH44 VSS[219] VSS[324] T7 AJ39 VSS[61] VSS[140] AY10
DDPD_2N BJ47 BH46 VSS[220] VSS[325] T9 AJ41 VSS[62] VSS[141] B10
DAC_IREF R51 BL47 G21 BH28 AJ43 B14
DAC_IREF DDPD_2P VSS[221] VSS[328] VSS[63] VSS[142]
T48 CRT_IRTN DDPD_3N BL45 BH48 VSS[222] VSS[329] N25 AJ45 VSS[64] VSS[143] B18
R102 BJ45 BH6 AF8 AJ7 B22
DDPD_3P VSS[223] VSS[330] VSS[65] VSS[144]
1K_4 BK10 VSS[224] VSS[331] AF35 AJ9 VSS[66] VSS[145] B26
B CougarPoint-H_SFF_Rev_1_0 B
BK14 VSS[225] VSS[333] BB2 AK17 VSS[67] VSS[146] B30
BK18 VSS[226] VSS[334] BE25 AK19 VSS[68] VSS[147] B34
If CRT hasn't used, it can changed to 5% BK22 VSS[227] VSS[335] BH30 AK2 VSS[69] VSS[148] B38
BK26 VSS[228] VSS[337] F4 AK23 VSS[70] VSS[149] B42
D14 VSS[229] VSS[338] G25 AK25 VSS[71] VSS[150] B46
BK32 VSS[230] VSS[340] N11 AK27 VSS[72] VSS[151] B6
BK34 VSS[231] VSS[342] BH18 AK35 VSS[73] VSS[152] BA11
BK38 VSS[232] VSS[343] BH22 AK37 VSS[74] VSS[153] BA13
BK42 VSS[233] VSS[344] BK30 AK4 VSS[75] VSS[154] BA16
BK46 VSS[234] VSS[345] AR17 AK48 VSS[76] VSS[155] AW41
D10 VSS[235] VSS[346] J39 AK50 VSS[77] VSS[156] BA18
+3.3V_RUN D18 U31 AL11 BA21
VSS[236] VSS[353] VSS[78] VSS[157]
D22 VSS[237] VSS[354] U49 AL39 VSS[79] VSS[158] BA23
RP5 2.2KX2 D26 V11
LCD_DDCDAT VSS[238] VSS[355] CougarPoint-H_SFF_Rev_1_0
1 2 D30 VSS[239] VSS[356] V15
LCD_DDCCLK 3 4 D34 V17
VSS[240] VSS[357]
D38 VSS[241] VSS[358] V2
D42 VSS[242] VSS[359] V27
RP7 2.2KX2 D46 V29
INT_DP_SCL VSS[243] VSS[360]
1 2 F48 VSS[244] VSS[361] V33
INT_DP_SDA 3 4 F50 V35
VSS[245] VSS[362]
G11 VSS[246] VSS[363] V4
G13 VSS[247] VSS[364] V41
Follow R05 QT stage design RP6 2.2KX2 G16 V43
L_CTRL_CLK VSS[248] VSS[365]
1 4 G18 VSS[249] VSS[366] V45
L_CTRL_DATA 3 2 G23 V48
+5V_RUN VSS[250] VSS[367]
G27 VSS[251] VSS[368] V7
G29 VSS[252] VSS[369] V9
A G31 VSS[253] VSS[370] Y15 A
3
R129 Q27 G34 Y17

MMST3904-7-F VSS[254] VSS[371]
[18] INT_DP_HPD_R 2 1 2 G36 VSS[255] VSS[372] Y33
G39 VSS[256] VSS[373] Y35
150K ENVDD R78 2 1 *100K_4_NC G41 Y37
1
INT_DP_HPD VSS[257] VSS[374]

D6 VSS[258] VSS[347] AR8
G43 AR6
R195 R191
G9
VSS[259]
VSS[260]
VSS[348]
VSS[349] BF15 Quanta Computer Inc.
J11 VSS[261] VSS[350] BD15
J13 VSS[262] VSS[351] BF24 PROJECT : D13
*365K/F_NC 10K J16 BD24
VSS[263] VSS[352] Size Document Number Rev
1A
Cougar Point 2/7
http://vinafix.vn
5 4 3 2 1
5 4 3 2 1
f ix
vina C321 18P/50V/_4
Cougar Point (HDA,JTAG,SATA) IRQ_SERIRQ
RP14
1
10K
2
+3.3V_RUN
SATA_DET0# 3 4
1
Y3 U31A
32.768KHZ R219
10M_4 RTC_X1 A19 A37
RTCX1 FWH0 / LAD0 LPC_LAD0 [21,22,23]
A39
4
C319 18P/50V/_4 RTC_X2 FWH1 / LAD1 LPC_LAD1 [21,22,23]
C19 RTCX2 FWH2 / LAD2 C39 LPC_LAD2 [21,22,23]
D
FWH3 / LAD3 C37 LPC_LAD3 [21,22,23] D
RTC_RST# F19
SRTC_RST#
RTCRST#
FWH4 / LFRAME# K40 LPC_LFRAME# [21,22,23]
PCH JTAG Debug (CLG)
A23 SRTCRST#
H40
LPC
RTC
R90 1M_4 SM_INTRUDER# LDRQ0#
+RTC_CELL K22 INTRUDER# LDRQ1# / GPIO23 F37 MP remove(Intel) +3.3V_SUS
PCH_INTVRMEN C21 +3V Y4 IRQ_SERIRQ
INTVRMEN SERIRQ IRQ_SERIRQ [22,23] PCH_JTAG_TMS R98 200_4
PCH_JTAG_TDI R95 200_4
8/1 NO. 16 AN3 SATA_RXN0 [23]
R223 47_4 ACZ_BITCLK_R SATA0RXN PCH_JTAG_TMS R104 1
[29] PCH_AZ_CODEC_BITCLK H35 HDA_BCLK SATA0RXP AN1 SATA_RXP0 [23] 2 100_4
AU3 PCH_JTAG_TDI R97 1 2 100_4
SATA0TXN SATA_TXN0 [23]
ACZ_SYNC_R H37 AU1 PCH_JTAG_TCK R107 51_4
SATA3
HDA_SYNC SATA0TXP SATA_TXP0 [23]
ACZ_SPKR 47P/50V/NPO_4 C784
ACZ_SPKR N1 AN6
EC17
[29] ACZ_SPKR
R216 33_4 ACZ_RST#_R
SPKR SATA1RXN
SATA1RXP AN8 mSATA
[22,29] PCH_AZ_CODEC_RST# F35 HDA_RST# SATA1TXN AR3
*100P_NC AR1
SATA1TXP
[29] PCH_AZ_CODEC_SDIN0 D36 HDA_SDIN0 SATA2RXN AD4

AD2 +3.3V_SUS
SATA2RXP
B36 HDA_SDIN1 SATA2TXN AL3
AL1 PCH_JTAG_TDO R99 200_4
SATA2TXP R105 1
C35 2 100_4
IHDA
HDA_SDIN2
SATA3RXN AD8
A35 HDA_SDIN3 SATA3RXP AD6
R227 1K_4 AG3
[22] PCH_MELOCK SATA3TXN
SATA3TXP AG1
C R222 33_4 ACZ_SDOUT K37 C
[29] PCH_AZ_CODEC_SDOUT
SATA
HDA_SDO
SATA4RXN AE3
AE1 +RTC_CELL
SATA4RXP
K35 HDA_DOCK_EN# / GPIO33 SATA4TXN AH8
SATA4TXP AH6
M35 +3V R100 20K/F_4 RTC_RST#
HDA_DOCK_RST# / GPIO13
AC3
+3V_S5 SATA5RXN
SATA5RXP AC1 R224 20K/F_4 SRTC_RST#
SATA5TXN AJ3
PCH_JTAG_TCK M17 AJ1
T26 JTAG_TCK SATA5TXP C77 C320
PCH_JTAG_TMS M15 AB10
JTAG
T27 JTAG_TMS SATAICOMPO 1U/6.3V_4 1U/6.3V_4
PCH_JTAG_TDI U12 AB12 SATA_COMP R211 37.4/F_4 +1.05V_PCH
T33 JTAG_TDI SATAICOMPI
PCH_JTAG_TDO M12
T28 JTAG_TDO
10/04: NO.7 SATA3RCOMPO AF10
AF12 SATA3_COMP R209 49.9/F_4

C317 22P/50V_4 SATA3COMPI
PCH_SPI_CLK_RAD12 AH4 SATA3_RBIAS R208 750/F_4

[25] PCH_SPI_CLK SPI_CLK SATA3RBIAS
R210 *SJ0402_NC
[25] PCH_SPI_CS0# AB8 SPI_CS0#
AB6 Open-drain output
SPI
SPI_CS1#
SATALED# W10
W8 M2 SATA_DET0#
B [25] PCH_SPI_SI SPI_MOSI SATA0GP / GPIO21 B
Y2 +3VSATA1GP / GPIO19 R1 BBS_BIT0

[25] PCH_SPI_SO SPI_MISO T32
+3V
PCH Strap Table

Pin Name Strap description Sampled Configuration note
0 = Default (weak pull-down 20K)
SPKR No reboot mode setting PWROK 1 = Setting to No-Reboot mode
0 = Default (weak pull-down 20K)
HDA_SDO Flash Descriptor Security PWROK 1 = Override
Del 0510 Remove SPI_MOSI from PCH strapping, HR_C/L_v0.91
A A
INTVRMEN Integrated 1.05V VRM enable ALWAYS Should be always pull-up +RTC_CELL R96 330K_4 PCH_INTVRMEN
1K_4 R89
0 = Support by 1.8V (weak PD) R85 33_4 ACZ_SYNC_R
+3.3V_SUS
HDA_SYNC On-Die PLL VR Volatge Select RSMRST 1 = Support by 1.5V [29] PCH_AZ_CODEC_SYNC
PROJECT : D13
1A
Cougar Point 3/7
1
10 of 41
5 4 3 2 1
x
fiPCI/USBOC# Cougar Point-M (PCI,USB,NVRAM)
in a Pull-up(CLG)
v
U31E
+3.3V_RUN BE3
RN17 RSVD1
RSVD2 BE1
1 2 PCI_PIRQC# BH24 AU8
PCI_PIRQB# TP1 RSVD3
3 4 BK24 TP2 RSVD4 BJ7
5 6 PCI_PIRQD# BH20
PCI_PIRQA# TP3
7 8 BK16 TP4 RSVD5 BA3
BH16 TP5 RSVD6 BH3
10K AN42
RN18 TP6
AN40 TP7 RSVD7 AU6
D 1 2 PCIE_MCARD2_DET# AR40 AW3 D
TP8 RSVD8
3 4 AR42 TP9 RSVD9 AW1
5 6 SATA_ODD_DA# D20 AY6
HDD_FALL_INT1 TP10 RSVD10
7 8 M30 TP11 RSVD11 AY2
E3 TP12 RSVD12 AY4
10K AM4 BC3
TP13 RSVD13
AT4 BC1
RSVD
TP14 RSVD14
AT2 TP15 RSVD15 BG1
AD10 TP16 RSVD16 BG3
B24 TP17 RSVD17 BE6
+3.3V_SUS D24 BH4
RN3 TP18 RSVD18
AD44 TP19 RSVD19 BF7
10 1 USB_OC0# AD46 BJ4
RSVD
USB_OC6# SIO_EXT_W AKE# TP20 RSVD20
9 2 RSVD21 BJ5
USB_OC4# 8 3 USB_OC3# BK6
USB_OC1# USB_OC5# RSVD22
7 4 BJ48 TP21
USB_OC2# 6 5 BL7 AY8
TP22 RSVD23 DF_TVS
W40 TP23 DF_TVS BC7
10KX8 K30 TP24
BH49 TP41 RSVD24 BL5
BB42 TP42
+3.3V_RUN BB6
RSVD25
RN4 BJ25 BD2
REQ1# TP25 RSVD26
1 2 BJ27 TP26 RSVD27 BD4
3 4 PIRQH# BJ31
REQ2# TP27
5 6 BJ29 TP28 RSVD28 BA1
7 8 REQ3# BL25 BF6
TP29 RSVD29
BL27 TP30
C 10K BL31 C
TP31
BL29 TP32 USBP0N F24
BF26 TP33 USBP0P H24
BB28 TP34 USBP1N C25 USBP1- [29]
BF28 TP35 USBP1P A25 USBP1+ [29] USB 2.0
BF30 TP36 USBP2N C27
BD26 TP37 USBP2P A27
AY28 TP38 USBP3N H28
BD28 TP39 USBP3P F28
BD30 TP40 USBP4N M26 USBP4- [21]
USBP4P K26 USBP4+ [21] WLAN
USBP5N D28
USBP5P B28 Pin Name Strap description Sampled Configuration
USBP6N H26
USBP6P F26
PCI_PIRQA#
PCI_PIRQB#
D49 PIRQA# +5V USBP7N D32 Should not be pull-down
C48 PIRQB# +5V B32 GNT2# / GPIO53 ESI strap (Server only) PWROK
PCI
PCI_PIRQC# USBP7P (weak pull-up 10K)

PCI_PIRQD#
C47 PIRQC# +5V USBP8N M28
C45 PIRQD# +5V USBP8P K28
USBP9N C29 0 = "top-block swap" mode
REQ1# G46 +5V A29 GNT3# / GPIO55 Top-Block Swap Override PWROK
USB
REQ2# K44
REQ1# / GPIO50
+5V USBP9P
C31 1 = Default (weak pull-up 10K)
REQ3# REQ2# / GPIO52 USBP10N
F46 REQ3# / GPIO54 +5V USBP10P A31
USBP11N H33
T14 BBS_BIT1 F42 +3V F33
T92 PCIE_MCARD2_DET# GNT1# / GPIO51 USBP11P
H42 GNT2# / GPIO53 +3V USBP12N H30 USBP12- [19]
T89 PCI_GNT3# D44 F30 Camara
GNT3# / GPIO55 USBP12P USBP12+ [19]
USBP13N M33
K33 GNT1# / GPIO51 Boot BIOS Selection 1 [bit-1] PWROK Bit 0 Bit 1 Boot Location
B HDD_FALL_INT1 USBP13P B
A47 PIRQE# / GPIO2 +5V
SATA_ODD_DA# C41 +5V
KB_LED_DET F45 PIRQF# / GPIO3 USB_BIAS R94 22.6/F_4
[24] KB_LED_DET PIRQG# / GPIO4 +5V USBRBIAS# C33 1 1 SPI *
PIRQH# F40 +5V
PIRQH# / GPIO5
GPIO19 Boot BIOS Selection 0 [bit-0] PWROK
USBRBIAS A33 0 0 LPC
T88 PCI_PME# H2 PME#
PLTRST# F7 +3V_S5 C17 USB_OC0# USB_OC0# [29]
[4,20,21,22,23] PLTRST# PLTRST# OC0# / GPIO59
+3V_S5 A17 USB_OC1#
OC1# / GPIO40 USB_OC2#
+3V_S5 OC2# / GPIO41 A13
R220 22_4 CLK_33M_LPC_R G51 +3V_S5 D16 USB_OC3#
[21] CLK_33M_LPC CLKOUT_PCI0 OC3# / GPIO42
E49 +3V_S5 A11 USB_OC4#
R221 22_4 CLK_33M_KBC_R CLKOUT_PCI1 OC4# / GPIO43 USB_OC5#
[22] CLK_33M_KBC H48 CLKOUT_PCI2 +3V_S5 OC5# / GPIO9 B16
R226 22_4 CLK_33M_KBC_R - 500mil J43 +3V_S5 C23 USB_OC6#
[23] CLK_33M_TPM CLKOUT_PCI3 OC6# / GPIO10
R218 22_4 CLK_PCI_FB_R G45 +3V_S5 H15 SIO_EXT_W AKE#
[12] CLK_PCI_FB CLKOUT_PCI4 OC7# / GPIO14 SIO_EXT_W AKE# [22]
EC wake up PCH during S3 mode Default weak pull-up on GNT0/1# (Internal PU)
Add EMC solution

DF_TVS DMI and FDI Tx/Rx
CLK_33M_KBC
CLK_33M_LPC
Termination Voltage PWROK weak pull-down 20kohm
R1961 2 2.2K_4 +1.8V_RUN
A
DF_TVS A
EC5 EC4 CheckList_1.5 p72; HR_v1.5 p476

*10P/50V_4_NC *10P/50V_4_NC

PROJECT : D13
1A
Cougar Point 4/7
1
11 of 41
5 4 3 2 1
f ix
ina
Cougar Point-M (PCI-E,SMBUS,CLK) SMBus/Pull-up(CLG)
v
+3.3V_RUN
For BIOS:
U31B
drop the PCH_SMB_ALERT from touchpad due to
2
4
SMBUS will control it by host notify mechanism
BJ33 RP4
PERN1 PCH_SMB_ALERT# T15
BL33 PERP1 +3V_S5 SMBALERT# / GPIO11 H12 2.2KX2
BB30 PETN1
5
AY30 F17 SMBCLK Q21A
PETP1 SMBCLK DMN66D0LDW -7
1
3
D BJ35 F10 SMBDATA SMBCLK 3 4 D
[21] PCIE_RXN2 PERN2 SMBDATA TP_SCLK [24]
[21] PCIE_RXP2 BL35 PERP2
WLAN C313 0.1U/16V_4 PCIE_TXN2_C BB33
[21] PCIE_TXN2 PETN2
C314 0.1U/16V_4 PCIE_TXP2_C AY33
SMBUS
[21] PCIE_TXP2 PETP2
+3V_S5 SML0ALERT# / GPIO60 H22 DDR_HVREF_RST_PCH [4]
BH36 PERN3
BK36 K12 SML0CLK
PERP3 SML0CLK
2
BF33 Q21B
PETN3 SML0DATA DMN66D0LDW -7
BD33 PETP3 SML0DATA A9
SMBDATA 6 1 TP_SDATA [24]
[20] PCIE_RXN4 BJ37 PERN4
[20] PCIE_RXP4 BL37 PERP4
C312 0.1U/16V_4 PCIE_TXN4_C BD35 +3V_S5 C9 PCH_GPIO74
[20] PCIE_TXN4 PETN4 SML1ALERT# / PCHHOT# / GPIO74
USB3.0 C311 0.1U/16V_4 PCIE_TXP4_C BF35
[20] PCIE_TXP4 PETP4
+3V_S5 D12 SMB_CLK_ME1
PCI-E*
SML1CLK / GPIO58
BJ39 PERN5
BL39 +3V_S5 C11 SMB_DATA_ME1
PERP5 SML1DATA / GPIO75
AY35 PETN5
BB35 +3.3V_SUS
PETP5
BH40 PERN6
BK40
Controller
PERP6
5
BD37 PETN6 CL_CLK1 L3
BF37 Q22A
PETP6 SMB_CLK_ME1 4 3
Link
SMBCLK1 [22]
BJ41 PERN7 CL_DATA1 J1
BL41 PERP7
AY37 DMN66D0LDW -7
PETN7
BB37 PETP7 CL_RST1# M8
C C
BJ43 PERN8
BL43 PERP8
2
AY40 PETN8
BB40 Q22B
PETP8 SMB_DATA_ME1 1 6 SMBDAT1 [22]
+3V_S5 R8 PEG_CLKREQ_GPU#
PEG_A_CLKRQ# / GPIO47
AD48 CLKOUT_PCIE0N
AD50 DMN66D0LDW -7
CLKOUT_PCIE0P
CLKOUT_PEG_A_N AF44
CLOCKS
PCIE_CLK_REQ0# M4 +3V_S5 AF46
PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P
[21] CLK_PCIE_W LANN AE49 CLKOUT_PCIE1N CLKOUT_DMI_N BB24 CLK_CPU_BCLKN [4]

WLAN [21] CLK_PCIE_W LANP AE51 CLKOUT_PCIE1P CLKOUT_DMI_P AY24 CLK_CPU_BCLKP [4]
PCIE_CLK_REQ1# U8 +3V
[21] PCIE_CLK_REQ1# PCIECLKRQ1# / GPIO18
AN10
CLKOUT_DP_N
AN12
CLK_REQ/Strap Pin(CLG)
CLKOUT_DP_P
AD40 CLKOUT_PCIE2N
AD42 +3.3V_SUS
CLKOUT_PCIE2P
CLKIN_DMI_N BD17 CLK_DMIN RN2 10K
PCIE_CLK_REQ2# T4 +3V BF17 R199 10K_4 PCIE_CLK_REQ0# 1 2
PCIECLKRQ2# / GPIO20 CLKIN_DMI_P PCIE_CLK_REQ3# 3 4
PCIE_CLK_REQ4# 5 6
AA49 CLKOUT_PCIE3N CLKIN_GND1_N BB26 CLK_GND1 PCIE_CLK_REQ5# 7 8
AA51 AY26 R198 10K_4
CLKOUT_PCIE3P CLKIN_GND1_P PEG_B_CLKRQ# R77 10K_4
PCIE_CLK_REQ3# B8 +3V_S5
B PCIECLKRQ3# / GPIO25 B
CLKIN_DOT_96N M24 CLK_BUF_DREFCLK PCIE_CLK_REQ6# 1 2
K24 R93 10K_4 PCIE_CLK_REQ7# 3 4
CLKIN_DOT_96P
[20] CLK_PCIE_USB30N Y48 CLKOUT_PCIE4N
USB3.0 Y50 RP11 10K
[20] CLK_PCIE_USB30P CLKOUT_PCIE4P
CLKIN_SATA_N AK8 CLK_BUF_DREFSSCLK
PCIE_CLK_REQ4# M19 +3V_S5 AK6 R207 10K_4 +3.3V_RUN
[20] PCIE_CLK_REQ4# PCIECLKRQ4# / GPIO26 CLKIN_SATA_P
PCIE_CLK_REQ1# 1 2
AB40 J49 CLK_PCH_14M R106 10K_4 PCIE_CLK_REQ2# 3 4
CLKOUT_PCIE5N REFCLK14IN
AB42 CLKOUT_PCIE5P RP15 10K +3.3V_SUS
PCIE_CLK_REQ5# K8 +3V_S5 E51 CLK_PCI_FB
PCIECLKRQ5# / GPIO44 CLKIN_PCILOOPBACK CLK_PCI_FB [11]
PEG_CLKREQ_GPU# R92 10K_4
AF40 CLKOUT_PEG_B_N XTAL25_IN W49 XTAL25_IN Y2

AF42 CLKOUT_PEG_B_P XTAL25_OUT W51 XTAL25_OUT R113
1M_4 1 3 +3.3V_SUS
PEG_B_CLKRQ# RP13 10K
C4 PEG_B_CLKRQ# / GPIO56 +3V_S5 2 4
PCH_GPIO74 1 2
XCLK_RCOMP AC49 XCLK_RCOMP R117 90.9/F_4 +1.05V_PCH C102
25MHz
C84 PCH_SMB_ALERT# 3 4
AB44 12P/50V_4 12P/50V_4
CLKOUT_PCIE6N RP8 2.2KX2
AB46 CLKOUT_PCIE6P SMBCLK 1 2
PCIE_CLK_REQ6# J3 +3V_S5 SMBDATA 3 4
PCIECLKRQ6# / GPIO45
W44 CLKOUT_PCIE7N +3V CLKOUTFLEX0 / GPIO64 H50 CLK_FLEX0 T22 RP12 2.2KX2
W46 SML0CLK 1 2
CLKOUT_PCIE7P
FLEX CLOCKS
+3V CLKOUTFLEX1 / GPIO65 D48 CLK_FLEX1 T20 SML0DATA 3 4

A
PCIE_CLK_REQ7# H4 +3V_S5 A
PCIECLKRQ7# / GPIO46
+3V CLKOUTFLEX2 / GPIO66 G49 CLK_FLEX2 T21 RP9 2.2KX2
AR12 SMB_DATA_ME1 1 2
CLKOUT_ITPXDP_N CLK_FLEX3 T24 SMB_CLK_ME1
AR10 CLKOUT_ITPXDP_P +3V CLKOUTFLEX3 / GPIO67 J51 3 4
PROJECT : D13
1A
Cougar Point 5/7
1
12 of 41
5 4 3 2 1
fix Cougar Point (GPIO,VSS_NCTF,RSVD) Pin Name Strap description Sampled Configuration
vina U31F
GPIO28 On-die PLL Voltage Regulator RSMRST# 0 = Disable
1 = Enable (Default)
S_GPIO W1 K42 PCH_GPIO68 T23
BMBUSY# / GPIO0 TACH4 / GPIO68 USB_PS_SELCDP R215 *10K_4_NC
+3V +3V Internal PU
SIO_EXT_SMI# B40 A43 PCH_GPIO69 T17
[22] SIO_EXT_SMI# TACH1 / GPIO1 TACH5 / GPIO69
+3V +3V
PCH_GPIO6 C43 D40 RAM_GPIO70
TACH2 / GPIO6 TACH6 / GPIO70
+3V +3V
SIO_EXT_SCI# A45 A41 RAM_GPIO71
D
[22] SIO_EXT_SCI# TACH3 / GPIO7
+3V +3V
TACH7 / GPIO71 GPIO Pull-up/Pull-down(CLG) D
SMIB# H17
[20] SMIB# GPIO8
+3V_S5
LAN_PHY_PW R_CTRL C5 LAN_PHY_PWR_CTRL / GPIO12 +3.3V_SUS
+3V_S5
HOST_ALERT#1 K6 U3 SIO_A20GATE SIO_A20GATE [22]
GPIO15 A20GATE
+3V_S5
AU12 LAN_PHY_PW R_CTRL R79 10K_4
CPU/MISC
PCH_GPIO16 PECI GPIO57 R76 10K_4
AA3 SATA4GP / GPIO16
+3V U6 SIO_RCIN# SIO_RCIN# [22] SMIB# R82 10K_4
RCIN#
GPIO
B44 TACH0 / GPIO17 PROCPWRGD AU10 H_PW RGOOD [4]
+3V +3.3V_RUN
GPIO22 W3 BC9 PCH_THRMTRIP# R193 390_4 PM_THRMTRIP# [4]
SCLOCK / GPIO22 THRMTRIP# SIO_EXT_SMI# R71 10K_4
+3V
PCIE_MCARD1_DET# K15 R6 SIO_EXT_SCI# R72 10K_4
[21] PCIE_MCARD1_DET# GPIO24 / MEM_LED INIT3_3V#
+3V_S5 The internal pull-up is disabled after PLTRST# deasserts. This signal is intended for CRIT_TEMP_REP# R183 10K_4
ROUSH_PAID_TS_DET# C15 SIO_A20GATE R67 10K_4
GPIO27 Firmware Hub. It can be Leave as "No Connect". (desktop SKUs only) SIO_RCIN# R68 10K_4
DSW
USB_PS_SELCDP G1 HDD_FALL_INT2 R190 *10K_4_NC
[29] USB_PS_SELCDP GPIO28
+3V_S5 AK10 USB_MCARD2_DET# R197 10K_4
USB_MCARD2_DET# TS_VSS1 USB_MCARD1_DET# R182 10K_4
R3 STP_PCI# / GPIO34
+3V AH12 BT_RADIO_DIS# R192 10K_4
USB_MCARD1_DET# TS_VSS2 S_GPIO R185 10K_4
[21] USB_MCARD1_DET# W12 GPIO35
+3V AK12 PCH_GPIO16 R204 10K_4
PCH_GPIO36 TS_VSS3 PCIE_MCARD1_DET# R91 10K_4
W6 SATA2GP / GPIO36
+3V AH10 W LAN_ON/OFF# R201 10K_4
FDI_OVRVLTG TS_VSS4 PCH_GPIO6 R88 10K_4
M6 SATA3GP / GPIO37
+3V U40 PCH_GPIO69 R83 10K_4
C W LAN_ON/OFF# NC_1 C
[21] W LAN_ON/OFF# N3 SLOAD / GPIO38
+3V
BT_RADIO_DIS# U10 PCH_GPIO68 R205 10K_4
[21] BT_RADIO_DIS# SDATAOUT0 / GPIO39
+3V
HDD_FALL_INT2 U1 BL48
SDATAOUT1 / GPIO48 VSS_NCTF_15 ROUSH_PAID_TS_DET# R86 10K_4
+3V
CRIT_TEMP_REP# AA1 BL49
[22] CRIT_TEMP_REP# SATA5GP / GPIO49 VSS_NCTF_16
+3V GPIO22 R212 10K_4
GPIO57 K17 BL51
GPIO57 VSS_NCTF_17
+3V_S5
VSS_NCTF_18 C3
A4 VSS_NCTF_1 VSS_NCTF_19 C49
A48 VSS_NCTF_2 VSS_NCTF_20 C51
A49 VSS_NCTF_3 VSS_NCTF_21 D1
NCTF
A5 D51 +3.3V_SUS
VSS_NCTF_4 VSS_NCTF_22
A51 E1
RAM Vender select
VSS_NCTF_5 VSS_NCTF_23
BH1
RAM_GPIO70
VSS_NCTF_6
BH51 R254 R256
R254(1) R255(0)
VSS_NCTF_7
BJ1
Samsung V
VSS_NCTF_8 *10K_4_NC 10K_4
BJ3
Hynix V
B VSS_NCTF_9 RAM_GPIO70 B
BJ49 VSS_NCTF_10 RAM_GPIO71

BJ51 VSS_NCTF_11 R255 R257
RAM size select
BL1 VSS_NCTF_12 RAM_GPIO71
10K_4 *10K_4_NC
BL3 VSS_NCTF_13 R256(1) R257(0)
BL4 VSS_NCTF_14 2G V
4G V
Reserve (PDC) +3.3V_SUS

FDI_OVRVLTG R111 100K_4
HOST_ALERT#1 R87 1K_4
FDI TERMINATION LOW - Tx, Rx terminated Intel ME Crypto Transport Layer

VOLTAGE OVERRIDE to same voltage Security (TLS) cipher suite
A
Low = Disable (Default) A
High = Enable
+3.3V_RUN
R200 1 2 200K/F_4PCH_GPIO36
MFG-TEST Quanta Computer Inc.
Low = Tx, Rx terminated to PROJECT : D13
DMI TERMINATION same voltage (DC Coupling Mode)
VOLTAGE OVERRIDE (DEFAULT) del 0527 Size Document Number Rev
1A
Cougar Point 6/7
1
13 of 41
5 4 3 2 1
f ix Cougar Point (POWER)
vina COUGAR POINT (POWER) VccADAC =1mA(8mils)

+VCCA_DAC_1_2
+3.3V_RUN VCCDSW3_3 tie to 3.3V_SUS,
when don't support Deep SX VccDSW3_3= 3mA(8mil)
T34
+VCCACLK
U31J
POWER +1.05V_PCH
VccCORE =6A
L4 180ohm/1.5A CP_v1.0 p88
+3.3V_SUS SJ9 1 1 2 2 *SJ0402_NC AC51 VCCACLK VCCIO[29] R23
+1.05V_PCH +1.05V_PCH_VCC U31G POWER C113 10U/6.3V_6
VCCIO[30] R25 C131 *1U/6.3V_4_NC
C103 0.1U/16V_4 C101 0.1U/16V_4 +VCCPDSW R12
SJ19 1 VCCDSW3_3
1 2 2 *SJ1206_NC AB21 VCCCORE[1]
C92 0.01U/25V_4
VCCIO[31] U23
need C126 10U/6.3V_6
AB23 VCCCORE[2] VCCADAC U51
PCH_VCCDSW
AC21 VCCCORE[3] T30 R10 DCPSUSBYP VCCIO[32] U25
1206? AC23 VCCSUS3_3 = 119mA
CRT
D VCCCORE[4] D
C117 1U/6.3V_4 AE21 V50 (15mils)
C124 *1U/6.3V_4_NC VCCCORE[5] VSSADAC +3V_SUS_CLKF33 +3.3V_SUS
AE23 VCCCORE[6] V37 VCC3_3[5]
C114 1U/6.3V_4 AF21 V39
VCCCORE[7] +VCCALVDS +3.3V_RUN VCC3_3[6] +3V_VCCPUSB SJ6
AF23 VCCCORE[8]
VccALVDS=1mA VCCSUS3_3[7] R27 1 1 2 2 *SJ0603_NC
VCC CORE
AG21 VCCCORE[9] (8mils)
AG23 AF33 SJ14 1 2 *SJ0402_NC AW31 R29 C93 0.1U/16V_4
VCCCORE[10] VCCALVDS[1] 1 2 T43 VCCAPLLDMI2 VCCSUS3_3[8]
AG25 VCCCORE[11] VCCALVDS[2] AG33
AG27 AP27 U27
USB
VCCCORE[12] +1.05V_PCH VCCIO[14] VCCSUS3_3[9]
AJ21 SJ7 1 2 *SJ0603_NC
VCCCORE[13] 1 2
AJ23 VCCCORE[14] VSSALVDS[1] AC33 VCCSUS3_3[10] U29
AJ25 AE33 V13 C83 0.1U/16V_4
VCCCORE[15] VSSALVDS[2] +VCC_TX_LVDS +1.8V_RUN DCPSUS[1] +3V_VCCAUBG
AJ27 VCCCORE[16]
VccTX_LVDS=60mA VCCSUS3_3[6] N27
AJ29 (10mils) AR33
LVDS
VCCCORE[17] SJ18 1 +VCCSUS1 DCPSUS[2]
AJ31 VCCCORE[18] VCCTX_LVDS[1] AF37 1 2 2 *SJ_0805_NC T38 AU33 DCPSUS[3]
AK29 VCCCORE[19] VCCIO[34] N18 +1.05V_PCH
AK31 VCCCORE[20] VCCTX_LVDS[2] AG37
AK33 VCCCORE[21] AB27 VCCASW[1]
VCC5REFSUS=1mA(8mil)
AM33 VCCCORE[22] VCCTX_LVDS[3] AG39 C119 10U/6.3V_6 need Indutor? VccASW =1.01A V5REF_SUS M37 +5V_PCH_VCC5REFSUS R108 10/F_4 +5V_SUS
AM35 C116 0.01U/25V_4 (50mils) AB29
VCCCORE[23] C120 0.01U/25V_4 VCCASW[2] D19 SDM10K45-7-F +3.3V_SUS
AJ37
Clock and Miscellaneous

VCCTX_LVDS[4] +VCCA_USBSUS
VccIO =2.925 A(120mils) +1.05V_PCH AB31 VCCASW[3] DCPSUS[4] AU31
+1.05V_PCH AM21 C80 0.1U/16V_4
VCCIO[28] C97 10U/6.3V_6 +3V_VCCPSUS
AC27 VCCASW[4] VCCSUS3_3[1] AM27
+3V_VCC_GIO +3.3V_RUN C115 10U/6.3V_6
AP19 Vcc3_3 = 0.266A AC29 T41
T40 VCCAPLLEXP VCCASW[5]
T39 SJ8 1 2 *SJ0603_NC (15mils) C107 1U/6.3V_4
HVCMOS VCC3_3[6] 1 2 C106 1U/6.3V_4 AC31 V5REF= 1mA(8mil)
VCCASW[6]
AR15 VCCIO[15]
C89 0.1U/16V_4 C94 1U/6.3V_4
V5REF N36 +5V_PCH_VCC5REF R103 10/F_4 +5V_RUN
AE27 VCCASW[7]
+1.05V_PCH AT13 U37 Change 22U/6.3V_8 to 10U/6.3V_6 for package D20 SDM10K45-7-F +3.3V_RUN
VCCIO[16] VCC3_3[7]
AE29 R33
PCI/GPIO/LPC
VCCASW[8] VCCSUS3_3[2] C81 1U/6.3V_4 VCCSUS3_3 =
C118 1U/6.3V_4 AR23 AE31 R35 119mA (15mils)
VCCIO[17] +VCCAFDI_VRM VCCASW[9] VCCSUS3_3[3]
C109 *1U/6.3V_4_NC
+VCCAFDI_VRM 01/26 power rail for VCCIO +3V_VCCPSUS SJ4
AR25 VCCIO[18] U21 VCCASW[10] VCCSUS3_3[4] U33 1 1 2 2 *SJ0603_NC+3.3V_SUS
C C
VCCVRM[3] AU21
C130 *1U/6.3V_4_NC AR27 AW21 V21 U35 C90 1U/6.3V_4
VCCIO[19] VCCVRM[4] VCCASW[11] VCCSUS3_3[5]
C95 1U/6.3V_4 AR29 +1.1V_VCC_DMI +1.05V_PCH V23 VCCPCORE = 28mA(10mils)
VCCIO[20] VCCASW[12] +3V_VCCPCORE SJ13 1
VCCDMI[1] AM23 VccDMI = 80mA
VCC3_3[1] AB19 1 2 2 *SJ0603_NC+3.3V_RUN
AU23 SJ21 1 2 *SJ0402_NC (10mils) V25
DMI
VCCIO[21] 1 2 VCCASW[13] C112 0.1U/16V_4

Near to AN16, AP21, AN33 AC19
VCCIO
C123 1U/6.3V_4 VCC3_3[8]

AU25 VCCIO[22] Y21 VCCASW[14]
VCC3_3[4] R40 +3.3V_RUN
AU27 AP39 +1.1V_VCC_DMI_CCI +1.05V_PCH Y23 C87 0.1U/16V_4
VCCIO[23] VCCCLKDMI VCCASW[15]
VccCLKDMI = 20mA
AU29 L5 10uH_6 (8mils) Y25
VCCIO[24] VCCASW[16]
C128 1U/6.3V_4
AU35
09/28: NO.3 Y27 VCCASW[17]
AF6
+3.3V_RUN +3V_VCC_EXP VCCIO[25] VCC3_3[2] +3.3V_RUN
AJ13 Y29 C88 0.1U/16V_4
VccDFTERM[1] VCCASW[18]
AW34 VCCIO[26]
SJ23 1 2 *SJ0603_NC Y31 AA13
NAND / SPI
1 2 VCCASW[19] VCCIO[5]
VccDFTERM[2] AJ15
C139 0.1U/16V_4 BK28 +VCCP_NAND +1.8V_RUN VCCPNAND = 190 mA(15mils)
VCC3_3[3] C100 0.1U/16V_4 +VCCRTCEXT R15 DCPRTC[1] VCCIO[12] AG13 +1.05V_PCH
VccVRM(1.5V) =0.16 A(10mils) AK15 SJ20 1 2 *SJ0805_NC U15
VccDFTERM[3] 1 2 DCPRTC[2] C132 *1U/6.3V_4_NC
VCCIO[13] AG15
+VCCAFDI_VRM AU19 C122 0.1U/16V_4
+VCCAFDI_VRM VCCVRM[5]
AW18 AL13 +VCCAFDI_VRM +VCCAFDI_VRM AC39
T42 VCCVRM[6] VccDFTERM[4] VCCVRM[4]
VCCIO[6] AF15
SATA
+1.05V_PCH AM2 +V1.1LAN_VCCAPLL T83
T39 AP13 VCCAFDPLL[1] +3V_VCCME_SPI +3.3V_RUN
Intel +1.05V_VCCA_A_DPL VCCAPLLSATA
AP15 VCCAFDPLL[2]
80mA(10mils) BF40 VCCADPLLA
VCCSPI = 20mA(8mils) SJ17 1 2 *SJ0603_NC
1 2
FDI
+1.05V_PCH AK21 Y19 SJ12 1 2 *SJ0603_NC +1.05V_VCCA_B_DPL BD40 AE19 +VCCAFDI_VRM

VCCIO[27] VCCSPI 1 2 C121 1U/6.3V_4 VCCADPLLB VCCVRM[1]
80mA(10mils) VCCVRM[2] AF17 VCCVRM= 114mA(15mils)
VccDMI =0.042 A(10mils) C108 1U/6.3V_4
AU15 +VCCDIFFCLK AJ17
+1.1V_VCC_DMI VCCDMI[2] VCCIO[7]
AW16 SJ15 1 2 *SJ0603_NC +VCCDIFFCLKN AC37 AB15
B
T44 VCCDMI[3] 1 2 VCCDIFFCLKN[1] VCCIO[2]
VCCDIFFCLKN= AE37 VCCDIFFCLKN[2]
B
C110 1U/6.3V_4 55mA(18mils,PDDG) AE39 AC13 +1.05V_PCH
CougarPoint-H_SFF_Rev_1_0 VCCDIFFCLKN[3] VCCIO[3]
AC15 C129 *1U/6.3V_4_NC
+VCCAFDI_VRM SJ11 1 VCCIO[4]
1 2 2 *SJ0603_NC +V1.05V_SSCVCC AC35 VCCSSC
VCCSSC= 95mA(10mils)
C111 1U/6.3V_4
C99 0.1U/16V_4 +VCCSST U17
SJ16 1 DCPSST
+1.5V_RUN 1 2 2 *SJ0603_NC VCCASW[22] U19 +1.05V_PCH
FUSE
VCCASW[23] R19
VCCSUSHDA= 10mA(8mils)
CPU
1mA(8mils) +1.05V_PCH SJ22 1 2 +VTT_VCCPCPU AM17
*SJ0402_NC
1 2
C135 4.7U/6.3V_4 V_PROC_IO
VCCASW[21] V19
C125 0.1U/16V_4
C127 *0.1U/10V/X7R_4_NC
RTC
N16 V31 +V3.3A_1.5A_HDA_IO SJ5 1 2 *SJ0402_NC
HDA
+RTC_CELL VCCRTC VCCSUSHDA 1 2 +3.3V_SUS
C82 1U/6.3V_4
C75 *0.1U/10V/X7R_4_NC C91 0.1U/16V_4
VCCRTC<1mA(8mils) C86 0.1U/16V_4 CougarPoint-H_SFF_Rev_1_0
+3.3V_RUN
+1.05V_PCH L7 10uH_6 +1.05V_VCCA_A_DPL
C137 SJ10 1 +3V_SUS_CLKF33_L

2 *SJ0402_NC L3 10uH_6 +3V_SUS_CLKF33
C138 1U/6.3V_4 1 2
A 10U/6.3V_6 A
C105 C104
09/28: NO.3 10U/6.3V_6 1U/6.3V_4
L6 10uH_6 +1.05V_VCCA_B_DPL
C134
C133 1U/6.3V_4
09/28: NO.3 10U/6.3V_6

PROJECT : D13
1A
Cougar Point 7/7
5 4
http://vinafix.vn 3 2
1
Sheet 14 of 41
5 4 3 2 1
f ix
CHANNEL A: SINGLE RANK 256Mb*8 DDR3 M_A_DQ[63..0] [5] M_A_DQSP[7..0] [5] M_A_DQSN[7..0] [5]
ina
[5] M_A_DQ[16..23] U15
[5] M_A_DQ[32..39] U16 M_A_DQ20 E7
U13 U19 DQ7
[5] M_A_DQ[0..7] [5] M_A_DQ[56..63] M_A_DQ37 E7 M_A_DQ21 D2
M_A_DQ63 DQ7 DQ6
v
M_A_DQ5 E7 E7 DQ7 M_A_DQ36 M_A_DQ16
DQ7 M_A_DQ56 D2 DQ6 E8 DQ5
M_A_DQ0 D2 D2 DQ6 M_A_DQ33 M_A_DQ17
DQ6 M_A_DQ62 E8 DQ5 E3 DQ4
M_A_DQ1 E8 E8
Samsung M_A_DQ4 E3
DQ5
DQ4
M_A_DQ57
M_A_DQ58
E3
DQ5
DQ4
M_A_DQ32
M_A_DQ35
E3
C8
DQ4
DQ3 VREFCA J8 +SMDDR_VREF_DIMMA
M_A_DQ19
M_A_DQ23
C8
C2
DQ3
DQ2
VREFCA
VREFDQ
J8
E1
+SMDDR_VREF_DIMMA
+SMDDR_VREF_DQA
M_A_DQ2 C8 J8 +SMDDR_VREF_DIMMA
C8 DQ3 VREFCA J8 +SMDDR_VREF_DIMMA M_A_DQ34 M_A_DQ22
C2 E1 C7
2G D-die M_A_DQ3
M_A_DQ6
C2
C7
DQ3
DQ2
VREFCA
VREFDQ E1 +SMDDR_VREF_DQA
M_A_DQ61
M_A_DQ59
C2
C7
DQ2 VREFDQ E1 +SMDDR_VREF_DQA M_A_DQ38 C7
DQ2
DQ1
VREFDQ +SMDDR_VREF_DQA
M_A_DQ18 B3
DQ1
DQ0
DQ1 DQ1 M_A_DQ39 B3 A2 +1.5V_SUS
M_A_DQ7 B3 M_A_DQ60 B3 DQ0 VDD
DQ0 DQ0 A2 +1.5V_SUS F1 A9
A2 A2 +1.5V_SUS VDD NC VDD
VDD +1.5V_SUS VDD F1 A9 [5,17] M_A_ODT0 G1 D7
F1 A9 F1 A9 NC VDD ODT0 VDD
NC VDD NC VDD [5,17] M_A_ODT0 G1 D7 G2
G1 D7 [5,17] M_A_ODT0 G1 D7 ODT0 VDD VDD
[5,17] M_A_ODT0 ODT0 VDD ODT0 VDD G2 [5,17] M_A_RAS# F3 G8
G2 G2 VDD RAS VDD
VDD VDD [5,17] M_A_RAS# F3 G8 [5,17] M_A_CAS# G3 K1
D F3 G8 [5,17] M_A_RAS# F3 G8 RAS VDD CAS VDD D
[5,17] M_A_RAS# RAS VDD RAS VDD [5,17] M_A_CAS# G3 K1 K9
G3 K1 [5,17] M_A_CAS# G3 K1 CAS VDD VDD
[5,17] M_A_CAS# CAS VDD CAS VDD K9 [5,17] M_A_CLKP0 F7 M1
K9 K9 VDD CK VDD
VDD VDD [5,17] M_A_CLKP0 F7 M1 [5,17] M_A_CLKN0 G7 M9
F7 M1 [5,17] M_A_CLKP0 F7 M1 CK VDD CK VDD
[5,17] M_A_CLKP0 CK VDD CK VDD [5,17] M_A_CLKN0 G7 M9
G7 M9 [5,17] M_A_CLKN0 G7 M9 CK VDD
[5,17] M_A_CLKN0 CK VDD CK VDD [5] M_A_DQSP2 C3 B9
DQS VDDQ
[5] M_A_DQSP4 C3 DQS VDDQ B9 [5] M_A_DQSN2 D3 DQS VDDQ C1
C3 B9 [5] M_A_DQSP7 C3 DQS VDDQ B9
[5] M_A_DQSP0 DQS VDDQ [5] M_A_DQSN4 D3 DQS VDDQ C1 VDDQ E2
D3 C1 [5] M_A_DQSN7 D3 DQS VDDQ C1
[5] M_A_DQSN0 DQS VDDQ VDDQ E2 F9 NC VDDQ E9
E2 VDDQ E2
VDDQ F9 NC VDDQ E9 [5,17] M_A_CKE0 G9 CKE0
F9 E9 F9 NC VDDQ E9
NC VDDQ [5,17] M_A_CKE0 G9 CKE0
G9 [5,17] M_A_CKE0 G9 CKE0
[5,17] M_A_CKE0 CKE0 A7 NU/TDQS
A7 NU/TDQS B7 DM/TDQS
A7 A7 NU/TDQS
NU/TDQS B7 DM/TDQS
B7 B7 DM/TDQS
DM/TDQS H9 ZQ1
5/13 NO. 37 H9 H9 ZQ1 1R147 240/F_4
2
H9
H8
ZQ1
A1 [5,17] M_A_A[14..0]
1R144 240/F_4
2 H8 ZQ0 VSS A1
A8
ZQ1 1R156 240/F_4
2 H8 A1 ZQ0 VSS VSS
1R136 240/F_4
2 H8 ZQ0 VSS A1 ZQ0 VSS [5,17] M_A_A[14..0] A8 M_A_A14 N7 B1
A8 A8 M_A_A14 VSS M_A_A13 A14 VSS
[5,17] M_A_A[14..0] VSS [5,17] M_A_A[14..0] M_A_A14 VSS N7 B1 N3 J1
M_A_A14 N7 B1 N7 B1 M_A_A13 A14 VSS M_A_A12 A13 VSS
A14 VSS M_A_A13 A14 VSS N3 J1 K7 L1
M_A_A13 N3 J1 N3 J1 M_A_A12 A13 VSS M_A_A11 A12/BC VSS
A13 VSS M_A_A12 A13 VSS K7 L1 M7 N1
M_A_A12 K7 L1 K7 L1 M_A_A11 A12/BC VSS M_A_A10 A11 VSS
A12/BC VSS M_A_A11 A12/BC VSS M7 N1 H7 D8
M_A_A11 M7 N1 M7 N1 M_A_A10 A11 VSS M_A_A9 A10/AP VSS
A11 VSS M_A_A10 A11 VSS H7 D8 M3 F2
M_A_A10 H7 D8 H7 D8 M_A_A9 A10/AP VSS M_A_A8 A9 VSS
A10/AP VSS M_A_A9 A10/AP VSS M3 F2 N8 J9
M_A_A9 M3 F2 M3 F2 M_A_A8 A9 VSS M_A_A7 A8 VSS
A9 VSS M_A_A8 A9 VSS N8 J9 M2 L9
M_A_A8 N8 J9 N8 J9 M_A_A7 A8 VSS M_A_A6 A7 VSS
A8 VSS M_A_A7 A8 VSS M2 L9 M8 N9
M_A_A7 M2 L9 M2 L9 M_A_A6 A7 VSS M_A_A5 A6 VSS
A7 VSS M_A_A6 A7 VSS M8 N9 L2 F8
M_A_A6 M8 N9 M8 N9 M_A_A5 A6 VSS M_A_A4 A5 VSS
A6 VSS M_A_A5 A6 VSS L2 F8 L8
M_A_A5 L2 F8 L2 F8 M_A_A4 A5 VSS M_A_A3 A4
A5 VSS M_A_A4 A5 VSS L8 K2 D1
M_A_A4 L8 L8 M_A_A3 A4 M_A_A2 A3 VSSQ
A4 M_A_A3 A4 K2 D1 L3 B2
M_A_A3 K2 D1 K2 D1 M_A_A2 A3 VSSQ M_A_A1 A2 VSSQ
A3 VSSQ M_A_A2 A3 VSSQ L3 B2 L7 B8
M_A_A2 L3 B2 L3 B2 M_A_A1 A2 VSSQ M_A_A0 A1 VSSQ
A2 VSSQ M_A_A1 A2 VSSQ L7 B8 K3 C9
M_A_A1 L7 B8 L7 B8 M_A_A0 A1 VSSQ A0 VSSQ
A1 VSSQ M_A_A0 A1 VSSQ K3 C9 D9
M_A_A0 K3 C9 K3 C9 A0 VSSQ VSSQ
A0 VSSQ A0 VSSQ D9 H1
D9 D9 VSSQ NC
VSSQ VSSQ H1 [5,17] M_A_CS#0 H2
H1 H1 NC CS0
C NC NC [5,17] M_A_CS#0 H2 C
H2 [5,17] M_A_CS#0 H2 CS0
[5,17] M_A_CS#0 CS0 CS0 [5,17] M_A_BS2 J3 BA2
[5,17] M_A_BS2 J3 BA2 [5,17] M_A_BS1 K8 BA1
J3 [5,17] M_A_BS2 J3 BA2
[5,17] M_A_BS2 BA2 [5,17] M_A_BS1 K8 BA1 [5,17] M_A_BS0 J2 BA0
K8 [5,17] M_A_BS1 K8 BA1
[5,17] M_A_BS1 BA1 [5,17] M_A_BS0 J2 BA0 NC1 A3
J2 [5,17] M_A_BS0 J2 BA0
[5,17] M_A_BS0 BA0 NC1 A3 [5,17] M_A_WE# H3 WE NC2 J7
A3 NC1 A3
NC1 [5,17] M_A_WE# H3 WE NC2 J7 [4,16] DDR3_DRAMRST# N2 RESET
H3 J7 [5,17] M_A_WE# H3 WE NC2 J7
[5,17] M_A_WE# WE NC2 [4,16] DDR3_DRAMRST# N2 RESET
N2 [4,16] DDR3_DRAMRST# N2 RESET
[4,16] DDR3_DRAMRST# RESET
DDR3
DDR3
DDR3 DDR3
[5] M_A_DQ[24..31] U22 [5] M_A_DQ[8..15] U24
[5] M_A_DQ[40..47] U20 [5] M_A_DQ[48..55] U17 M_A_DQ29 E7 M_A_DQ14 E7
M_A_DQ42 E7 DQ7 DQ7
DQ7 M_A_DQ52 E7 M_A_DQ30 D2 M_A_DQ9 D2
M_A_DQ41 D2 DQ7 DQ6 DQ6
DQ6 M_A_DQ49 D2 M_A_DQ27 E8 M_A_DQ15 E8
M_A_DQ47 E8 DQ6 DQ5 DQ5
DQ5 M_A_DQ50 E8 M_A_DQ28 E3 M_A_DQ8 E3
M_A_DQ44 E3 DQ5 DQ4 DQ4
DQ4 M_A_DQ48 E3 M_A_DQ25 C8 J8 +SMDDR_VREF_DIMMA M_A_DQ11 C8 J8 +SMDDR_VREF_DIMMA
M_A_DQ43 C8 J8 DQ4 DQ3 VREFCA DQ3 VREFCA
DQ3 VREFCA +SMDDR_VREF_DIMMA M_A_DQ54 C8 J8 M_A_DQ31 C2 E1 M_A_DQ13 C2 E1
M_A_DQ40 C2 E1 DQ3 VREFCA +SMDDR_VREF_DIMMA DQ2 VREFDQ +SMDDR_VREF_DQA DQ2 VREFDQ +SMDDR_VREF_DQA
DQ2 VREFDQ +SMDDR_VREF_DQA M_A_DQ53 C2 E1 M_A_DQ26 C7 M_A_DQ10 C7
M_A_DQ46 C7 DQ2 VREFDQ +SMDDR_VREF_DQA DQ1 DQ1
DQ1 M_A_DQ51 C7 M_A_DQ24 B3 M_A_DQ12 B3
M_A_DQ45 B3 DQ1 DQ0 DQ0
DQ0 M_A_DQ55 B3 A2 +1.5V_SUS A2 +1.5V_SUS
A2 +1.5V_SUS DQ0 VDD VDD
VDD A2 +1.5V_SUS F1 A9 F1 A9
F1 A9 VDD NC VDD NC VDD
NC VDD F1 A9 [5,17] M_A_ODT0 G1 D7 [5,17] M_A_ODT0 G1 D7
[5,17] M_A_ODT0 G1 D7 NC VDD ODT0 VDD ODT0 VDD
ODT0 VDD [5,17] M_A_ODT0 G1 D7 G2 G2
G2 ODT0 VDD VDD VDD
VDD G2 [5,17] M_A_RAS# F3 G8 [5,17] M_A_RAS# F3 G8
[5,17] M_A_RAS# F3 G8 VDD RAS VDD RAS VDD
RAS VDD [5,17] M_A_RAS# F3 G8 [5,17] M_A_CAS# G3 K1 [5,17] M_A_CAS# G3 K1
[5,17] M_A_CAS# G3 K1 RAS VDD CAS VDD CAS VDD
CAS VDD [5,17] M_A_CAS# G3 K1 K9 K9
K9 CAS VDD VDD VDD
VDD K9 [5,17] M_A_CLKP0 F7 M1 [5,17] M_A_CLKP0 F7 M1
[5,17] M_A_CLKP0 F7 M1 VDD CK VDD CK VDD
CK VDD [5,17] M_A_CLKP0 F7 M1 [5,17] M_A_CLKN0 G7 M9 [5,17] M_A_CLKN0 G7 M9
[5,17] M_A_CLKN0 G7 M9 CK VDD CK VDD CK VDD
CK VDD [5,17] M_A_CLKN0 G7 M9
CK VDD
[5] M_A_DQSP3 C3 DQS VDDQ B9 [5] M_A_DQSP1 C3 DQS VDDQ B9
[5] M_A_DQSP5 C3 DQS VDDQ B9
[5] M_A_DQSP6 C3 DQS VDDQ B9 [5] M_A_DQSN3 D3 DQS VDDQ C1 [5] M_A_DQSN1 D3 DQS VDDQ C1
[5] M_A_DQSN5 D3 DQS VDDQ C1
[5] M_A_DQSN6 D3 DQS VDDQ C1 VDDQ E2 VDDQ E2
VDDQ E2
B VDDQ E2 F9 NC VDDQ E9 F9 NC VDDQ E9 B
F9 NC VDDQ E9
F9 NC VDDQ E9 [5,17] M_A_CKE0 G9 CKE0 [5,17] M_A_CKE0 G9 CKE0
[5,17] M_A_CKE0 G9 CKE0 [5,17] M_A_CKE0 G9 CKE0
A7 NU/TDQS A7 NU/TDQS
A7 NU/TDQS A7 NU/TDQS B7 DM/TDQS B7 DM/TDQS
B7 DM/TDQS B7 DM/TDQS
H9 ZQ1 H9 ZQ1
H9 ZQ1 H9 1R158 240/F_4
2 H8 A1 1R161 240/F_4
2 H8 A1
1R157 240/F_4
2 H8 A1 ZQ1 [5,17] M_A_A[14..0] ZQ0 VSS [5,17] M_A_A[14..0] ZQ0 VSS
[5,17] M_A_A[14..0]
ZQ0 VSS
[5,17] M_A_A[14..0]
1R148 240/F_4
2 H8 ZQ0 VSS A1 VSS A8 VSS A8
VSS A8 M_A_A14 M_A_A14
M_A_A14 VSS A8 N7 A14 VSS B1 N7 A14 VSS B1
N7 A14 VSS B1 M_A_A14 M_A_A13 M_A_A13
M_A_A13 N7 A14 VSS B1 N3 A13 VSS J1 N3 A13 VSS J1
N3 A13 VSS J1 M_A_A13 M_A_A12 M_A_A12
M_A_A12 N3 A13 VSS J1 K7 A12/BC VSS L1 K7 A12/BC VSS L1
K7 A12/BC VSS L1 M_A_A12 M_A_A11 M_A_A11
M_A_A11 K7 A12/BC VSS L1 M7 A11 VSS N1 M7 A11 VSS N1
M7 A11 VSS N1 M_A_A11 M_A_A10 M_A_A10
M_A_A10 M7 A11 VSS N1 H7 A10/AP VSS D8 H7 A10/AP VSS D8
H7 A10/AP VSS D8 M_A_A10 M_A_A9 M_A_A9
M_A_A9 H7 A10/AP VSS D8 M3 A9 VSS F2 M3 A9 VSS F2
M3 A9 VSS F2 M_A_A9 M_A_A8 M_A_A8
M_A_A8 M3 A9 VSS F2 N8 A8 VSS J9 N8 A8 VSS J9
N8 A8 VSS J9 M_A_A8 M_A_A7 M_A_A7
M_A_A7 N8 A8 VSS J9 M2 A7 VSS L9 M2 A7 VSS L9
M2 A7 VSS L9 M_A_A7 M_A_A6 M_A_A6
M_A_A6 M2 A7 VSS L9 M8 A6 VSS N9 M8 A6 VSS N9
M8 A6 VSS N9 M_A_A6 M_A_A5 M_A_A5
M_A_A5 M8 A6 VSS N9 L2 A5 VSS F8 L2 A5 VSS F8
L2 A5 VSS F8 M_A_A5 M_A_A4 M_A_A4
M_A_A4 L2 A5 VSS F8 L8 A4 L8 A4
L8 A4 M_A_A4 M_A_A3 M_A_A3
M_A_A3 L8 A4 K2 A3 VSSQ D1 K2 A3 VSSQ D1
K2 A3 VSSQ D1 M_A_A3 M_A_A2 M_A_A2
M_A_A2 K2 A3 VSSQ D1 L3 A2 VSSQ B2 L3 A2 VSSQ B2
L3 A2 VSSQ B2 M_A_A2 M_A_A1 M_A_A1
M_A_A1 L3 A2 VSSQ B2 L7 A1 VSSQ B8 L7 A1 VSSQ B8
L7 A1 VSSQ B8 M_A_A1 M_A_A0 M_A_A0
M_A_A0 L7 A1 VSSQ B8 K3 A0 VSSQ C9 K3 A0 VSSQ C9
K3 A0 VSSQ C9 M_A_A0 K3 A0 VSSQ C9 VSSQ D9 VSSQ D9
VSSQ D9
VSSQ D9 H1 NC H1 NC
H1 NC H1 NC [5,17] M_A_CS#0 H2 CS0 [5,17] M_A_CS#0 H2 CS0
[5,17] M_A_CS#0 H2 CS0 [5,17] M_A_CS#0 H2 CS0
[5,17] M_A_BS2 J3 BA2 [5,17] M_A_BS2 J3 BA2
[5,17] M_A_BS2 J3 BA2 [5,17] M_A_BS2 J3 BA2 [5,17] M_A_BS1 K8 BA1 [5,17] M_A_BS1 K8 BA1
[5,17] M_A_BS1 K8 BA1 [5,17] M_A_BS1 K8 BA1 [5,17] M_A_BS0 J2 BA0 [5,17] M_A_BS0 J2 BA0
[5,17] M_A_BS0 J2 BA0 [5,17] M_A_BS0 J2 BA0 NC1 A3 NC1 A3
NC1 A3
NC1 A3 [5,17] M_A_WE# H3 WE NC2 J7 [5,17] M_A_WE# H3 WE NC2 J7
[5,17] M_A_WE# H3 WE NC2 J7
[5,17] M_A_WE# H3 WE NC2 J7 [4,16] DDR3_DRAMRST# N2 RESET [4,16] DDR3_DRAMRST# N2 RESET
[4,16] DDR3_DRAMRST# N2 RESET [4,16] DDR3_DRAMRST# N2 RESET
A A
+1.5V_SUS +1.5V_SUS DDR3 DDR3
DDR3
+1.5V_SUS
+1.5V_SUS
DDR3 M1 VREF Separate from
R155
R133
1K/F_4
1K/F_4 DIMM-A and
+SMDDR_VREF_DQA
DIMM-B
1
+SMDDR_VREF_DIMMA
1
C305 C316 C315 C303 C278 C266 C199 C282

C270 C253 C267 C292 C289 C279 1U/6.3V_4 *1U/6.3V_4_NC
1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_41U/6.3V_4 Quanta Computer Inc.
2
10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6

1
R132 C275
2
R150
1K/F_4 C208
1K/F_4
PROJECT : D13
0.1U/16V_4 0.1U/16V_4 Size Document Number Rev
2
16 16 1A
Dan0406:remove 2 extra 10U decoupling. DDR3 1/2
5 4 3 2 1
http://vinafix.vn
5 4 3 2 1
f ix
CHANNEL B: SINGLE RANK 256Mb*8 DDR3 M_B_DQ[63..0] [5] M_B_DQSN[7..0] [5] M_B_DQSP[7..0] [5] [5] M_B_DQ[16..23] U9
ina
[5] M_B_DQ[32..39] U11 M_B_DQ21 E7
U8 U26 M_B_DQ22 DQ7
[5] M_B_DQ[0..7] [5] M_B_DQ[56..63] M_B_DQ37 E7 D2 DQ6
M_B_DQ6 E7 M_B_DQ63 E7 DQ7 M_B_DQ17 E8
DQ7 M_B_DQ38
M_B_DQ5 M_B_DQ57 D2 DQ7 D2 DQ6 DQ5
v
D2 DQ6 M_B_DQ36 M_B_DQ19 E3
M_B_DQ3 E8 M_B_DQ59 E8 DQ6 E8 DQ5 M_B_DQ20 C8
DQ4
J8
Samsung M_B_DQ4
M_B_DQ7
E3
DQ5
DQ4
M_B_DQ58 E3 DQ5
M_B_DQ56 C8 DQ4
M_B_DQ34
M_B_DQ32
E3
C8
DQ4
DQ3 VREFCA J8 +SMDDR_VREF_DIMMB
M_B_DQ23 C2
DQ3
DQ2
VREFCA
VREFDQ E1
+SMDDR_VREF_DIMMB
+SMDDR_VREF_DQB
C8 DQ3 VREFCA J8 +SMDDR_VREF_DIMMB J8 +SMDDR_VREF_DIMMB M_B_DQ35 M_B_DQ16 C7
M_B_DQ62 C2 DQ3 VREFCA C2 E1
2G D-die M_B_DQ0
M_B_DQ2
C2
C7
DQ2 VREFDQ E1 +SMDDR_VREF_DQB
M_B_DQ61 C7 DQ2 VREFDQ E1 +SMDDR_VREF_DQB M_B_DQ33
M_B_DQ39
C7
DQ2
DQ1
VREFDQ +SMDDR_VREF_DQB M_B_DQ18 B3
DQ1
DQ0
A2 +1.5V_SUS
M_B_DQ1 DQ1 M_B_DQ60 B3 DQ1 B3 VDD
B3 DQ0 F1 A9
DQ0 DQ0 A2 +1.5V_SUS NC VDD
A2 +1.5V_SUS A2 +1.5V_SUS VDD G1 D7
VDD VDD F1 A9 [5,17] M_B_ODT0 ODT0 VDD
F1 A9 F1 A9 NC VDD G2
NC VDD NC VDD [5,17] M_B_ODT0 G1 D7 VDD
[5,17] M_B_ODT0 G1 D7 [5,17] M_B_ODT0 G1 D7 ODT0 VDD F3 G8
ODT0 VDD ODT0 VDD G2 [5,17] M_B_RAS# RAS VDD
G2 G2 VDD G3 K1
VDD VDD [5,17] M_B_RAS# F3 G8 [5,17] M_B_CAS# CAS VDD
[5,17] M_B_RAS# F3 G8 [5,17] M_B_RAS# F3 G8 RAS VDD K9
RAS VDD RAS VDD [5,17] M_B_CAS# G3 K1 VDD
D [5,17] M_B_CAS# G3 K1 [5,17] M_B_CAS# G3 K1 CAS VDD F7 M1 D
CAS VDD CAS VDD K9 [5,17] M_B_CLKP0 CK VDD
K9 K9 VDD G7 M9
VDD VDD [5,17] M_B_CLKP0 F7 M1 [5,17] M_B_CLKN0 CK VDD
[5,17] M_B_CLKP0 F7 M1 [5,17] M_B_CLKP0 F7 M1 CK VDD
CK VDD CK VDD [5,17] M_B_CLKN0 G7 M9
[5,17] M_B_CLKN0 G7 M9 [5,17] M_B_CLKN0 G7 M9 CK VDD C3 B9
CK VDD CK VDD [5] M_B_DQSP2 DQS VDDQ
C3 B9 [5] M_B_DQSN2 D3 DQS VDDQ C1
C3 B9 C3 B9 [5] M_B_DQSP4 DQS VDDQ E2
[5] M_B_DQSP0 DQS VDDQ [5] M_B_DQSP7 DQS VDDQ D3 C1 VDDQ
D3 C1 D3 C1 [5] M_B_DQSN4 DQS VDDQ F9 E9
[5] M_B_DQSN0 DQS VDDQ [5] M_B_DQSN7 DQS VDDQ E2 NC VDDQ
E2 E2 VDDQ G9
VDDQ VDDQ F9 E9 [5,17] M_B_CKE0 CKE0
F9 E9 F9 E9 NC VDDQ
NC VDDQ NC VDDQ [5,17] M_B_CKE0 G9
[5,17] M_B_CKE0 G9 [5,17] M_B_CKE0 G9 CKE0 A7
CKE0 CKE0 NU/TDQS
A7 B7 DM/TDQS
A7 A7 NU/TDQS
NU/TDQS NU/TDQS B7
B7 B7 DM/TDQS H9
DM/TDQS DM/TDQS ZQ1
H9 1R121 240/F_4
2 H8 ZQ0 VSS A1
H9 H9 ZQ1 [5,17] M_B_A[14..0] A8
ZQ1 ZQ1 1R125 240/F_4
2 H8 A1 VSS
1R116 240/F_4
2 H8 ZQ0 VSS A1 1R178 240/F_4
2 H8 ZQ0 VSS A1 [5,17] M_B_A[14..0]
ZQ0 VSS M_B_A14 N7 B1
VSS A8 A14 VSS
[5,17] M_B_A[14..0] VSS A8 [5,17] M_B_A[14..0] VSS A8 M_B_A14 M_B_A13 N3 J1
M_B_A14 M_B_A14 N7 A14 VSS B1 A13 VSS
N7 A14 VSS B1 N7 A14 VSS B1 M_B_A13 M_B_A12 K7 L1
M_B_A13 M_B_A13 N3 A13 VSS J1 A12/BC VSS
N3 A13 VSS J1 N3 A13 VSS J1 M_B_A12 M_B_A11 M7 N1
M_B_A12 M_B_A12 K7 A12/BC VSS L1 A11 VSS
K7 A12/BC VSS L1 K7 A12/BC VSS L1 M_B_A11 M_B_A10 H7 D8
M_B_A11 M_B_A11 M7 A11 VSS N1 A10/AP VSS
M7 A11 VSS N1 M7 A11 VSS N1 M_B_A10 M_B_A9 M3 F2
M_B_A10 M_B_A10 H7 A10/AP VSS D8 A9 VSS
H7 A10/AP VSS D8 H7 A10/AP VSS D8 M_B_A9 M_B_A8 N8 J9
M_B_A9 M_B_A9 M3 A9 VSS F2 A8 VSS
M3 A9 VSS F2 M3 A9 VSS F2 M_B_A8 M_B_A7 M2 L9
M_B_A8 M_B_A8 N8 A8 VSS J9 A7 VSS
N8 A8 VSS J9 N8 A8 VSS J9 M_B_A7 M_B_A6 M8 N9
M_B_A7 M_B_A7 M2 A7 VSS L9 A6 VSS
M2 A7 VSS L9 M2 A7 VSS L9 M_B_A6 M_B_A5 L2 F8
M_B_A6 M_B_A6 M8 A6 VSS N9 A5 VSS
M8 A6 VSS N9 M8 A6 VSS N9 M_B_A5 M_B_A4 L8
M_B_A5 M_B_A5 L2 A5 VSS F8 A4
L2 A5 VSS F8 L2 A5 VSS F8 M_B_A4 M_B_A3 K2 D1
M_B_A4 M_B_A4 L8 A4 A3 VSSQ
L8 A4 L8 A4 M_B_A3 M_B_A2 L3 B2
M_B_A3 M_B_A3 K2 A3 VSSQ D1 A2 VSSQ
K2 A3 VSSQ D1 K2 A3 VSSQ D1 M_B_A2 M_B_A1 L7 B8
M_B_A2 M_B_A2 L3 A2 VSSQ B2 A1 VSSQ
L3 A2 VSSQ B2 L3 A2 VSSQ B2 M_B_A1 M_B_A0 K3 C9
M_B_A1 M_B_A1 L7 A1 VSSQ B8 A0 VSSQ
L7 A1 VSSQ B8 L7 A1 VSSQ B8 M_B_A0 D9
M_B_A0 M_B_A0 K3 A0 VSSQ C9 VSSQ
K3 A0 VSSQ C9 K3 A0 VSSQ C9 H1
VSSQ D9 NC
VSSQ D9 VSSQ D9 H2
H1 NC [5,17] M_B_CS#0 CS0
H1 NC H1 NC [5,17] M_B_CS#0 H2 CS0
[5,17] M_B_CS#0 H2 CS0 [5,17] M_B_CS#0 H2 CS0 J3
C [5,17] M_B_BS2 BA2 C
J3 [5,17] M_B_BS1 K8 BA1
J3 J3 [5,17] M_B_BS2 BA2 J2
[5,17] M_B_BS2 BA2 [5,17] M_B_BS2 BA2 K8 [5,17] M_B_BS0 BA0
K8 K8 [5,17] M_B_BS1 BA1 A3
[5,17] M_B_BS1 BA1 [5,17] M_B_BS1 BA1 J2 NC1
J2 J2 [5,17] M_B_BS0 BA0 H3 J7
[5,17] M_B_BS0 BA0 [5,17] M_B_BS0 BA0 A3 [5,17] M_B_WE# WE NC2
A3 A3 NC1 N2
NC1 NC1 [5,17] M_B_WE# H3 J7 [4,15] DDR3_DRAMRST# RESET
[5,17] M_B_WE# H3 J7 [5,17] M_B_WE# H3 J7 WE NC2
WE NC2 WE NC2 [4,15] DDR3_DRAMRST# N2
[4,15] DDR3_DRAMRST# N2 [4,15] DDR3_DRAMRST# N2 RESET
RESET RESET
DDR3
DDR3
DDR3 DDR3
[5] M_B_DQ[24..31] U29 [5] M_B_DQ[8..15] U30
[5] M_B_DQ[40..47] U28 [5] M_B_DQ[48..55] U12 M_B_DQ24 E7 M_B_DQ15 E7
M_B_DQ46 E7 DQ7 DQ7
DQ7 M_B_DQ53 E7 M_B_DQ31 D2 M_B_DQ13 D2
M_B_DQ47 D2 DQ7 DQ6 DQ6
DQ6 M_B_DQ50 D2 M_B_DQ25 E8 M_B_DQ10 E8
M_B_DQ42 E8 DQ6 DQ5 DQ5
DQ5 M_B_DQ48 E8 M_B_DQ30 E3 M_B_DQ12 E3
M_B_DQ43 E3 DQ5 DQ4 DQ4
DQ4 M_B_DQ51 E3 M_B_DQ28 C8 J8 +SMDDR_VREF_DIMMB M_B_DQ11 C8 J8 +SMDDR_VREF_DIMMB
M_B_DQ40 C8 J8 +SMDDR_VREF_DIMMB DQ4 DQ3 VREFCA DQ3 VREFCA
DQ3 VREFCA M_B_DQ49 C8 J8 +SMDDR_VREF_DIMMB M_B_DQ27 C2 E1 +SMDDR_VREF_DQB M_B_DQ9 C2 E1 +SMDDR_VREF_DQB
M_B_DQ41 C2 E1 DQ3 VREFCA DQ2 VREFDQ DQ2 VREFDQ
DQ2 VREFDQ +SMDDR_VREF_DQB M_B_DQ54 C2 E1 M_B_DQ29 C7 M_B_DQ14 C7
M_B_DQ45 C7 DQ2 VREFDQ +SMDDR_VREF_DQB DQ1 DQ1
DQ1 M_B_DQ52 C7 M_B_DQ26 B3 M_B_DQ8 B3
M_B_DQ44 B3 DQ1 DQ0 DQ0
DQ0 M_B_DQ55 B3 A2 +1.5V_SUS A2 +1.5V_SUS
A2 +1.5V_SUS DQ0 VDD VDD
VDD A2 +1.5V_SUS F1 A9 F1 A9
F1 A9 VDD NC VDD NC VDD
NC VDD F1 A9 [5,17] M_B_ODT0 G1 D7 [5,17] M_B_ODT0 G1 D7
[5,17] M_B_ODT0 G1 D7 NC VDD ODT0 VDD ODT0 VDD
ODT0 VDD [5,17] M_B_ODT0 G1 D7 G2 G2
G2 ODT0 VDD VDD VDD
VDD G2 [5,17] M_B_RAS# F3 G8 [5,17] M_B_RAS# F3 G8
[5,17] M_B_RAS# F3 G8 VDD RAS VDD RAS VDD
RAS VDD [5,17] M_B_RAS# F3 G8 [5,17] M_B_CAS# G3 K1 [5,17] M_B_CAS# G3 K1
[5,17] M_B_CAS# G3 K1 RAS VDD CAS VDD CAS VDD
CAS VDD [5,17] M_B_CAS# G3 K1 K9 K9
K9 CAS VDD VDD VDD
VDD K9 [5,17] M_B_CLKP0 F7 M1 [5,17] M_B_CLKP0 F7 M1
[5,17] M_B_CLKP0 F7 M1 VDD CK VDD CK VDD
CK VDD [5,17] M_B_CLKP0 F7 M1 [5,17] M_B_CLKN0 G7 M9 [5,17] M_B_CLKN0 G7 M9
[5,17] M_B_CLKN0 G7 M9 CK VDD CK VDD CK VDD
CK VDD [5,17] M_B_CLKN0 G7 M9
CK VDD
[5] M_B_DQSP3 C3 DQS VDDQ B9 [5] M_B_DQSP1 C3 DQS VDDQ B9
[5] M_B_DQSP5 C3 DQS VDDQ B9
[5] M_B_DQSP6 C3 DQS VDDQ B9 [5] M_B_DQSN3 D3 DQS VDDQ C1 [5] M_B_DQSN1 D3 DQS VDDQ C1
[5] M_B_DQSN5 D3 DQS VDDQ C1
[5] M_B_DQSN6 D3 DQS VDDQ C1 VDDQ E2 VDDQ E2
VDDQ E2
VDDQ E2 F9 NC VDDQ E9 F9 NC VDDQ E9
F9 NC VDDQ E9
B F9 NC VDDQ E9 [5,17] M_B_CKE0 G9 CKE0 [5,17] M_B_CKE0 G9 CKE0 B
[5,17] M_B_CKE0 G9 CKE0 [5,17] M_B_CKE0 G9 CKE0
A7 NU/TDQS A7 NU/TDQS
A7 NU/TDQS A7 NU/TDQS B7 DM/TDQS B7 DM/TDQS
B7 DM/TDQS B7 DM/TDQS
H9 ZQ1 H9 ZQ1
H9 ZQ1 H9 1R186 240/F_4
2 H8 A1 1R206 240/F_4
2 H8 A1
1R179 240/F_4
2 H8 A1 ZQ1 [5,17] M_B_A[14..0] ZQ0 VSS [5,17] M_B_A[14..0] ZQ0 VSS
[5,17] M_B_A[14..0]
ZQ0 VSS 1R131 240/F_4
2 H8 ZQ0 VSS A1 VSS A8 VSS A8
VSS A8 [5,17] M_B_A[14..0] M_B_A14 M_B_A14
M_B_A14 VSS A8 N7 A14 VSS B1 N7 A14 VSS B1
N7 A14 VSS B1 M_B_A14 M_B_A13 M_B_A13
M_B_A13 N7 A14 VSS B1 N3 A13 VSS J1 N3 A13 VSS J1
N3 A13 VSS J1 M_B_A13 M_B_A12 M_B_A12
M_B_A12 N3 A13 VSS J1 K7 A12/BC VSS L1 K7 A12/BC VSS L1
K7 A12/BC VSS L1 M_B_A12 M_B_A11 M_B_A11
M_B_A11 K7 A12/BC VSS L1 M7 A11 VSS N1 M7 A11 VSS N1
M7 A11 VSS N1 M_B_A11 M_B_A10 M_B_A10
M_B_A10 M7 A11 VSS N1 H7 A10/AP VSS D8 H7 A10/AP VSS D8
H7 A10/AP VSS D8 M_B_A10 M_B_A9 M_B_A9
M_B_A9 H7 A10/AP VSS D8 M3 A9 VSS F2 M3 A9 VSS F2
M3 A9 VSS F2 M_B_A9 M_B_A8 M_B_A8
M_B_A8 M3 A9 VSS F2 N8 A8 VSS J9 N8 A8 VSS J9
N8 A8 VSS J9 M_B_A8 M_B_A7 M_B_A7
M_B_A7 N8 A8 VSS J9 M2 A7 VSS L9 M2 A7 VSS L9
M2 A7 VSS L9 M_B_A7 M_B_A6 M_B_A6
M_B_A6 M2 A7 VSS L9 M8 A6 VSS N9 M8 A6 VSS N9
M8 A6 VSS N9 M_B_A6 M_B_A5 M_B_A5
M_B_A5 M8 A6 VSS N9 L2 A5 VSS F8 L2 A5 VSS F8
L2 A5 VSS F8 M_B_A5 M_B_A4 M_B_A4
M_B_A4 L2 A5 VSS F8 L8 A4 L8 A4
L8 A4 M_B_A4 M_B_A3 M_B_A3
M_B_A3 L8 A4 K2 A3 VSSQ D1 K2 A3 VSSQ D1
K2 A3 VSSQ D1 M_B_A3 M_B_A2 M_B_A2
M_B_A2 K2 A3 VSSQ D1 L3 A2 VSSQ B2 L3 A2 VSSQ B2
L3 A2 VSSQ B2 M_B_A2 M_B_A1 M_B_A1
M_B_A1 L3 A2 VSSQ B2 L7 A1 VSSQ B8 L7 A1 VSSQ B8
L7 A1 VSSQ B8 M_B_A1 M_B_A0 M_B_A0
M_B_A0 L7 A1 VSSQ B8 K3 A0 VSSQ C9 K3 A0 VSSQ C9
K3 A0 VSSQ C9 M_B_A0 K3 A0 VSSQ C9 VSSQ D9 VSSQ D9
VSSQ D9
VSSQ D9 H1 NC H1 NC
H1 NC H1 NC [5,17] M_B_CS#0 H2 CS0 [5,17] M_B_CS#0 H2 CS0
[5,17] M_B_CS#0 H2 CS0 [5,17] M_B_CS#0 H2 CS0
[5,17] M_B_BS2 J3 BA2 [5,17] M_B_BS2 J3 BA2
[5,17] M_B_BS2 J3 BA2 [5,17] M_B_BS2 J3 BA2 [5,17] M_B_BS1 K8 BA1 [5,17] M_B_BS1 K8 BA1
[5,17] M_B_BS1 K8 BA1 [5,17] M_B_BS1 K8 BA1 [5,17] M_B_BS0 J2 BA0 [5,17] M_B_BS0 J2 BA0
[5,17] M_B_BS0 J2 BA0 [5,17] M_B_BS0 J2 BA0 NC1 A3 NC1 A3
NC1 A3
NC1 A3 [5,17] M_B_WE# H3 WE NC2 J7 [5,17] M_B_WE# H3 WE NC2 J7
[5,17] M_B_WE# H3 WE NC2 J7
[5,17] M_B_WE# H3 WE NC2 J7 [4,15] DDR3_DRAMRST# N2 RESET [4,15] DDR3_DRAMRST# N2 RESET
[4,15] DDR3_DRAMRST# N2 RESET [4,15] DDR3_DRAMRST# N2 RESET
A DDR3 DDR3 A
DDR3
DDR3 Separate from R112
+1.5V_SUS
R119 DIMM-A and +1.5V_SUS
+1.5V_SUS
+1.5V_SUS DIMM-B +SMDDR_VREF_DQB
1K/F_4
1K/F_4 +SMDDR_VREF_DIMMB
1

1
C74 C304 C76 C318 C143 C308

C78
1
10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 C251 C153 C141 C271 C268 C280 C136 C293 R109
2
1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 *1U/6.3V_4_NC

1U/6.3V_4 1K/F_4
1
PROJECT : D13
2
R120
0.1U/16V_4
1K/F_4 C140
2
16 Size Document Number Rev

0.1U/16V_4 1A
2
16
DDR3 2/2
5 4 3 2 1
http://vinafix.vn
5 4 3 2 1
fix
vina
D D
+0.75V_DDR_VTT
+0.75V_DDR_VTT
+0.75V_DDR_VTT
M_B_A[14..0] [5,16] M_A_A[14..0] [5,15] C277 C85 C273 C96
C79
36X4 2 1RN10 M_B_A7 36X4 2 1RN12 M_A_A7 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 10U/6.3V_6
4 3 M_B_A6 4 3 M_A_A13
6 5 M_B_A14 6 5 M_A_A4
8 7 M_B_A8 8 7 M_A_A8
[5,15] M_A_CLKP0
36X4 2 1RN7 M_B_A9 36X4 2 1RN11 M_A_A6
C C
4 3 M_B_A5 4 3 M_A_A1
6 5 M_B_A13 6 5 M_A_A2
8 7 M_B_A11 8 7 M_A_A3
R152
30.1/F_4
C291
36X4 2 1RN9 M_B_A3 36X4 2 1RN15 M_A_A0 1.5P/50V_4
4 3 M_B_A4 4 3 M_A_BS0 [5,15]
6 5 M_B_A1 6 5
8 7 M_B_A2 8 7 M_A_A12
M_A_CS#0 [5,15]
R153 C276
30.1/F_4 0.1U/16V_4
36X4 2 1RN8 M_B_A10 36X4 2 1RN16 M_A_A5
4 3 4 3 M_A_A9
M_B_WE# [5,16] [5,15] M_A_CLKN0
6 5 6 5 M_A_A14
M_B_BS1 [5,16]
8 7 8 7 M_A_A11
M_B_BS2 [5,16]
36X4 RN6 36X4 RN14

M_B_CS#0 [5,16]
2 1 2 1 M_A_BS2 [5,15] [5,16] M_B_CLKP0
4 3 M_B_A12 4 3 M_A_BS1 [5,15]
6 5 M_B_BS0 [5,16] 6 5 M_A_WE# [5,15]
8 7 8 7
M_B_A0 M_A_A10 R114
30.1/F_4
36X4 RN5 36X4 RN13
2 1 M_B_ODT0 [5,16] 2 1 M_A_CAS# [5,15]
4 3 M_B_CKE0 [5,16] 4 3 M_A_RAS# [5,15]
6 5 6 5 M_A_CKE0 [5,15] C215
M_B_RAS# [5,16]
8 7 8 7 M_A_ODT0 [5,15] 1.5P/50V_4
M_B_CAS# [5,16]
C98
B 0.1U/16V_4 B
R115
30.1/F_4
[5,16] M_B_CLKN0
R110
+0.75V_DDR_VTT
22_4 Q23
3
PMF780SN
2 PS_S3CNTRL [8]
S3 Power reduce
1
A A

PROJECT : D13
1A
DDR3 TERMINATION
5 4 3 2 1
http://vinafix.vn
5 4 3 2 1
fix
vina
MINI DISPLAY PORT CONNECTOR
D D
CN3
1 GND
[9] INT_DP_HPD_R 2 HP_DET GND 21
C1 0.1U/16V_4 INT_DP_TXP0 3 22
[9] INT_DP_TXP0_C LANE0+ GND
CAD_SINK# 4 23
T1 C2 0.1U/16V_4 INT_DP_TXN0 CONFIG1 GND
[9] INT_DP_TXN0_C 5 LANE0- GND 24
CONFIG2 6 25
T93 CONFIG2 GND
7 GND GND 26
8 GND
C3 0.1U/16V_4 INT_DP_TXP1 9
[9] INT_DP_TXP1_C LANE1+
C351 0.1U/16V_4 INT_DP_TXP3 10
+3.3V_RUN [9] INT_DP_TXP3_C LANE3+
C4 0.1U/16V_4 INT_DP_TXN1 11
[9] INT_DP_TXN1_C LANE1-
C352 0.1U/16V_4 INT_DP_TXN3 12
[9] INT_DP_TXN3_C LANE3-
13 GND
14 GND
C6 0.1U/16V_4 INT_DP_TXP2 15
[9] INT_DP_TXP2_C LANE2+
8/11: DPF1, change source to HF DPF1 AUX_SINK_P_R 16 AUX_CH+
(DK150TPU072 to DK150TPU009) 1206L150THW R [9] INT_DP_TXN2_C
C5 0.1U/16V_4 INT_DP_TXN2
AUX_SINK_N_R
17 LANE2-
18 AUX_CH-
19 GND
+3.3V_RUN_DPF1 20 DP_PWR
dp-3v112m1-rc5aa1-7h-20p
1
C350 C354
C *10U/6.3V_6_NC 0.1U/16V_4 C
2
+3.3V_RUN +3.3V_RUN
1
DisplayPort R3
*100K_4_NC
R18
100K_4
2
U1
C8 0.1U/16V_4 INT_AUX_SINKP 2 3 AUX_SINK_P_R
[9] INT_DP_AUXP_C 1A 1B
C22 0.1U/16V_4 INT_AUX_SINKN 5 6 AUX_SINK_N_R

[9] INT_DP_AUXN_C 2A 2B
B B
+5V_RUN 8 VCC
1
1
1 CAD_SINK# +5V_RUN
C20 1OE CAD_SINK#
4 GND 2OE 7
R4 R16 0.1U/16V_4
2
100K_4 *100K_4_NC
SN74CBTD3306CPW R
2
R7
4.7K_4
DDC_EN#
3
Q4 2 CAD_SINK#
PMF780SN
U2
1
1
2 3 AUX_SINK_P_R
[9] INT_DP_SCL 1A 1B R2
HDMI 5 6 AUX_SINK_N_R
1M_4
2
[9] INT_DP_SDA 2A 2B
+5V_RUN 8 VCC
1
1 DDC_EN#
C21 1OE DDC_EN#
4 GND 2OE 7
0.1U/16V_4
2
A
SN74CBTD3306CPW R A

PROJECT : D13
1A
MINI DP CONN
1
18 of 41
5 4 3 2 1
fix
vina 40Pin LVDS 1 2
EC11 100P/50V_4 1 2
2 1 ER2 0_4
J3 EC10 100P/50V_4 1 2
ER6 0_4 ER1 0_4
40 40 1 2 DMIC_DATA [29]
39 1 2 *PLW 3216S900SQ2T1_NC
39 DMIC_CLK [29] 1206
38 ER7 0_4
38 USBP12+_L
37 37 1 2 USBP12+ [11]
36 USBP12-_L 4 3 USBP12- [11]
36
D
35 35 D
34 34 LCD_TST [22]
33 LCD_DDCCLK EL1
33 LCD_DDCDAT LCD_DDCCLK [9]
32 32 LCD_DDCDAT [9]
31 INT_TXLOUTP2_R INT_TXLOUTP2_R 2 1
31 INT_TXLOUTP2 [9]
30 INT_TXLOUTN2_R 0_4 ER12
30 *PLW 3216S900SQ2T1_NC
29 29
28 INT_TXLOUTP1_R 2 1
28 INT_TXLOUTN1_R EC27
27 27 3 4
26 *1.5P/50V_4_NC
26 INT_TXLOUTP0_R EL7
25 25
24 INT_TXLOUTN0_R INT_TXLOUTN2_R 2 1
24 INT_TXLOUTN2 [9]
0_4 ER13
23 23
22 INT_TXLCLKOUTP_R
09/28: NO.4
22 INT_TXLCLKOUTN_R INT_TXLOUTP1_R
21 21 2 1 INT_TXLOUTP1 [9]
20 0_4 ER14
20 *PLW 3216S900SQ2T1_NC
19 19 LCD_PW M_OUT [39]
18 18 2 1
17 EC28 3 4
17 SMBCLK3 [22,28]
16 *1.5P/50V_4_NC
16 SMBDAT3 [22,28] EL8
15 LCD_PW M_IN
15 LCD_DBC INT_TXLOUTN1_R
14 14 LCD_DBC [22] 2 1 INT_TXLOUTN1 [9]
13 IFB1 0_4 ER15
13 IFB1 [39]
12 IFB2
12 IFB2 [39]
11 IFB3 INT_TXLOUTP0_R 2 1
11 IFB3 [39] INT_TXLOUTP0 [9]
10 IFB4 0_4 ER16
10 IFB4 [39] *PLW 3216S900SQ2T1_NC
9 9
8 8 2 1
41 7 EC29 3 4
C 41 7 *1.5P/50V_4_NC C
42 42 6 6 +3.3V_RUN
43 5 EL9
43 5 +LCDVCC INT_TXLOUTN0_R
4 4 2 1 INT_TXLOUTN0 [9]
44 3 0_4 ER17
44 3
45 45 2 2 +LED_BL
1 INT_TXLCLKOUTP_R 2 1
1 INT_TXLCLKOUTP [9]
0_4 ER18
*PLW 3216S900SQ2T1_NC
GS12401-1011-40P-R-NH-SMT +LED_BL +LCDVCC +3.3V_RUN 2 1
EC30
*1.5P/50V_4_NC
3 4 09/28: NO.4
1
C15 C14 C7 EL10
INT_TXLCLKOUTN_R 2 1 INT_TXLCLKOUTN [9]
0.1U/50V_6 0.047U/10V_4 0.1U/16V_4 0_4 ER19
2
10 16
08/11: Q1 change to HF
+15V_ALW +3.3V_RUN +LCDVCC
Q1 (FDC655BN to BAM06550000)
FDC655BN
B B
6
2
5 4
R6 2
330K_4 1
2
2
R1
1
47_8 C355 C10

LCDVCC_ON 0.01U/25V_4 Brightness Control
1
10U/6.3V_6 D8
1
[9] LCD_PW M 1
C11 3 LCD_PW M_IN

0.1U/25V_4
1
2 R36
[22] LCD_PW M_EC
BAT54C T/R 10K_4
+3.3V_SUS
3
2
5 2
Q2B
2
Q2A DMN66D0LDW -7
4
DMN66D0LDW -7
R5
10K_4
1
D6
3
A [9] ENVDD 1 A
3 EN_LCDVCC 2
Q5
2 DDTC124EUA-7-F
[22] LCDVCC_TST_EN
1
BAT54C T/R
PROJECT : D13
1A
LVDS CONN
1
19 of 41
5 4 3 2 1
f ix
ina
AVCC33X PVCCA33X
+5V_ALW +USB_SIDE_PWR1 +3V_USB3
Min Typ Max Min Typ Max
v
U35
3.15V 3.30V 3.45V 3.15V 3.30V 3.45V UP7534BRA8-15
09/28: NO.5 2
3
IN1 OUT3
8
7 R9
Current = 36mA Current = 72mA IN2 OUT2
U3 6 4.7K_4
OUT1
1
4
C339 1U/6.3V_4C341 0.1U/16V_4 EN#
1
USB32_P1+ 6.3v GND USB30_OC#
AVCC10X AVCC10 [4,11,21,22,23] PLTRST# B13 A55 5
2
PERST# U2DP0 USB32_P1- OC#
A56
U2DM0
PCI Express Interface

Min Typ Max Min Typ Max [12] CLK_PCIE_USB30P B17
PCIECKP USB3.0_TX1+
[12] CLK_PCIE_USB30N B18 B48
PCIECKM SSTXP0 USB3.0_TX1-
SuperSpeed USB Port 0 Interface

1.00V 1.05V 1.10V 1.00V 1.05V 1.10V B49
C23 0.1U/16V_4 PCIE_RXP4_C A23 SSTXM0 +5V_ALW
D [12] PCIE_RXP4 PCIE_RXN4_C A24 PCIETXP USB3.0_RX1+ D
C24 0.1U/16V_4 B50
Current = 164mA Current = 9mA TX base on FL1009 [12] PCIE_RXN4 PCIETXM SSRXP0
B51 USB3.0_RX1-
SSRXM0
1
[12] PCIE_TXP4 B15
PCIERXP R240
B16
RX base on FL1009 [12] PCIE_TXN4 PCIERXM
A57 R8 12K/F_4
DVCC33X DVCC33 R20 12K/F_4 A18
UREF0 47K_4
PCIEREXT C9 2200P/50V_4
Typ Typ B47
2
Min Max Min Max UCAP0
C25 0.1U/16V_4B19
PCIECAP
2.97V 3.30V 3.63V 2.97V 3.30V 3.63V A58 +1.05V_USB3.0
UV1280
3
Q3 Q6
A50 USB_P0_EN 2 USB_P0_EN 2
Current = 0mA Current = 5mA PPWR0 [22] USB_SIDE_EN
+3V_USB3 B39 USB30_OC# PMF780SN *PMF780SN_NC
1
OVCN0 C347
DVCC10X DVCC10 A4 4.7U/6.3V_4
AVCC33X
Analog 3.3V power supply

B45
C17 C16 AVCC33X
Min Typ Max Min Typ Max
1.00V 1.05V 1.10V 1.00V 1.05V 1.10V 1U/6.3V_4 0.1U/16V_4

A3 B2
AGND33 U2DP1
Current = 25mA Current = 90mA A59 B3
AGND33 U2DM1
B6
AGND33
B44 A7
AGND33 SSTXP1 +USB_SIDE_PWR1
SuperSpeed USB Port 1 Interface

A8
+3V_USB3 SSTXM1
A9
CANNOT floating even
SSRXP1
+3.3V_SUS +3V_USB3
A12
PVCC33X SSRXM1
A10 if it hasn't been used CN5
1
C338 C337 R10 12K/F_4 VBUS
1 2 B4
UREF1
1
+3.3V_ALW +15V_ALW R253 0_6 C343 USB32_P1-_C 2
Q9 1U/6.3V_4 0.1U/16V_4 C18 2200P/50V_4 C348 C349 C353 USB32_P1+_C D- USB2.0
10U/6.3V_6 A6 3
*FDC655BN_NC UCAP1 R14 *SJ0402_NC 22U/6.3V_8 22U/6.3V_8 0.1U/16V_4 D+
2
6 B5 1 2 +1.05V_USB3.0 4
UV1281 GND
1
5 4
1
2 A48 USB3.0_RX1-_C 5
R24 +1.05V_USB3.0 PPWR1 USB3.0_RX1+_C SSRX-
1 6
SSRX+
1
C R26 *100K_4_NC A46 10/04 NO.7 C

*100K_4_NC C31 OVCN1 C19 USB3.0_TX1-_C USB 3.0
A17 8
2
AVCC10X SSTX-
Analog 1.0V power supply

*0.1U/16V_4_NC A22 4.7U/6.3V_4 USB3.0_TX1+_C 9 10
2
C342 C340 AVCC10X SSTX+ GND

A60 11
AVCC10X GND
1
B7 7 12
AVCC10X GND GND
3
C32 1U/6.3V_4 0.1U/16V_4 A51 13

*PMF780SN_NC *4700P/25V_4_NC NC GND
2
2
Q8 Q7 USB3
B41
NC
3
*PMF780SN_NC
1
[8,22,34] SLP_S4# 2
A52 Need closed to CN4
NC
1
+1.05V_USB3.0
1
R25 B14 B43 C26 6.8P/50V_4 +USB_SIDE_PWR1

*100K_4_NC AVCC10 XSCI ESD1
C334 EL3 USB32_P1-_C 1 6
2
1 6
3
4
C330 USB32_P1- 3 4 USB32_P1-_C 2 5
1U/6.3V_4 Y1 USB32_P1+ USB32_P1+_C USB32_P1+_C 2 5
2 1 3 4
0.1U/16V_4 R21 3 4
A19 12MHz
AGND10 DLP11SN900HL2L TVL ST23 04 AD0
A61 *1M_4_NC
Crystal
AGND10
A62
1
2
AGND10
B8
B9
AGND10 10/204 NO.7 1 2
R246 *SJ0402_NC
PVCCA25OX AGND10 EL5
B20 A53
AGND10 XSCO C27 6.8P/50V_4 USB3.0_TX1N USB3.0_TX1-_C
3 4
B11 1 2 USB3.0_TX1P 2 1 USB3.0_TX1+_C
PVCC25OX R244 *SJ0402_NC
FL1009
C335 C336 EL4 *DLP11SN900HL2L_NC
USB3.0_RX1- 3 4 USB3.0_RX1-_C 1 2
1U/6.3V_4 0.1U/16V_4 USB3.0_RX1+ 2 1 USB3.0_RX1+_C R245 *SJ0402_NC
Internal POWER
+3V_USB3
R239 *DLP11SN900HL2L_NC
B34 R12 4.7K_4 1 2 USB3.0_TX1- C13 USB3.0_TX1N
0.1U/16V_4
PPWRCTL R243 *SJ0402_NC
10/04 NO.7 *SJ0402_NC 1
USB3.0_TX1+ USB3.0_TX1P
C12 0.1U/16V_4
PVCCA25X A39 AUXDET R13 4.7K_4
10/04 NO.7
AUXDET EU1 TVU1240R1A
A5
B PVCC25X USB30_WAKE# B
A21 A14 USB30_WAKE# [22]
PVCC25X WAKE# USB3.0_RX1-_C USB3.0_RX1-_C
B46 1 10
PVCC25X 1- NC
C345 C331 A15 PCIE_CLK_REQ4# PCIE_CLK_REQ4# [12]
CLKREQ# USB3.0_RX1+_C USB3.0_RX1+_C
2 9
1+ NC
1U/6.3V_4 0.1U/16V_4 A1 B28 SMIB# SMIB# [13]
U33 G966A-25ADJF11U PGND SMI#
A20 3
1 8
Vout=0.8*(R222+R223)/R223 A54
PGND GND
VENABLE POK GND PGND EEPORM_SDA USB3.0_TX1-_C USB3.0_TX1-_C
2 7 B10 B27 T95 4 7
VEN ADJ PGND ROMSDA 2- NC
+1.5V_SUS 3 6 +1.05V_USB3.0
VIN VO +3V_USB3 EEPROM_SCL USB3.0_TX1+_C USB3.0_TX1+_C
+5V_SUS 4 5 A35 T96 5 6
VPP NC ROMSCL 2+ NC
9
Digital IO power supply
EEPROM
A44 A33 EEPROM_PRESENT
9
DVCC33X ROMPRES T97

R23 B12
C30 60.4K/F C344 C333 DVCC33X
B38
C29 C28 DVCC33X
10U/6.3V_6 B22
0.1U/16V_4 1U/6.3V_4 C327 1U/6.3V_4 0.1U/16V_4 U2LNK#
B21
PCIELNK#
10U/6.3V_6 A26 A27
DVCC33 SSLNK#
B25 A28
DVCC33 DATTX#
B30 B24
R22 DVCC33 DATRX#
191K/F_6
+1.05V_USB3.0
A11 A2
DVCC10X NC
A13 A29
DVCC10X NC
Digital core power supply
C332 C346 B40 A30

DVCC10X NC
B42 A31
1U/6.3V_4 0.1U/16V_4 DVCC10X NC
B52 A32
R238 *SJ0402_NC DVCC10X NC
A34
VENABLE NC
+3V_USB3 2 1 A37
NC
A16 A38
DVCC10 NC
A25 A40
DVCC10 NC
10/04 NO.7 C329
A36
A41
DVCC10 NC
A43
A45
*0.1U/16V_4_NC DVCC10 NC
A42 A47
DVCC10 NC
B23 A49
DVCC10 NC
B26 A63
DVCC10 NC +3V_USB3
A B32 A64 A
DVCC10 NC
B1
NC
B29
NC
B31
NC R11
B33
NC
B35 4.7K_4
NC
B36
NC
117 B37
Exposed Pad TESTN
FL1009 Quanta Computer Inc.

PROJECT : D13
1A
TI USB 3.0
5 4 3 2 1
http://vinafix.vn
1 2 3 4 5 6 7 8
f ix
v ina
MiniCard WLAN connector
+3.3V_W LAN +3.3V_W LAN
+3.3V_W LAN +3.3V_W LAN
1
A A
WLAN_WAKE#: R34
10K_4
2
EC internal PU to +3.3V_ALW Q11 PMF780SN
J2
2
[22] W LAN_W AKE# 3 1 1 WAKE# +3.3V 2 For Debug Only, Remove at QT
3 Reserved GND 4
5 Reserved +1.5V 6
7 8 LPC_LFRAME#_R R31 1 2 0_4
[12] PCIE_CLK_REQ1# CLKREQ# Reserved LPC_LFRAME# [10,22,23]
9 10 LPC_LAD3_R R30 1 2 0_4
GND Reserved LPC_LAD2_R R29 0_4 LPC_LAD3 [10,22,23]
[12] CLK_PCIE_W LANN 11 REFCLK- Reserved 12 1 2 LPC_LAD2 [10,22,23]
13 14 LPC_LAD1_R R28 1 2 0_4
[12] CLK_PCIE_W LANP REFCLK+ Reserved LPC_LAD1 [10,22,23]
For Debug Only, Remove at QT 15 16 LPC_LAD0_R R27 1 2 0_4
GND Reserved LPC_LAD0 [10,22,23]
R236 1 2 0_4 PLTRST#_R 17 18
[4,11,20,22,23] PLTRST# Reserved GND
R235 1 2 0_4 CLK_LPC_DEBUG_R 19 20 W LAN_ON/OFF_R#
[11] CLK_33M_LPC Reserved Reserved
21 GND PERST# 22 PLTRST# [4,11,20,22,23]
TX base on device [12] PCIE_RXN2 23 PERn0 +3.3Vaux 24
[12] PCIE_RXP2 25 PERp0 GND 26
27 GND +1.5V 28
29 30 T3 ER4 2 1 *SJ0402_NC
GND SMB_CLK
[12] PCIE_TXN2 31 PETn0 SMB_DATA 32 T2
RX base on device 33 34 EL2
[12] PCIE_TXP2 PETp0 GND
35 36 USBP4-_R USBP4+_R 3 4
GND USB_D- USBP4+_R USBP4-_R USBP4+ [11]
[13] PCIE_MCARD1_DET# 37 Reserved USB_D+ 38 2 1 USBP4- [11]
39 Reserved GND 40 USB_MCARD1_DET# [13]
41 42 *DLP11SN900HL2L_NC
Reserved LED_WWAN#
43 Reserved LED_WLAN# 44
45 Reserved LED_WPAN# 46 2 1
B 47 48 ER5 *SJ0402_NC B
Reserved +1.5V
49 50
GND
GND
Reserved GND
[13] BT_RADIO_DIS# 51 Reserved +3.3V 52 10/204 NO.7
53
54
Mini Card
+3.3V_WLAN
Max Current : 0.667A
+3.3V_RUN +3.3V_W LAN
+15V_ALW +3.3V_ALW +3.3V_W LAN

Q10 1 2
FDC655BN
6 R32 *0_6_NC
1
5 4
2
R35 1
1
100K_4
C38
2
C W LAN_PW ER_ON 0.1U/16V_4 C

2
3
2 C39
[22] W LAN_PW ER_EN#
4700P/25V_4
2
Q12
1
PMF780SN
Support for WoW Prevent backdrive when

+3.3V_W LAN +3.3V_RUN WoW is enabled.
+3.3V_W LAN
C37 4.7U/6.3V_4
D
C33 1 2 0.1U/16V_4 D
R241 C36 0.1U/16V_4
10K_4
09/28: NO.2 C35
1
1
2
2 0.1U/16V_4
2
Q34 PMF780SN C34 1 2 0.1U/16V_4
W LAN_ON/OFF_R# 3 1 W LAN_ON/OFF# [13]

Place caps close to connector. Quanta Computer Inc.
PROJECT : D13
1A
MINI-PCI (WLAN/WPAN)
1 2 3 http://vinafix.vn 4 5 6
7
Sheet 21
8
of 41
5 4 3 2 1
f ix
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CLK_33M_KBC +3.3V_ALW
IMVP_PW RGD KB_BACKLITE_EN R62 10K_4
v ER3 +RTC_CELL
1
10/F_4 C63 1U/6.3V_4
USB30_W AKE# [20]
C66 +3.3V_ALW _AVCC
T4
100P/50V_4 C61 1 2 0.1U/16V_4
ALW _ON [26,33]
2
C56 1 2 0.1U/16V_4
EC_PW ROK [4,8]
1
C69 1 2 0.1U/16V_4 C70 1 2 0.1U/16V_4

AC_OFF [38]
EC2
+3.3V_ALW PCH_AZ_CODEC_RST# [10,29]
2.2P/50V_4
CAP_LED [24]
2
BID1 Place these caps close to ITE8518.

+3.3V_RUN
D BID0 D
USB_CHG_DET#_R [26]
U6
CLKRUN# [8]
IT8519
C11
C12
E12
A10
A11
B12
F12
F10
J12
+3.3V_ALW
G5
G8
G2
G3
D1
E6
E7
E8
A1
E5
RP2 4.7KX2
E1 B6 SMBCLK0 SMBDAT0 1 2
VCC
AVCC
EGCLK/WUI27/GPE3(Dn)
EGCS#/WUI26/GPE2(Dn)
EGAD/WUI25/GPE1(Dn)
L80HLAT/BAO/WUI24/GPE0(Dn)
L80LLAT/WUI7/GPE7(Up)
HMOSI/GPH6/ID6(Dn)
HMISO/GPH5/ID5(Dn)
HSCK/GPH4/ID4(Dn)
HSCE#/WUI19/GPH3/ID3(Dn)
CLKRUN#/WUI16/GPH0/ID0(Dn)
VSTBY
VSTBY
VSTBY
VSTBY
VSTBY
VSTBY
VBAT
[10,21,23] LPC_LAD0 LAD0/GPM0(3_X) SMCLK0/GPB3(X) SMBCLK0 [32,38]
SMBDAT0 SMBCLK0
[10,21,23] LPC_LAD1 D2 LAD1/GPM1(3_X) SMDAT0/GPB4(X) C6 SMBDAT0 [32,38] Charge ,BAT 3 4
D4 SM BUS B5 SMBCLK1
[10,21,23] LPC_LAD2 LAD2/GPM2(3_X) SMCLK1/GPC1(X) SMBCLK1 [12]
SMBDAT1 RP3 10K
[10,21,23] LPC_LAD3 C3 LAD3/GPM3(3_X) SMDAT1/GPC2(X) A6 SMBDAT1 [12] PCH SMBDAT1
[4,11,20,21,23] PLTRST# H3 LPCRST#/WUI4/GPD2(Up) PECI/SMCLK2/WUI22/GPF6(3_Up) C5 PECI_EC [4] 1 2
E2 C4 SMBCLK1 3 4
[11] CLK_33M_KBC LPCCLK/GPM4(3_X) SMDAT2/WUI23/GPF7(3_Up) W LAN_PW ER_EN# [21]
[10,21,23] LPC_LFRAME# D3 LFRAME#/GPM5(3_X)
PS2CLK0/TMB0/GPF0(Up) E10 PCH_MELOCK [10]
E3 E11 H_PROCHOT#_EC USB_BACK_EN# R42 1 2 *10K_NC
[19] LCD_TST LPCPD#/WUI6/GPE6(Dn) PS2DAT0/TMB1/GPF1(Up)
PS2CLK2/WUI20/GPF4(Up) D11 CLK_TP_SIO [24]
PS/2
D13 2 1 SDMK0340L-7-F B2 D12
[13]
SIO_A20GATE GA20/GPB5(3_X) PS2DAT2/WUI21/GPF5(Up) DAT_TP_SIO [24] +3.3V_RUN
IRQ_SERIRQ A2 LPC
[10,23]
IRQ_SERIRQ SERIRQ/GPM6(3_X)
D16 2 1 SDMK0340L-7-F F2 RP1 2.2KX2
[13]
SIO_EXT_SMI# ECSMI#/GPD4(3_Up)
D17 2 1 SDMK0340L-7-F H2 SMBDAT3 1 2
[13]
SIO_EXT_SCI# ECSCI#/GPD3(Up)
W RST# F1 GPIO SMBCLK3 3 4
T12 WRST#
D14 2 1 SDMK0340L-7-F C2
[13] SIO_RCIN# KBRST#/GPB6(3_X)
[26] BLED_ SW _IN0#_R G1 PWUREQ#/BBO/SMCLK2ALT/GPC7(3_Up)
J3 0209 R239,R245 de-pop
IT8519 PWM0/GPA0(Up)
PWM1/GPA1(Up)
PWM2/GPA2(Up)
J2
J1
KB_BACKLITE_EN [24]
BLED3 [27]
FAN1_PW M [28]
SUS_ON R51 2 1 *100K_4_NC
IMVP_VR_ON R57 *100K_4_NC
C
[8,28,37] IMVP_PW RGD
[35,36,39] RUN_ON
T9
B4
A4
CRX0/GPC0(Dn)
CTX0/TMA0/GPB2(3_Dn) CIR BGA-128 PWM3/GPA3(Up)
PWM4/GPA4(Up)
K1
M1
L1
LCD_PW M_EC [19]
BAT_LED_AMBER [29]
BAT_LED_W HITE [29]
C
PWM5/GPA5(Up)
Not pin to pin ! PWM +3.3V_ALW
T10
[8] RSMRST# G12 DAC4/DCD0#/GPJ4(3_X)
[29] NB_MUTE# B9 DSR0#/GPG6(X) TACH0A/GPD6(3_Dn) L6 FAN1_TACH [29]
2
[19] LCDVCC_TST_EN L2 GINT/CTS0#/GPD5(Up) TACH1A/TMA1/GPD7(3_Dn) J9 LCD_BAK [39]
[27] BLED2 D10 PS2DAT1/RTS0#/GPF3(Up)
D12 2 SDMK0340L-7-F
1 F11 A5 R65
[8] SIO_PW RBTN# DAC5/RIG0#/GPJ5(3_X) TMRI0/WUI2/GPC4(3_Dn) LID_SW # [29]
D9 B3 100K_4
[38] PS_ID PS2CLK1/DTR0#/GPF2(Up) TMRI1/WUI3/GPC6(3_Dn) SIO_SLP_S3# [8,34]
[19] LCD_DBC A8
1
TXD/SOUT0/GPB1(Up) D15
[27] BLED4 B8 RXD/SIN0/GPB0(Up)
1 2 W RST#
[28,30] THERM_STP#
[38] PBAT_PRES# K11 ADC5/DCD1#/WUI29/GPI5(3_X) UART port PWRSW/GPE4(3_Up) A3 SYS_PW R_SW # [26]
J11 F3 W LAN_W AKE# SDMK0340L-7-F
[32] IINP ADC6/DSR1#/WUI30/GPI6(3_X) RI1#/WUI0/GPD0(3_Up) W LAN_W AKE# [21]
[8,34] SIO_SLP_S5# H11 ADC7/CTS1#/WUI31/GPI7(3_X) RI2#/WUI1/GPD1(Up) H1 2 1 ACAV_IN [26,32]
M3 WAKE UP SDMK0340L-7-F D18 C68
[8] PCIE_W AKE# RTS1#/WUI5/GPE5(Dn)
K2 1U/6.3V_4
[29] BEEP PWM7/RIG1#/GPA7(Up)
C7 A7 AC_PRESENT
[8,20,34] SLP_S4# DTR1#/SBUSY/GPG1/ID7(Dn) RING#/PWRFAIL#/CK32KOUT/LPCRST#/GPB7(Dn) AC_PRESENT [8]
SMBDAT3 B11
[19,28] SMBDAT3 CTX1/WUI18/SOUT1/GPH2/SMDAT3/ID2(Dn)
SMBCLK3 A12
[19,28] SMBCLK3 CRX1/WUI17/SIN1/SMCLK3/GPH1/ID1(Dn)
EC_FLASH_SPI_CLK C8
[25] EC_FLASH_SPI_CLK FSCK
EC_FLASH_SPI_CS# C10
[25] EC_FLASH_SPI_CS# FSCE#
EC_FLASH_SPI_DIN A9 EXTERNAL SERIAL FLASH
[25] EC_FLASH_SPI_DIN FMOSI
EC_FLASH_SPI_DO C9 M12
[25] EC_FLASH_SPI_DO FMISO ADC0/GPI0(3_X) HW PG [8,30]
C62 2 1*100P/50V/NPO_4_NC L12 T_CPU Board ID Straps
ADC1/GPI1(3_X) T_CPU [28]
KSO16 K8 K12
KSO16/SMOSI/GPC3(3_Dn) ADC2/GPI2(3_X) ME_SUS_PW R_ACK [8]
IMVP_VR_ON K7 M11
B [37] IMVP_VR_ON KSO17/SMISO/GPC5(3_Dn) ADC3/GPI3(3_X) CRIT_TEMP_REP# [13] +3.3V_ALW B
[27] BLED0 M2 PWM6/SSCK/GPA6(Up) ADC4/WUI28/GPI4(3_X) L11 PANEL_BKEN [9]
T6
SUS_ON B10 A/D D/A
09/28: NO.1
[39] SUS_ON SSCE0#/GPG2(X)
[24] KB_DET# B7 SSCE1#/GPG0(X) SPI ENABLE
TACH2/GPJ0(3_X) H10 USBP0_BUS_SW _CB0 [29]
1
KSO0 L3 J10
KSO0/PD0 GPJ1(3_X) SIO_EXT_W AKE# [11]
KSO1 K3 G10 R43 R48
KSO1/PD1 TACH0B/DAC2/GPJ2(3_X) USB_SIDE_EN [20]
KSO2 J4 G11 USB_BACK_EN# 10K_4 *10K_4_NC
KSO2/PD2 TACH1B/DAC3/GPJ3(3_X) USB_BACK_EN# [29]
KSO3 L4
BEEP KSO4 KSO3/PD3
H5 KBMX
2
KSO5 KSO4/PD4
M4 KSO5/PD5
NB_MUTE# KSO6 K4
KSO7 KSO6/PD6
M5 KSO7/PD7
EC20 EC22 KSO8 L5 BID1
KSO9 KSO8/ACK# BID0
K5 KSO9/BUSY
2
*100P_NC*100P_NC KSO10 M6
KSO11 KSO10/PE
H6 C1 BLED1 [27]
KSI3/SLIN#
KSO11/ERR# CK32KE(3_X)
KSI1/AFD#
KSI0/STB#
KSI2/INIT#
KSO12 M7 CLOCK B1 R45 R49

KSO13 KSO12/SLCT CK32K(3_X) T11 *10K_4_NC 10K_4
VCORE
K6 KSO13
AVSS
KSO14 L7
KSI4
KSI5
KSI6
KSI7
VSS
VSS
VSS
VSS
VSS
VSS
1
KSO15 KSO14
H7 KSO15
M8
L9
M9
L8
K9
M10
L10
K10
F5
F6
F7
G6
G7
H8
H12
F8
[24] KSO[0..16]
BID1 BID0 D13
[24] KSI[0..7] IMVP7_PROCHOT# [4,32,37]
0 0 SSI (X00)
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
A
0 1 PT (X01) A
2
C58 1 0 ST (X02)
0.1U/16V_4 1 1 QT (A00)
0 0 (A01)
1
+3.3V_ALW L2
BLM11A05S H_PROCHOT#_EC 2 Q16
+3.3V_ALW _AVCC
603 PMF780SN Quanta Computer Inc.
1
2
C57
0.1U/16V_4 R46
100K_4 PROJECT : D13
1
L1 Size Document Number Rev

603 1A
SIO (ITE8519E)
http://vinafix.vn
BLM11A05S
5 4 3 2 1
1 2 3 4 5 6 7 8
f ix
vina
A A
mSATA Connector
+5V_RUN is for testing mSATA by factory. +3.3V_RUN
CON1 +1.5V are NC pin for this connector.
TPM
1 Reserved +3.3V 2 +3.3V_RUN
3 4 R231 *0_4_NC R38
Reserved GND
5 Reserved +1.5V 6 1 2 +5V_RUN 4.7K_4
7 Reserved Reserved 8 U5
9 GND Reserved 10
Max =6000 mils 11 Reserved Reserved 12 1 ATEST LPCPD# 28
1
13 14 C51 C52 2 27
Min = 1000 mils Reserved Reserved 0.1U/16V_4 2200P/50V_4 ATEST SERIRQ IRQ_SERIRQ [10,22]
15 GND Reserved 16 3 ATEST LAD0 26 LPC_LAD0 [10,21,22]
1
DG: Place TX cap close to connector 4 25 C50
2
GND GND 2200P/50V_4
17 Reserved GND 18 +3.3V_RUN 5 SB3V VCC 24
19 20 6 23
TX- based on SSD
2
Reserved Reserved GPIO6 LAD1 LPC_LAD1 [10,21,22]
21 GND Reserved 22 7 NC LFRAME# 22 LPC_LFRAME# [10,21,22] +3.3V_RUN
C45 0.01U/25V_4 SATA_RXP0_C 23 24 8 21 CLK_33M_TPM [11]
[10] SATA_RXP0 SATA_RXP +3.3 V TESTI LCLK
C44 0.01U/25V_4 SATA_RXN0_C R233 *0_4_NC
[10] SATA_RXN0 25 SATA_RXN GND 26 9 TESTBI LAD2 20 LPC_LAD2 [10,21,22] 5/25 NO. 72
1
27 28 1 2 +3.3V_RUN 10 19 C55
GND +1.5V VCC VCC 2200P/50V_4
29 GND SMB_CLK 30 11 GND GND 18
1
[10] SATA_TXN0 C42 0.01U/25V_4 SATA_TXN0_C 31 32 C47 C48 12 17
2
C43 0.01U/25V_4 SATA_TXP0_C SATA_TXN SMB_DATA 0.1U/16V_4 2200P/50V_4 NBO LAD3 LPC_LAD3 [10,21,22]
[10] SATA_TXP0 33 SATA_TXP GND 34 13 NBO LREST# 16 PLTRST# [4,11,20,21,22]
B 35 36 14 15 B
2
GND Reserved NBO CLKRUN#
37 38
RX- based on SSD +3.3V_RUN 39
GND Reserved
40
+3.3 V GND R39
41 +3.3 V Reserved 42 AT97SC3204 EC1
43 Device Type Reserved 44 4.7K_4
45 46 R234 *0_4_NC *10P/50V_4_NC
Vendor Specific Reserved
47 Vendor Specific +1.5V 48 1 2
49 DAS GND 50
51 Presence Detect +3.3V 52
2
R237 SATA_HDD Add EMC solution

*0_4_NC
1
10/204 NO.7
+3.3V_RUN
C C
C46 C40
C326
10U/6.3V_6 1U/6.3V_4 0.1U/16V_4
Place caps close to connector.
D D

PROJECT : D13
1A
SATA HDD/ODD
7
Sheet 23
8
of 41
1 2 3 4 5 6 7 8
a fix
vin KEYBOARD CONNECTOR
03/30 Change CP1,CP2,CP3,CP4,CP5,CP6,C382 from Pop to Depop Vi(on_max)= -1.4V
CP2 *100PX4_NC CP1 *100PX4_NC CP4 *100PX4_NC
Vi(off_min)=-0.3
8 7 KSO13 8 7 KSO10 8 7 KSO8
6 5 KSO15 6 5 KSO11 6 5 KSO6 +5V_RUN
4 3 KSO16 4 3 KSO9 4 3 KSO7
A 2 1 KSO12 2 1 KSO14 2 1 KSO4 A
1
1206 50 NPO 1206 50 NPO 1206 50 NPO
Q13
CP6 *100PX4_NC CP5 *100PX4_NC DDTA114YUA-7-F
47K
CP3 *100PX4_NC 8 7 KSI5 8 7 KSO5
8 7 KSO0 6 5 KSI2 6 5 KSI0 2
6 5 KSO2 4 3 KSI4 4 3 KSI3 10K
3
4 3 KSO1 2 1 KSI6 2 1 KSI1
2 1 KSO3 [22] CAP_LED 2
1206 50 NPO 1206 50 NPO
3
1206 50 NPO Q14
1
1
PMF780SN
R252 R37
10K_4 150_4
C60 1 2 *100P/50V/X7R_4_NC KSI7 1 2 CAP_LED_L
2
8.67mA
B B
Key board illumination

KEYBOARD CONNECTOR
+KB_LED power trace width >10 mil
FS1 +3.3V_SUS R55 1 2 10K_4
1206L050YR
+5V_RUN JKB1
Q28
410mA NTR4503NT1G
+5V_RUN 1 2
1
[22] KB_DET# 1
J1 KSI7 2
LED_PW M R230 100K_4 KSI6 2
3 1 4 4 3 3
1
1 2 3 KSI4 4
[11] KB_LED_DET 3 4
2 C41 KSI2 5
2 5
1
LED_PW M 1 0.1U/16V_4 KSI5 6

2
2
1 KSI1 6
[22] KSO[0..16] 7 7
R232 91504-0401 KSI3 8
200K/F_4 KSI0 8
[22] KSI[0..7] 9 9
KSO5 10
2
KSO4 10
[22] KB_BACKLITE_EN 08/01: J1 change from KSO7
11
12
11
12
DFFC04FR055 to DFFC04FR068 KSO6 13 13
KSO8 14
KSO3 14
15 15
KSO1 16
KSO2 16
17 17
KSO0 18
KSO12 18
19 19
KSO16 20
C KSO15 20 C
21 21
KSO13 22
KSO14 22
23 23
KSO9 24
KSO11 24
25 25
+3.3V_RUN +3.3V_RUN KSO10 26
Touch Pad CAP_LED_L 27
26
27
28 28
29 29 31 31
30 30 32 32
1
3
ERP1
4.7KX2 C325 C324 51510-03041-001
0.1U/16V_4 0.047U/10V_4
Add EMC solution
2
16 10
EC9 10P/50V_4
2
4
+3.3V_RUN
EC8 10P/50V_4 JP1
20mil
L9 1 1
[22] DAT_TP_SIO 2 BLM18AG601SN1D TP_DATA
2
L8 1 603 2 BLM18AG601SN1D TP_CLK
[22] CLK_TP_SIO 603 3
4
[12] TP_SDATA 5 7
[12] TP_SCLK 6 8
D
50503-0060N-001 D

PROJECT : D13
1A
TP / KB
7
Sheet 24
8
of 41
5 4 3 2 1
f ix
vina
For EC 4Mbit (512K Byte) The max charge current is flow on charged at the end voltage of battery
D
+3.3V_ALW +3.3V_ALW
2V. And the charge current is 1mA. D
R >= (+RTC_CELL - 2)/1mA
T5
R101
T91
10K_4
T8
R228
T7 U32 +RTC_CELL +3.3V_RTC_LDO
[22] EC_FLASH_SPI_CS# 1 CE# VDD 8
10K_4
RTC BATTERY
[22] EC_FLASH_SPI_CLK 6 SCK
[22] EC_FLASH_SPI_DIN 5 SI
[22] EC_FLASH_SPI_DO 2 SO HOLD# 7 1 2
C322 3 4 RTCD1
*22P_NC WP# VSS C323 SDMK0340L-7-F
W 25X40BVSSIG 0.1U/16V_4
Change R438,R435,R437 from 15 ohm to 0 ohm RTCBT1
RTCR2 1K_4 RTCR1 390_4
+RTC_1_R 1 2 +RTC_1 2 1
RTC_SOCKET/2032
C357
1U/6.3V_4
C C
For PCH 64Mbit (8M Byte)

RTC-BATTERY
+3.3V_RUN +3.3V_RUN
Change R351,R399,R378,R358 from 15 ohm to 0 ohm R181

10K_4
R180
U27 10K_4
PCH_SPI_CS0# 1 8
[10] PCH_SPI_CS0# CE# VDD
PCH_SPI_CLK 6
[10] PCH_SPI_CLK SCK
PCH_SPI_SI 5
[10] PCH_SPI_SI SI
PCH_SPI_SO 2 7
[10] PCH_SPI_SO SO HOLD#
C306 3 4
*22P_NC WP# VSS C307
W 25Q64BVSSIG 0.1U/16V_4
Change SPI ROM for BIOS to AKE3EFP0N04 -0613

B B
A A

PROJECT : D13
1A
FLASH / RTC
1
25 of 41
A B C D E
fix
vina
3VALW ON POWER LOGIC
+3.3V_ALW
PT +3.3V_ALW
4 4
2
R56
100K_4
D10
2
+5V_ALW 2
1
2 R58
USB_CHG_DET#_R [22]
100K_4
USB_CHG_DET# 3
[29] USB_CHG_DET#
1
1
2
R63 R64
BAT54C T/R 100K_4 100K_4
SYS_PW R_SW # [22]
1
D11
1
2 C64
0.1U/16V_4
2
POW ER_SW _IN0# 3
[29] POW ER_SW _IN0# 3.3V_ALW _ON [30]
1
For Debug PWR SW BAT54C T/R
3
LATCH 5 Q18A
DMN66D0LDW -7
POW ER_SW _IN0#
4
1
3 3
C67
2
*0.1U/10V/X7R_4_NC
2
R229
*0_6_NC
1
6
2 Q18B
D9 [22,33] ALW _ON
DMN66D0LDW -7
2
1
[27] BLED_ SW _IN0# 3
1
+3.3V_ALW
BAT54C T/R
3
2
[22,32] ACAV_IN 2
R47
10K_4 Q17
1
PMF780SN
1
BLED_ SW _IN0#_R [22]
2 2
1 1

PROJECT : D13
1A
PWR SW/LED
A B http://vinafix.vn C D
E
26 of 41
A B C D E
fix
vina Truth table of Battery LED
Battery Power State BLED4 BLED3 BLED2 BLED1 BLED0 LED State
Battery Status LED <20% 0 0 0 0 0 N/A

4 4
[22] BLED0
BLED0 20% 0 0 0 0 1 D29
BLED1
[22] BLED1
40% 0 0 0 1 1 D29 D30
BLED2
[22] BLED2
[22] BLED3
BLED3 60% 0 0 1 1 1 D29 D30 D31
BLED4
[22] BLED4
80% 0 1 1 1 1 D29 D30 D31 D32
100% 1 1 1 1 1 D29 D30 D31 D32 D33
10/14, change current limit resistor from 365 ohm to 620

+5V_ALW +5V_ALW +5V_ALW +5V_ALW +5V_ALW
3 3
R248
620_4 R249 R247 R250 R251
620_4 620_4 620_4 620_4
2
2
D1
HT-S91BP5 D2 D3 D4 D5
HT-S91BP5 HT-S91BP5 HT-S91BP5 HT-S91BP5
1
1
10/06 NO.08
10/06 NO.08 10/06 NO.08 10/06 NO.08 10/06 NO.08
3
3
BLED0 2 Q33 BLED1 2 Q30 BLED2 2 Q32 BLED3 2 Q29 BLED4 2 Q31
PMF780SN PMF780SN PMF780SN PMF780SN PMF780SN
2
2
C356 C360 C358 C359
1
1
R258 C361 R259 R260 R261 R262
10K_4 10K_4 1U/6.3V_4 10K_4 1U/6.3V_4 10K_4 1U/6.3V_4 10K_4 1U/6.3V_4
1U/6.3V_4
1
1
2 2
Battery LED need to change direction
Battery LED button
SW 1
[26] BLED_ SW _IN0# 1 2

3 4
SKRELJE010
1 1

PROJECT : D13
1A
LED SWITCH
A B http://vinafix.vn C D
Date: Friday, October 14, 2011 Sheet
E
27 of 41
1 2 3 4 5 6 7 8
fix
vina
+5V_RUN +5V_RUN
2
+5V_FAN1 C269
*DA204U_NC 1U/6.3V_4
A
D21 A
U21
3
1 VEN GND 8
2 VIN GND 7
+5V_FAN1 3 6
FAN1_PW M R159 VO GND
[22] FAN1_PW M 4 SET GND 5
180K/F_4
G990P11U
C281
1000P/50V_4
B B
SYS_SHD#
2K 7.5K 10.5K 14K 18.7K

THERMAL IC ALERT#
2K 77'C 87'C 97'C 107'C 117'C
7.5K 79'C 89'C 99'C 109'C 119'C
10.5K 81'C 91'C 101'C 111'C 121'C
Place under CPU 10/20mils

+3.3V_RUN 14K 83'C 93'C 103'C 113'C 123'C
C REM_DIODE1_P C
C183 U4
3
C49 1 8 18.7K 85'C 95'C 105'C 115'C 125'C

VDD SCL SMBCLK3 [19,22]
Q25 2 *2200P/50V/X7R_4_NC 2200P/50V_4
MMST3904-7-F 2 7 SMBDAT3 [19,22]
2
DP SDA
1
50 REM_DIODE1_N 50 3 6 THERM_ALERT#
DN ALERT#
+3.3V_ALW 4 5
SYS_SHDN# GND
NCT7718W
1
RT1
10K/NTC_6 C54
0.1U/16V_4 SYS_SHDN#
OTP 85 degree C
2
2
T_CPU
[22] T_CPU
+3.3V_RUN R41 1 2 18.7K/F_4 THERM_ALERT#
R40 1 2 2K_4 SYS_SHDN#

R44
1K_4 Q15
PMF780SN OTP 85 degree : R92 = 18.7K, R95 = 2K
Need closed to CPU
D 1 3 THERM_STP# [22,30] D
2
[8,22,37] IMVP_PW RGD

1
C53
*100P/50V/NPO_4_NC PROJECT : D13
2

1A
FAN & THERMAL
7
Sheet 28
8
of 41
1 2 3 4 5 6 7 8
fix
vina
A A
CN2
56
+5V_ALW 1 54 +5V_FAN1
2 53 +5V_RUN
3 52
4 51
5 50
6 49 +3.3V_SUS
+3.3V_ALW 7 48 +3.3V_RUN
USB_PS_SELCDP 8 47 USBP1+
[13] USB_PS_SELCDP 9 46 USBP1+ [11]
USB_CHG_DET# USBP1- USBP1- [11] Ddifferent impedance=85 ohm
[26] USB_CHG_DET# 10 45
USB_OC0#
[11] USB_OC0# 11 44
USB_BACK_EN# BAT_LED_W HITE
[22] USB_BACK_EN# 12 43 BAT_LED_W HITE [22]
USBP0_BUS_SW _CB0 BAT_LED_AMBER
[22] USBP0_BUS_SW _CB0 13 42 BAT_LED_AMBER [22]
POW ER_SW _IN0#
[26] POW ER_SW _IN0# 14 41 AUD_SPK_R+
FAN1_TACH 15 40 AUD_SPK_R-
[22] FAN1_TACH 16 39 trace width=1mm
LID_SW #
[22] LID_SW # 17 38 PCH_AZ_CODEC_RST#
18 37 PCH_AZ_CODEC_RST# [10,22]
PCH_AZ_CODEC_SYNC
19 36 PCH_AZ_CODEC_SYNC [10]
PCH_AZ_CODEC_SDIN0
20 35 PCH_AZ_CODEC_SDIN0 [10]
PCH_AZ_CODEC_BITCLK
21 34 PCH_AZ_CODEC_BITCLK [10]
DMIC_DATA PCH_AZ_CODEC_SDOUT
[19] DMIC_DATA 22 33 PCH_AZ_CODEC_SDOUT [10]
DMIC_CLK
B [19] DMIC_CLK 23 32 NB_MUTE# B
24 31 NB_MUTE# [22]
ACZ_SPKR
25 30 ACZ_SPKR [10]
BEEP
26 29 BEEP [22]
55
27 28
0805 NO.23 C16407-150A8-L
+3.3V_ALW
08/01: change CN4 PN from DFHD02MR401 change to
DFHD02MR045
2
R60
100K_4
C C
1
100P/50V_4
CN4
LID_SW # EC13
[22] LID_SW #
ER9 *SJ0603_NC
AUD_SPK_R+ 1 2 1
AUD_SPK_R- 1
1 2 2 2
ER8 *SJ0603_NC
1
EC12
C65 88266-02001
0.1U/16V_4 100P/50V_4
10/04 NO.7
2
16
D D

PROJECT : D13
1A
BTB connector
7
Sheet 29
8
of 41
1 2 3 4 5 6 7 8
fix
vina
A A
+3.3V_RUN
R50
B 10K_4 B
R53 *SJ0402_NC
[35] 1.05V_PCH_PW RGD
R54 *SJ0402_NC HW PG
[36] VCCSA_PW RGD HW PG [8,22]
[34] 1.5V_SUS_PW RGD

R52 *SJ0402_NC 1 C59
100P/50V_4
2
10/04 NO.7
R69 *SJ0402_NC
THERM_STP# [22,28]
C C
R70 *SJ0402_NC
[33] +3.3V_EN2 3.3V_ALW _ON [26]
10/04 NO.7
D D

PROJECT : D13
1A
System Reset Circuit
4 5 6
7
Sheet 30
8
of 41
5 4 3 2 1
fix
vina
Need to add in BOM
H7 H8 H6 H10
D h-tc217bc197d102p2 h-tc217bc197d102p2 h-tc217bc197d102p2 H-C220D142P2 D
1
H4 H-C220D142P2
h-tc217bc197d102p2 h-tc217bc197d102p2 h-tc217bc197d102p2
h-tc166i131bc177d91p2
H11 H12
1
h-tc217bc197d102p2 h-tc217bc197d102p2
*h-tc166i131bc177d91p2_NC
BOT-Size
Need to modify PN
1
h-tc217bc197d102p2
h-tc217bc197d102p2
H3
TOP-Size
H-TC197BC221D91P2
1
*H-TC197BC221D91P2_NC
C C
H1
H-C79D79N H9
H-TC197I131BC220D91P2
H5
1
H-C217D91P2
*H-C79D79N_NC
1
*H-TC197I131BC220D91P2_NC
1
*H-C217D91P2_NC
09/30: NO.6
H2
h-o79x87d79x87n
1
B *h-o79x87d79x87n_NC B
A A

PROJECT : D13
1A
SCREW PAD
1
31 of 41
A B C D E
fix
vina +PWR_SRC +DC_IN
PQ25 PQ14
FDMC4435BZ FDMC4435BZ
8 1 PR145
(1) 1 8
+DC_IN_SS +DC_IN_SS 7 2 +DC_IN_SS_P 2 1 2 7
2 1
6 3 2P 2P 1P 1P 3 6
1
5 5 1
0.01/F_0612
1
4
4
1
1
PR143 PR144 PC56 PC57 +DC_IN_SS
10K_4 100K_4 *0.1U/25V_6_NC *2200P/50V_4_NC
1
PR50 PR169
CSSN
2 1 2 1
CSSP
1 2 22_8 *22_8_NC
PC44 PC142 10U/25V_12 PR57
2
0.1U/50V_6 470K_4
3
1 2 1 2
2
CHG_DCIN
ACAV_IN PQ28 PC55 0.1U/50V_6
2
PMF780SN
(2)
1 2
1
1
PC50 2200P/50V_4 PL5
PC42 PC46 4.7UH (PCMC063T-4R7MN) PR142
0.1U/50V_6 *0.1U/50V_6_NC 1 2 2 1 +VCHGR
2
2 1
2P 2P 1P 1P
0.01/F_0612
35
34
33
32
31
30
1
CHG_SW
TP
PHASE
PHASE
PGND
PGND
PGND
PR147 PR149 PR151 PC40 PC136 PC140
*SJ0402_NC 18.7K/F_4 100K_4 0.1U/50V_6 10U/25V_12 10U/25V_12
1
2 2 1 1 2 1 CHG_ICREF 2 1 +3.3V_ALW 1 29 CHG_SW 1 2
PGND PHASE PC54
1
2 28 2200P/50V_4
2
DCIN_P PHASE PC143 PD3 PC149 PC151
(21) 3 27 PR148 0.1U/50V_6 SDM10K45-7-F 0.1U/50V_6 *0.1U/50V_6_NC
2
DCIN_P PHASE
1
1_6
4 DCIN_P BOOT 26 CHG_BOOT 1 2 1 2 PR55
2 +DC_IN_SS 2.2_8 2
5 CSSN DCIN_A 25 CHG_DCIN 1 2 PC147
PC145 0.47U/25V_6 1U/25V_6
2
1
PC144 6 CSSP VDDP 24 CHG_VDDP 1 2

PR153 1U/6.3V_4
316K/F_4 2 1 CHG_VREF 7 23 CHG_ICOUT
VREF PU7 ICOUT
CHG_ICOUT 2 1 CHG_ICREF 8 BQ24765RUVR 22 CSOP
2
1.5M_4 PR150 ICREF CSOP

CHG_ACIN 9 21 CSON
ACIN CSON
2 1 2 1 2 1 CHG_EAO 10 20 CHG_VFB 1 2
2200P/50V_4 PC148 7.5K/F_4 PR154 EAO VFB PR155 100_4
1
PR156 CHG_EAI 11 19 PC154

PR152 PC146 200K/F_4 EAI AGND 0.1U/50V_6
49.9K/F_4 *0.01U/25V_4_NC CHG_FBO 12 18 1 2
VDDSMB
ACAV_IN [22,26]
2
FBO ACOK SR1
1
PC155 PR160 PC150
VICM
1 2
SDA
2
1 2
SCL
120P/50V_4 4.75K/F_4 56P/50V_4 PR159
CE
2 1 2 1 2 1 CHG_EAO 10K_4
13
14
15
16
17
AGND_CHG
2
CHG_VREF
PR158
1
1
PC157 +3.3V_ALW
0.1U/16V_4
2
10K_4
PR157
2
3 3
10K_4
PC156 1 2
1
100P/50V_4
2 1 IMVP7_PROCHOT# [4,22,37]
PR43 PR47
10K_4 100K_4
[22] IINP
3
[22,38] SMBDAT0
5 PQ11A
DMN66D0LDW-7
6
[22,38] SMBCLK0
4
CHG_ICOUT 2 PQ11B
DMN66D0LDW-7
1
1
1
PC37 PC39
*100P/50V_4_NC *100P/50V_4_NC
2
Adapter Type 45W
OCP Set Point 2.7A
4 4

PROJECT : D13
1A
Charger (BQ24765RUVR)
A B C D E
http://vinafix.vn
5 4 3 2 1
f ix
v ina
+PWR_SRC
+PWR_SRC
1
D D
PC161 PC160 PC21 PC22 PC24 PC26 PC159
10U/25V_12 10U/25V_12 0.1U/50V_6 2200P/50V_4 +5V_ALW2 2200P/50V_4 0.1U/50V_6 10U/25V_12
2
PR162
5V_DH TP9 *SJ0402_NC TP1 3P3V_DH
2 1
5V_DL 2 1 3P3V_DL
TP10 TP8
PQ31 PC23
8
7
6
5
FDMC8884 10U/6.3V_6 AGND_DC/DC +3.3V_ALW
5
6
7
8
+5V_ALW 4
PQ29 TDC : 2.402A
4 (4)
TDC : 3.894A PC20
0.1U/50V_6
PR30
3.3_6
PR33
3.3_6
PC28
0.1U/50V_6
FDMC8884
OCP: 4.72A
3
2
1
(3) OCP : 7.84A 2 1 2 1 1 2 1 2
1
2
3
PL8 PL7
2.2UH (FDV0530S-H-2R2M=P3) 3.3UH (MMD-05CZ-3R3M-M2Q)
3P3V_BST
5V_LX +3.3V_LX
5V_BST
+5V_ALW +3.3V_ALW
1
5V_DL 3P3V_DL
1
SJ27 SJ26 SJ2
1
SJ28 SJ29 *SJ0201_NC *SJ0201_NC *SJ0201_NC
8
7
6
5
2
32
31
30
29
28
27
26
25
*SJ0201_NC *SJ0201_NC
1
5
6
7
8
1
2
2
+ + +
2
SJ1 PC163 PC162 PC9 4 41 40 PC33 PC158
1
SW1
VBST1
DRVL1
VREG5
DRVL2
VBST2
SW2
GND
2
2
*SJ0201_NC 220U/6.3V/E25_7343 220U/6.3V/E25_7343 0.1U/16V_4 PAD PAD PQ30 0.1U/16V_4 150U/6.3V/E25_3528
2 42 39 4
2
PAD PAD
1
2
PQ32 FDMC8884
1
FDMC8884 5V_DH 1 24 3P3V_DH PR39
2
3
2
1
PR21 DRVH1 DRVH2 +3.3V_RTC_LDO 2.94K/F_4
1
2
3
4.99K/F_4 +5V_ALW 2 23 +PWR_SRC
V5SW VIN
2
2 1 3 22
2
PR23 300K/F_4 PR26 RF VREG3 PR37
1K/F_4 +5V_EN1 4 21 +3.3V_EN2 PC30 1K/F_4
EN1 PU2 EN2
C 2 1 2.2U/6.3V_6 1 2 C
PR25 5 TPS51220ARTVR 20 PR36
0_4 PGOOD1 PGOOD2 0_4
PC18 VREF2 2 1 6 19 1 2 VREF2 PC29
0.1U/16V_4 SKIPSEL1 SKIPSEL2 0.1U/16V_4
2 1 5V_CSP 7 18 3P3V_CSP 1 2
CSP1 CSP2
5V_CSN 8 17 3P3V_CSN
CSN1 CSN2
COMP1
COMP2
33 38
VREF2
PAD PAD
FUNC
VFB1
VFB2
34 37
TRIP
PAD PAD
EN
35 36
PAD PAD
PR22 PR35
10
11
12
13
14
15
16
120K/F_4 62K/F_4
5V_VFBP 1 2 5V_VFB 3P3V_VFB 1 2 3P3V_VFBP
5V_COMP 3P3V_COMP
1
PR27
1
(18) 28.7K/F_4 VREF2
1
PC19 PR28 PR38 +3.3V_EN2
+3.3V_EN2 [30]
1
*100P/50V_4_NC 18K/F_4 27K/F_4
2
PC25 PR34 PC27
2
0.22U/6.3V_4 12K/F_4 *220P/50V_4_NC
2
2
VREF2 VREF2
(17) PR29
*SJ0402_NC PR32
+3.3V_RTC_LDO 1 2 *SJ0402_NC
1 2
1 2 +5V_ALW2
PR31 1 2
*SJ0402_NC
1 2
B 1 2 B
+5V_ALW2
PC16
0.1U/50V_6 BAT54S-7-F
2 1 1 PC14
0.1U/50V_6
PD2 3 2 1
PC12
+15V_ALW 0.1U/50V_6
PQ2 2 1 1 PC13
DDTA114YUA-7-F 0.1U/50V_6
PD1 3 2 1
3 1 +15V_ALWP 2
47K
10K
BAT54S-7-F
1 PC8
3 2
0.1U/50V_6
2
PR20
*SJ0402_NC
1 2 +5V_EN1 2
[22,26] ALW_ON 1 2
PQ4
A PMF780SN A
1

PROJECT : D13
1A
3.3V_ALW/5V_ALW(TPS51125ARGER)
http://vinafix.vn
5 4 3 2 1
5 4 3 2 1
fix
vina
D D
[30] 1.5V_SUS_PWRGD
PR168
*0_4_NC
2
[8,20,22] SLP_S4# 1 2 (6) +PWR_SRC
PR44 PR45 PR46
0_4 200K/F_4 51K/F_4
1 2 1P5V_S5
[8,22] SIO_SLP_S5#
1
PR41
1P5V_TRIP
1P5V_MODE
1
10K_4
1 2 1P5V_S3 PC38 PC36 PC152 PC153
[8,22] SIO_SLP_S3# 0.1U/50V_6 10U/25V_8 10U/25V_8
1P5V_DH 2200P/50V_4
TP3 +1.5V_SUS
2
1P5V_DL
PC41
TP2 1.5 Volt +/- 5%
TDC : 8.75A
17
16
20
19
18
0.047U/10V_4
24 OCP : 12.5A
S3
S5
PGOOD
MODE
TRIP
5
6
7
8
PwPd
25
PwPd
23
PwPd PQ27
For power sequence PwPd
26 4
+1.5V_SUS
22 PR48 PC45 FDMC7696
PwPd 0.1U/50V_6
C
1P5V_VBST
2.2_6 (8) C
4 15 1 2 1 2 (5)
1
2
3
VTTGND VBST
PR51 1 14 1P5V_DH PL6
*SJ0402_NC VTTSNS DRVH 1UH (PCMC063T-1R0MN)
2 1 +0.75V_DDR_VTT_P 3 TPS51216RUKR 13 1P5V_LX
+0.75V_DDR_VTT 2 1 VTT SW
PU3
+DDR_VTTREF 5 11 1P5V_DL
1
VTTREF DRVL
1
1P5V_VLDOIN 2 12 1P5V_V5IN 2 1 +5V_ALW PC48

VLDOIN V5IN 2 1
1
5
6
7
8
1
PC53 2200P/50V_4
1
PC47 0.22U/6.3V_4 *SJ0603_NC SJ3 + PR58
1
2
1
PR52
VDDQSNS
10U/6.3V_6 4 PQ26 *SJ0201_NC PC139 PC141 *SJ0402_NC
2
2
PC49 FDMC7672S 0.1U/16V_4 220U/2.5V/E15_3528
(7)
2
1
REFIN
PGND
VREF
PwPd
1U/6.3V_4
GND
2
PC43 PR49
1
2
3
10U/6.3V_6 2.2_8
2
10
21
2
1P5V_VDDQSNS
1
PR53
10K/F_4
2
1
1
PR54
PC51 49.9K/F_4 PC52
0.1U/16V_4 0.01U/25V_4
2
2
2
B B
A A

PROJECT : D13
http://vinafix.vn
1A
1.5_SUS/0.75_DDR_VTT
5 4 3 2 1
1 2 3 4 5
afix
v i n
A A
PR137
(11) (10) +PWR_SRC
10_6 +1.05V_VCCIO
+5V_SUS 1 2 1P05V_VCC PR134
*SJ0402_NC
1.05 Volt DC +/- 2%
1 1 2 2 +5V_SUS TDC : 10.15A
1
PC138
OCP : 14.5A
1
4.7U/6.3V_4
PC134 PC131 PC132 PC133
2
1P05V_DH 2200P/50V_4 0.1U/50V_6 10U/25V_12 10U/25V_12
TP5
2
1P05V_DL
11
TP4
5
6
7
8
PR135
VCC
G0
73.2K/F_4
2 1 1P05V_CS 10 CS UGATE 3 1P05V_DH 4 PQ23
B PR136 PC135 FDMC7696 (9) B
0_6 0.1U/50V_6
9 4 1P05V_BST 1 2 1 2
[30] 1.05V_PCH_PWRGD
1
2
3
PR138 PGOOD BOOT PL4
*SJ0402_NC PU6 1UH (PCMC063T-1R0MN)
1 1 2 2 1P05V_EN 8 RT8240BZQW 2 1P05V_LX +1.05V_VCCIO
[22,36,39] RUN_ON EN PHASE
13 1 1P05V_DL
PAD LGATE
5
6
7
8
1
RGND
VOUT
GND
PC66 PR131
1
4 PQ24 2200P/50V_4 *0.01/F_0612_NC
1
PC137 FDMC7672S + +
12
1
*0.047U/25V_4_NC PC129 PC128 PC127
2
PR139 0.1U/16V_4 330U/2.5V/E9_3528 *330U/2.5V/E9_3528_NC 2 1 +1.05V_PCH
1
2
3
2
1
*10_4_NC
PR72
2
2.2_8
2
C C
PR140
*SJ0402_NC
1 1 2 2 VCCIO_SENSE [6]
PR141
*SJ0402_NC
1 1 2 2 VSSIO_SENSE [6]
1
PR132
*10_4_NC
2
D D

PROJECT : D13
1A
1.05V_VTT/1.05V_PCH
1 2 3 4 5
http://vinafix.vn
5 4 3 2 1
f ix
vina
PR63 +PWR_SRC
10_6
+5V_SUS 1 2 VCSA_VCC
1
1
D PC67 PC130 D
PC61 PC68
4.7U/6.3V_6 2200P/50V_4 0.1U/50V_6 10U/25V_12
+VCCSA_CORE
2
2
0.9 Volt +/- 5%
5
6
7
8
12
13
5
VCCSA_DH PQ22
Fsw : 300K
4
VCC
GND
PAD
PR66 FDMC8884 TDC : 6A
56.2K/F_4
2 1 VCCSA_CS 11 3 PR65 PC65
(12) OCP : 8.6A
1
2
3
CS UGATE 0.1U/50V_6
0_6
VCCSA_BST 1 PL3
9 PU4 BOOST 4 2 1 2
1UH (PCMC063T-1R0MN)
(13)
[30] VCCSA_PWRGD PGOOD
PR60 RT8241EZQW 2 VCCSA_LX +VCCSA_CORE
*SJ0402_NC PHASE
1 1 2 2VCCSA_EN 6 EN LGATE 1
5
6
7
8
1
[22,35,39] RUN_ON
1
PC69 +
VCCSA_DL 4 PQ21 *2200P/50V_4_NC PC125 PC126
G0
G1
FB
2
1
FDMC7692S 0.1U/16V_4 330U/2.5V/E9_3528
2
1
PC60
10
1
*0.047U/25V_4_NC TP6 VCCSA_DH
1
2
1
2
3
PR75
2
TP7 VCCSA_DL PR73 *SJ0402_NC
*2.2_8_NC
2
2
1
PR64
*0_4_NC
1
C PR62 VCCSA_FB 2 1 C
VCCSA_SENSE [6]
2
*SJ0402_NC
2
VCCSA_VID1 [6]
(19)
1
PR61
1K_4
2
VCCSA_VID1 VCCSA_CORE
Low 0.9V
High 0.85V
B B
PL10
+5V_ALW 2.2UH (FDV0530S-H-2R2M=P3)
4 PGOOD LX1 1 +1.8V_RUN
9 PVIN LX2 2
1
1
10 PVIN LX3 3 R1
PC7 PR15
PR13 PU8 7 *22P/50V_4_NC 2 20K/F_4 +1.8V_RUN
NC
10_6 RT8068AZQW
1.8 Volt +/- 5%
1
1 2 8 SVIN FB 6
RUN_ON
PC5
0.1U/16V_4
PC170
10U/6.3V_8
PC171
10U/6.3V_8
TDC : 1.23A
11 5 1 2
2
GND EN 1 2
1 OCP : 3.5A
1
*SJ0402_NC
R2
1
PC166 PC164 PC6 PR12 PR14

10U/6.3V_8 0.1U/16V_4 1U/6.3V_4 PC4 10K/F_4
2
*0.047U/25V_4_NC Vout =0.6(1+R1/R2)

2
=1.8V
A A

PROJECT : D13
1A
VCCSA_CORE/1.8V_RUN
5 4
http://vinafix.vn 3 2
1
36 of 41
5 4 3 2 1
f ix
ina
+PWR_SRC
v UGG
1
PC82 PC83 PC117 PC115 PC116
2200P/50V_4 0.1U/50V_6 10U/25V_12 10U/25V_12 10U/25V_12
2
PC79 PQ20
PR86
2
D FDMS3604S D
0_6 0.22U/25V_6
G1
D1
D1
D1
PC71 BOOTG 1 2 1 2 +VCC_GFX_CORE
*330P/50V_4_NC PL2
2 1 0.36UH (ETQP4LR36AFM)
VCC_AXG_SENSE [6] 1 2
S1/D2
1
PC78 PHG 9
0.01U/25V_4 PC114
VSS_AXG_SENSE [6]
1
1000P/50V_4
1
2 1
2
G2
1
S2
S2
S2
SJ25 SJ24 + +
1
R8 change to 1 *SJ0201_NC
*SJ0201_NC PC124 PC122 PC121
5
1
2
PR85 PC80 0.1U/16V_4 330U/2V/E6/H1.4_7343 330U/2V/E6/H1.4_7343
2
169Kohm for GT1
2
6.98K/F_4 1000P/50V_4
2
287Kohm for GT2 PR122
2
R5 Place near high side mosfet of AXG 2.2_8
2
2
R5 LGG
PR76 PR128 PR126
20K/F_4 470K/NTC_4 3.83K/F_4
2 1 1 2 1 2
1
PC74 PR80 PC72

1
PR84 68P/50V_4 210/F_4 1200P/50V_4 PR125 PR77

287K/F_4 PC70 2 1 2 1 2 1 27.4K/F_4 1.87K/F_4
330P/50V_4 1 2 ISPG 1 2
2
R8
2
PC73 PR78 PR81
1
330P/50V_4 140K/F_4 2.55K/F_4
PR79
ISPG
ISNG
NTCG
BOOTG
UGG
PHG
LGG
2 1 2 1 2 1 2.61K/F_4
1
R7
2
PC77 PC81 PR83
0.15U/10V_4 0.047U/10V_4 11K/F_4
40
39
38
37
36
35
34
33
32
31
1
R7 change to R6 change to
2
+3.3V_SUS PR129
COMPG
FBG
RTNG
ISUMPG
ISUMNG
NTCG
BOOTG
UGATEG
PHASEG
LGATEG
1.78Kohm for GT1 931ohm for GT1 10K/NTC_6
R6
2.55Kohm for GT2 1.65Kohm for GT2
C 1 30 PR87 R4 PR82 C
2
VWG NC 1.65K/F_4 1_4
1
29 ISNG 1 2 1 2
NC
PR121 PR127 IGFX_PWRGD 2 28
1.91K/F_4 1.91K/F_4 PGOODG NC PR88 PC75 PC76 R4 Place near AXG choke
VR_SVID_DATA 3 *100_4_NC *220P/50V_4_NC 0.1U/16V_4
2
[6] VR_SVID_DATA SDA

1 2 1 2 1 2
4 27 PR89
[6] VR_SVID_ALERT# ALERT# NC *SJ0603_NC
IGFX_PWRGD VR_SVID_CLK 5 26 2 1 +5V_SUS
[6] VR_SVID_CLK SCLK VCCP 2 1
PU5
PR167 1 2 *SJ0402_NC 6 25
[22] IMVP_VR_ON
1
1 2 VR_ON ISL95837HRZ-T NC +PWR_SRC
IMVP_PWRGD IMVP_PWRGD 7 24 LGATE1 PC85 PC84
(14)
[8,22,28] IMVP_PWRGD PGOOD LGATE1 1U/6.3V_4 1U/6.3V_4
2
+1.05V_VCCIO
(20) UGATE1
8 23 PHASE1
[4,22,32] IMVP7_PROCHOT# VR_HOT# PHASE1
PR118 PR106 9 22 UGATE1
1
1
3.83K/F_4 470K/NTC_4 NTC UGATE1
2 1 2 1 10 21 BOOT1 PC96 PC98 PC112 PC110 PC111
PR124 PR123 VW BOOT1 2200P/50V_4 0.1U/50V_6 10U/25V_12 10U/25V_12 10U/25V_12
2
130/F_4 54.9/F_4 R2
ISUMN
ISUMP
COMP
41
VDD
RTN
2
PAD PQ19
VIN
NC
NC
NC
PR120 PC86
FB
PR91
2
27.4K/F_4 0.22U/25V_6 FDMS3604S
0_6
G1
D1
D1
D1
VR_SVID_CLK 2 1 BOOT1 1 2 1 2 +VCC_CORE
11
12
13
14
15
16
17
18
19
20
PL1
R2 Place near high side mosfet of Vcore 0.24UH (ETQP4LR24AFM)
VR_SVID_DATA 1 2
S1/D2
1
PR94 PHASE1 9
1
*SJ0603_NC PC97
1
1
2 1 1000P/50V_4 SJ30 SJ31
1
+PWR_SRC
2
G2
1
S2
S2
S2
PR109 PC100 2 1 *SJ0201_NC *SJ0201_NC + + +
6.98K/F_4
2
1000P/50V_4 PC118 PC120 PC123 PC119
2
1
PR102 0.1U/16V_4 330U/2V/E6/H1.4_7343 330U/2V/E6/H1.9_7343 330U/2V/E6/H1.4_7343
2
1_6
2
B B
2 1 +5V_SUS PR95
2.2_8
2
1
PC87
PC93 0.22U/25V_6 LGATE1
VSUM+_P
VSUM-_P
1U/6.3V_4
2
PC88 PR97 PC95

68P/50V_4 249/F_4 1000P/50V_4
1 2 1 2 1 2
1
PR111
1.87K/F_4
R1 PR105 VSUM+ 1 2
PR96 PC94 PR98 PR101 2.61K/F_4
2.37K/F_4 330P/50V_4 165K/F_4 2.15K/F_4
1 2
1
2 1 1 2 1 2 1 2
PC90 PC92 PR100 PR110
0.22U/6.3V_4 *0.068U/10V_4_NC 11K/F_4 PR119 1_4
2
10K/NTC_6 VSUM- 1 2
PC102 PR104
2
330P/50V_4 4.99K/F_4 PR99 R3

2
2 1 2 1 1.21K/F_4 R3 Place near Vcore choke

PC103 2 1
*330P/50V_4_NC
2 1
1
PC91 PR92
[6] VCCSENSE
PC89 *330P/50V_4_NC *100_4_NC PC101
0.01U/25V_4 2 1 2 1 0.1U/16V_4
[6] VSSSENSE
2
2 1
R1=2.37K: set Vboot=0V & IFL=33A

R1=294K: set Vboot=1.1V & IFL=33A
A
NOTE 1: GT1 GT2 A
AXG Core power: Loadline ~-4.6mOhm
OCP~22A R6 931 / CS19312FB11 1.65K / CS21652FB29
CPU Core power: Loadline ~-2.9mOhm 1.78K / CS21782FB00 2.55K / CS22552FB01
OCP~40A R7
R8 169K / CS41692FB12 287K / CS42872FB13
PROJECT : D13
1A
VCC_CORE/iGPU_CORE
5 4 3 2 1
http://vinafix.vn
A B C D E
fix +VCHGR
ina
PC64
0.1U/50V_6
v
2 1
PC63 +3.3V_ALW
1000P/50V_4
2 1
PC62
2
2200P/50V_4
2 1 +3.3V_ALW
1 1
FOX_GS73091-10272-7H PD7 PD8 PD9
3
*DA204UGT106_NC *DA204UGT106_NC *DA204UGT106_NC
2 B9
2
1 A9
B8 PR70
A8
B7 1 2 SMBCLK0 [22,32] 10K_4
PR67 100_4
1
A7
B6 1 2 SMBDAT0 [22,32]
PR68 100_4
A6 +DCIN_JACK
B5 1 2 PBAT_PRES# [22]
PR69 100_4
A5
B4
A4
B3
A3
B2
A2
B1
1
A1 EC14 EC15 EC16
JBAT1 0.01U/50V_4 4700P/50V_4 68P/50V_4
2
2 2
Reserve for EMI Solution
+DC_IN +DC_IN_SS
PQ18
FL2 FDMC4435BZ
MHC2012S800UBP(80,5A)
1 2 +DC_IN 1 8
2 7
3 6
1
5
1
1
1
PC109 PC108 PR117
4
PC105 PC113 PC107 PC106 PC99 PR108 0.01U/25V_4 0.1U/50V_6 10K_6
2
2200P/50V_4 1000P/50V_4 0.1U/50V_6 0.1U/50V_6 0.47U/25V_6 240K_4
2
2
2
6 PQ15
4
IMD2A GZ T108
1
PR103
*10K_4_NC
+3.3V_ALW 1 2 PR107
AC_OFF [22]
47K_4
3 3
2
+DC_IN_SS +DC_IN
+5V_ALW2 +3.3V_ALW
9/30: CN1 change from D (23)

DFHD05MR080 to DFHD05MS074
1
1
1
EC7 EC3
CN1 6 50278-0050n PR115 EC6 1000P/50V_4 *10P/50V_4_NC
2
GND 2.2K_4 0.1U/25V_4
2
+DCIN_JACK
Adapter2+ 5
2
PQ17 PD5
3
4 FL1 FDV301N_G PR116 DA204UGT106

Adapter1+ BLM11B102S (1K,100MA) 33_4
3 DOCK_PSID 1 2 3 1 1 2
PSID PS_ID [22]
1
2 PR112
Adapter2- 10K_4
2
PR114
Adapter1- 1
100K_4
2 1 +5V_ALW2 Reserve for EMI Solution
1
GND
2
1
4 7 2 PQ16 4
PC104 MMST3904-7-F
1
PD4 100P/50V_4
2
*BAS316_NC
2
PR113
15K_4

2
PROJECT : D13
1A
DCIN/BATT CONNECTOR
A B
http://vinafix.vn C D
E
38 of 41
1 2 3 4 5
f ix
ina
+5V_ALW 2 +15V_ALW +5V_ALW +5V_RUN
v PQ5 +5V_ALW 2 +15V_ALW +5V_ALW +5V_SUS +5V_SUS

FDMC8884 +5V_RUN PQ1
FDMC8884
Max Current : 1.5A
8 3 Max Current : 1.86A
1
7 2 8 3
1
6 1 7 2
PR24 PR19 5 6 1
1
100K_4 100K_4 PR18 PR17 5
1
PC15 100K_4 100K_4
4
0.1U/16V_4 PC10
4
0.1U/16V_4
2
3
1
A A
1
RUN_ON# 5 PQ6A PC17
DMN66D0LDW -7 4700P/25V_4 SUS_ON# 5 PQ3A PC11
2
6
DMN66D0LDW -7 4700P/25V_4
2
6
2 PQ6B
[22,35,36] RUN_ON
4
DMN66D0LDW -7 2 PQ3B
[22] SUS_ON
1 DMN66D0LDW -7
1
+15V_ALW +3.3V_ALW +3.3V_RUN
PQ9 +3.3V_RUN
FDMC8884
8 3
Max Current : 2.24A
1
7 2
6 1
PR42 5
1
100K_4
PC34
4
0.1U/16V_4
2
+15V_ALW +3.3V_ALW +3.3V_SUS
+3.3V_SUS
3
PQ8
1
FDC655BN_G
2
PC35 6
Max Current : 0.13A
1
PQ10 0.047U/25V_4 5 4
2
PMF780SN 2
PR40 1
1
100K_4
PC31
3
0.1U/16V_4
2
+15V_ALW +1.5V_SUS +1.5V_RUN
+1.5V_RUN
1
B PQ13 B
FDC655BN_G PC32
6
Max Current : 0.5A 2
0.047U/25V_4
2
1
5 4 PQ7
1
2 PMF780SN
PR59 1
1
100K_4
PC59
2
3
0.1U/16V_4
2
3
2 PC58
0.047U/25V_4
2
PQ12
1
PMF780SN
PR163
*0_12_NC
1 2
+LED_BL
+PW R_SRC
Q51 +LED_PW RSRC PD6
AO3409 PL9 RB060M-60GTR
(15)
10UH (#A915AY-H-100M=P3)
1 3 1 2
C C
1
PC172
1
PR165 0.1U/25V_4 PC165 PR9
2
240K_4 10U/25V_12 10_6 PC168 PC169 PC167

2
4.7U/50V_12 4.7U/50V_12 4.7U/50V_12

2
2
1
2
7 8 PR11
VIN LX 2M/F_4
1
2
PC3 LX
PR164 1U/25V_6
1
47K_4 12
OVP
2
1
3
PR10
2 5 75K/F_4
[22,35,36] RUN_ON [19] LCD_PW M_OUT PWM RT8510GQW
2
PQ33 PU1
1
PMF780SN
[22] LCD_BAK 6
EN (16)
2 COMP CH1 13 IFB1 [19]
1
CH2 14 IFB2 [19]

4
1
PR5 RT
15 IFB3 [19]
100K_4 CH3
D D
PR3 3 16 IFB4 [19]
2
ISET CH4
PGND
PGND
AGND
10K/F_4
PAD
1
PC2
2
1000P/50V_4
PR1 PR2
2
10
11
17
1
49.9K/F_4 3.92K/F_4
PC1
2
0.01U/25V_4
2
PROJECT : D13
http://vinafix.vn
1A
PR2 has been changed to 3.92K at ST build Load Switch/LED_BL_Converter
1 2 3 4 5
1 2 3 4 5 6 7 8
fix +3.3V_SUS +3.3V_RUN
vina 202
A0
2.2K 2.2K 2.2K 2.2K 200 SO-DIMM 0
+3.3V_RUN
H14 SMBCLK TP_SCLK 202
2N7002
C9 SMBDATA TP_SDATA 200
A4
A
SO-DIMM 1 A
2N7002
0 ohm_NC
+3.3V_SUS +3.3V_RUN
10h
Touch PAD
PCH 2.2K 2.2K

C8 SML0CLK
G12 SML0DATA
+3.3V_SUS
2.2K 2.2K
B Function IC SMBus Address B
E14 SMB_CLK_ME1
DIMM0 A0
M16 SMB_DATA_ME1
DDR3
DIMM1 A4
+3.3V_ALW Thermal IC EMC2112 1001_100xb (22h)
+3.3V_SUS
+3.3V_SUS
Charge IC BQ24765RUVR 0b0001001x (0x12)
2N7002
2N7002
Battery Battery 16h
WLAN WLAN Module X
10K 10K Touch PAD Touch PAD 10h
115 SMBDAT1
ALS LTR-328ALS-01 0X52
116 SMBCLK1
+3.3V_ALW
100
C 3 C
4
16h
4.7K 4.7K Battery
SIO 110 SMBCLK0
100
15
12
ITE8518E 111 SMBDAT0 16 Charger
+3.3V_RUN
2.2K 2.2K
94 SMBCLK3 15
2E
95 SMBDAT3 14
THERMAL(EMC1422)
D 17 D
16 ALS 0X52
PROJECT : D13
1A
SMBUS
4 5 6
7
Sheet 40
8
of 41
5 4 3 2 1
a fix
vin Adapter 65W VER : 1A
Charger
BQ24707ARGRR PWR_SRC
D D
Battery 3S2P
+3.3V_EN2 ALW_ON
TI
TPS51125ARGER
+15V_ALW
+3.3V_ALW +5V_ALW
C C
SUS_ON
SUS_ON SUS_ON
Load Switch Load Switch Richtek

FDC655BN FDC655BN RT8207AGQW
+3.3V_SUS +5V_SUS +1.5V_SUS +0.75V_DDR_VTT
B B
RUN_ON RUN_ON IMVP_VR_ON

RUN_ON RUN_ON RUN_ON RUN_ON
Load Switch RichTek Load Switch Load Switch Richtek Richtek Onsemi
TPCC8065 RT8068AZQW TPCC8065 FDC655BN RT8241DGQW RT8240BGQW NCP6132A
+3.3V_RUN +1.8V_RUN +5V_RUN +1.5V_RUN +VCCSA_CORE +1.05V_PCH +VCC_CORE +VCC_GFX_CORE
A A

PROJECT : D13
1A
Power Block Diagram
5 4 3 2 1
http://vinafix.vn

Spyder 13.3

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1 2 3 4 5 6 7 8

FDI LINK DMI LINK

SINGLE CHANNEL LVDS LCD CONN

Keyboard Conn. LPC

Quanta Computer Inc.

Quanta Computer Inc.

PEG_RX[0] K22 PEG_ICOMPI and RCOMPO signals should

PCI EXPRESS -- GRAPHICS

Quanta Computer Inc.

BF44 SM_RCOMP_0 R172 140/F_4 +1.05V_VCCIO

IMVP7_PROCHOT# R168 62_4

PRDY# N53 T57

JTAG & BPM

[13] H_PW RGOOD B46 UNCOREPWRGOOD

SM_DRAMPW ROK BE45 G58 Boot S3 S3 RSM

Pin1 Pin2 Pin4

[8,22] EC_PW ROK 1 2 74AHC1G09GW R124

+3.3V_SUS R81 1K_4 C73 4.99K/F_4

Quanta Computer Inc.

BC48 AV45 BF52 BG51

DDR SYSTEM MEMORY B

[15] M_A_DQ[0..7] [15] M_A_DQ[32..39] [16] M_B_DQ[0..7] [16] M_B_DQ[32..39]

[15] M_A_DQ[8..15] [15] M_A_DQ[40..47] [16] M_B_DQ[8..15] [16] M_B_DQ[40..47]

[15] M_A_DQ[16..23] [15] M_A_DQ[48..55] [16] M_B_DQ[16..23] [16] M_B_DQ[48..55]

f ix Sandy Bridge Processor (POWER) Sandy Bridge Processor (GRAPHIC POWER)

SNB:33A AF46 C226 10U/6.3V_6 AA46 10mil

PEG AND DDR

J34 AJ15 Y48 *4700P/25V/X7R_4_NC

VIDSCLK VR_SVID_CLK [37] VCCSA[7] VCCSA_SENSE VCCSA_SENSE [36]

VCC_SENSE VCCSENSE [37]

+1.05V_VCCIO SVID DATA SVID ALERT +1.05V_VCCIO

Place resistor R175 close to CPU

BG17 VSS[181] VSS[251] M4

VSS[60] VSS[150] VSS[241] VSS_NCTF_5

f ix Cougar Point (DMI,FDI,PM)

+1.05V_PCH R203 49.9/F_4 DMI_COMP BD19 BK8

FDI_LSYNC1 BH8 FDI_LSYNC1 [3]

XDP_DBRST# R213 1K_4

System Power Management

SYS_PW ROK M10 T2 CLKRUN#

S3 Power reduce +5V_ALW

*10K_4_NC *0.01U/25V_4_NC 100K_4

f ix Cougar Point (LVDS,DDI) Cougar Point (GND)

Digital Display Interface

DDPD_AUXN VSS[212] VSS[317] VSS[54] VSS[133]

R129 Q27 G34 Y17

INT_DP_HPD VSS[257] VSS[374]

[29] PCH_AZ_CODEC_SDIN0 D36 HDA_SDIN0 SATA2RXN AD4

AF12 SATA3_COMP R209 49.9/F_4

PCH_SPI_CLK_RAD12 AH4 SATA3_RBIAS R208 750/F_4

Y2 +3VSATA1GP / GPIO19 R1 BBS_BIT0

PCH Strap Table

Del 0510 Remove SPI_MOSI from PCH strapping, HR_C/L_v0.91

PCI_PIRQC# USBP7P (weak pull-up 10K)

Add EMC solution

Termination Voltage PWROK weak pull-down 20kohm

R1961 2 2.2K_4 +1.8V_RUN

EC5 EC4 CheckList_1.5 p72; HR_v1.5 p476

Quanta Computer Inc.

[21] CLK_PCIE_W LANN AE49 CLKOUT_PCIE1N CLKOUT_DMI_N BB24 CLK_CPU_BCLKN [4]

AF40 CLKOUT_PEG_B_N XTAL25_IN W49 XTAL25_IN Y2

+3V CLKOUTFLEX1 / GPIO65 D48 CLK_FLEX1 T20 SML0DATA 3 4

10K_4_NC 0.01U/25V_4_NC 100K_4