Faculty of Electrical and Electronic Engineering

BEC 30303, Computer Architecture and Organization, Semester II Session 2014/2015

CHAPTER 2: INSTRUCTION SET ARCHITECTURE (ISA)

TUTORIAL

1. Using sign magnitude and 1’s complement methods, the value of zero (0) can be
represented by more than one value, which is not exists in 2’s compliment method.
Demonstrate this phenomenon by taking a 3-bit number as example.
2. Briefly explain about the overflow condition when performing arithmetic operations.
3. Sketch the basic structure of memory showing the 8 data bits, 3 bit address space. Calculate
the total memory capacity.
4. Describe the types of operation in memory structure. Describe also the effect of the
operations to the content of the memory.
5. Briefly explain about the function of ISA. Support your explanation with appropriate diagram.
6. List the elements that can be found in an instruction.
7. From the following statement, produce the equivalent Register Transfer Notation and
Assembly Language Notation.

Save the data in R1 to memory location Y

8. Sketch the block diagram for stack, accumulator, register-memory and register-register (load-
store) organizations. State the key difference between those CPU organizations?
9. Given a simple Z = B - C + D * E operation, evaluate the instructions to be executed on the
CPU for stack, accumulator, register-memory and register-register organizations.
10. Analyze the key difference between 3-address, 2-address, 1-address, and 0-address
instruction formats.
11. Compare between RISC instruction format and CISC instruction formats. Use example to
support your answer.
12. Explain the function status flags in a processor.
13. Define addressing modes. Do you think that a processor can have a mix of addressing
modes? Justify your answer.
14. Distinguish the addressing mode characteristics between RISC and CISC computers.

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