Code No.

15083/AICTE

FACULTY OF ENGINEERING
B.E. IV Semester (AICTE) (Main & Backlog) Examination, October 2021
Subject: Computer Organization
Max. Marks: 75
Time: 2 hours
Note: Missing data, if any, may be suitably assumed.

PART-A
(5x3 = 15 Marks)
Answer any five questions.

1. What is the use of CALL and RETURN instructions? n_

2. What is meant by program status word (psw). ,,,.. ~ 1- }
3. Draw block diagram of CPU. ( ~\i ,.,,,#
4. Differentiate Isolated and Memory mapped 1/0. . lr""' J'
5. How to write back method differ from write thrdligh i~ ~emory.
6. Differentiate SRAM and DRAM ,.;· ' ~
,,7. Explain flag register of 8086 ,
,,8. How is effective address calculated in " l ~ dt iadlressing Mode"?
9. An eight bit register contains the binary ue '010010. What is value in the
registrar after Arithmetic right Shift? ~ l overflow?
/ 10. Write an assembly language progra~ rform 8 bit subtraction.

tf)4_RT-B
Answer any four questions. \ , ~ (4x15 = 60 Marks)

11 (a) what do you unders6~~Je term" Addressing Modes"? Explain any six
addressing mod~wt,~ amples.
~b) Write an Assembfy1~guage program to evaluate (w+x+y)-(u/v) using
three,two,one,and zero address instructions.
,l•
12(a) Explain~ block diagram how CPU and IOP communicate with each other.
/ (b) Ex_pla~ 9 "ree different modes of data transfer.

13(a) O two-way set associative mapping in cache memory with an example.

(b) ~l the functioning of magnetic disk. .

14 Explain the architecture of 8086 microprocessor in detail with diagram.

15 Explain Data transfer and Arithmetic instructions of 8086 in detail with examples.

/16(a) Explain Asynchronous data transfer with neat block and timing diagrams.
·(b) Explain types of interrupts in detail. Draw interrupts cycle.

17 Write short notes on :

...-{a)Push and Pop Instructions (b) Auxiliary memory ~Pipelining
 Code No. 11459/CBCS

FACULTY OF ENGINEERING

B.E. IV-Semester (CBCS) (CSE) (Suppl.) Examination, Dec. 2018/ January 2019
Subject: Computer Organization

Time: 3 Hours Max. Marks: 70

Note: Answer all questions from Part-A and Any five questions from Part-B.

PART – A (20 Marks)

1 What is r’s complement? How do you implement complement system? 2
2 What is bus transfer? Explain different mechanisms to construct buses. 2

3 What is register transfer? Give an example. 2

4 What are different types of shift micro operations. 2
5 Draw the instruction word format and indicate number of bits in each part. 2
6 List different addressing modes. 2
7 Classify CPU organizations. 2
8 What is cache hit ratio? 2

9 What is CAM? 2
10 Differentiate between RISC and CISC. 2

PART – B (50 Marks)

11 a) Show the inter connection structure of different components of a computer.

Explain their functions. 4

b) Draw Instruction cycle flow chart. Explain its operations. 6

12 a) What is a micro operation? Discuss different kinds of operations implemented on

a shift register. 6
b) Illustrate Interrupt cycle with an example. 4

13 a) Write a program to evaluate the arithmetic statement

X = {A + B * C – (D * E – F)} / {G+H * K}
Using i) Three address ii) Two address iii) One address iv) Zero address
instructions 6
b) An instruction is stored at location 300 with its address field at location 309. The
address field has value 500. A processor register contains number 200. Evaluate
 the effective address if the addressing mode of the instruction is

a) direct b) immediate c) register indirect d) Index with processor register

as the index register 4

14 a) What is associative mapping? How is it implemented to improve performance? 4

b) What are the different types of data transfer? Explain. 6

15 a) Explain how the communication takes place between CPU and IOP. 6
b) Draw the block diagram of RAM chip and explain with the help of function table. 4

16 a) What are the six basic I/O operations? Explain. 6

b) Differentiate between Isolated and Memory mapped I/O. 4

17 Explain in detail different kinds of asynchronous data transfer methods with the
help of block and timing diagrams. 10
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 Code No. 11459 /
CBCS

FACULTY OF ENGINEERING

B.E. (CSE) IV – Semester (CBCS)(Main & Backlog) Examination, May / June 2019

Subject: Computer Organization

Time: 3 Hours Max.Marks: 70
Note: Answer all questions from Part – A and any five questions from Part – B.

PART – A (10x2 = 20 Marks)

1 How is effective address calculated in “Indirect Addressing mode”? 2

2 Draw a diagram to illustrate the interrupt cycle. 2
3 What is Gray Code? 2
4 What are Flyn’s classification? 2
5 The contents of register A are 1101 and that of register 'B' is '0110'. Find the result of
the following micro-program sequence 2

T1: BB̄
T2: AA+B
6 What is meant by Pipelining? 2
7 Define virtual memory. 2
8 What is meant by basic computer instruction format? 2

9 What is auxiliary memory? 2

10 What are the three methods of data transfer between I/O peripheral device and
memory? 2
PART – B (5x10 = 50 Marks)

11 a) Explain fixed point representation with examples? 5

b) Explain Instruction Cycle with flow chart and example? 5
 12 a) Design a bus system with multiplexers and other gates for communicating between
registers. 5

b) What do you understand by arithmetic shift? Explain 5

13 Explain Booth’s Algorithm with an example and draw flow chart. 10

14 a) Discuss in detail about Read and write operation with timing diagram. 5
b) Explain the concept of Array Processor. 5

15 a) Explain in detail about DMA data transfer. 5

b) Distinguish between isolated I/O and memory mapped I/O with an example. 5

16 a) What is cache memory, explain a mechanism of data transfer between cache and
main memory. 6

b) Briefly explain the functioning of magnetic disks. 4

17 Write a short note on:

i) Computer Registers 4
ii) Modes of transfers 3

iii) RAM and ROM 3

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