Assignment-12

The number of cycles a packet can be delayed in the network without reducing application’s
performance is known as _____.

Packet latency

Network stall time

Slack
Critical time
Ans) A slack of a packet is defined as the number of cycles it can be delayed in the network without
reducing the application’s performance.
Intel KNL has _____ tiles in 2D mesh.

8
36
64
16
Ans) Intel KNL has 36 Tiles interconnected by 2D Mesh

Which one of the following emerging NoCs uses the concept of diverting light to a certain
wavelength when voltage is applied?

3D NoC

Nanophotonics
RF waveguide wireless communication
Vertical interconnect
Ans) Nanophotonics is a promising technology for network building blocks, due to their inherently low
latency, high throughput, and low dynamic energy requirements. Nanophotonics uses a microring
resonator which diverts light of a certain wavelength when a voltage is applied

Which one of the following is a 64-bit dual core VEGA processor?

VEGA AS1061

VEGA AS2161
VEGA AS4161
 VEGA AS1161
Ans) VEGA AS2161: VEGA AS2161 64-bit dual core 16-stage pipeline out-of-order RISC-V processor.

Which one of the following statements is TRUE about layerwise DNN computation done on a
TCMP system?

Filter/weights are moved from global buffer to off-chip memory

Output feature map is progressed from off-chip memory to global buffer
Global buffer is directly connected to each PE using a dedicated bus

Filter/weights are moved from off-chip memory to global buffer

Consider a 16 x16 Cmesh NoC structure in which each node is connected to 4 processing cores.
The entire mesh structure is divided into 16 Wcubes. Each Wcube is marked with a 4 bit number.
[Wcube- 0 (0000) to Wcube- 15 (1111)] Identify the correct Wcube to which Wcube-15 can be
directly communicated?

Wcube- 9
Wcube- 13
Wcube- 10
Wcube- 8
Ans) Direct communication is possible only with a Wcube that is at hamming distance 1 (they differ only
at one bit position). Here 15 (1111) and 13 (1101) only differ in one bit position.
Consider a TCMP system with 64 tiles, where each tile consists of a superscalar processor, a
private L1 cache and a shared distributed L2 cache. The total L2 cache on the chip is 16MB and
L2 uses 64B blocks and is 8-way associative. Each L2 cache slice on-chip has all the 8 ways of
the sets assigned to it. The L2 cache memory per tile division is such that total sets in L2 cache
are uniformly partitioned across tiles in a sequential fashion. The system uses a 32-bit physical
address. How many L2 cache sets are mapped per tile?
Ans) 512
L2 size per tile= 16MB / 64 = (24 x 2
20
)/2
6=2
18 Bytes
No of sets in one L2 cache = (Size of cache) / ((size of block) * (associativity))
= 512

Consider a TCMP system with a 4x4 mesh NoC where each tile consists of a superscalar
processor, a private L1 cache and a shared distributed L2 cache. Let T0, T1, T2... ,T15
corresponds to the tiles where T0 is the bottom left tile and T15 the top right tile. Each tile has a
16KB 2-way associative L1 cache with a block size of 16B. The total L2 cache on the chip is
32MB and L2 uses 128B blocks and is 16-way associative. Each L2 cache bank has all the 16
ways of the sets assigned to it. The L2 cache memory per tile division is such that total sets in L2
cache are uniformly partitioned across all tiles in sequential fashion. The system uses a 40-bit
physical address. T4 generated an L1 cache miss for the address A1=0x A8CD210652. As per
L2 set mapping, tile Tx host the L2 set for A1. What is the value of x? (Hint: Possible value of x
ranges from 0 to 15).
Ans) 0
L2 size per tile= 32MB / 16 = 2MB = 2 21Bytes No of sets in one L2 cache= (221 ) / (27x 2 4 ) = 2 10 So,
the address distribution is: tag =19, tile=4, set index within tile 10; byte offset =7 0xA8CD210652 = 1010
1000 1100 1101 0010 0001 0000 0110 0101 0010 First 7 bits from left are offset bits, next 10 bits are set
bits and then next 4 bits are tile number bits. Rest of the bits are tag bits. Extract tile bits. So, tile bits
are: 0000 = 0 So the miss request travels from T4 to T0 through the NoC.

Name- Sahil Singh

UID- 23BCS80031