1)RISC feature of pentinum:-1)Because of the advance in
microelectronic manufacturing technology, a num of change
in the computer architecture are taking place from the last
decode2.)The new computer were design which use process
–or with complex instructions and addressing modes, which
we call a complex instruction set computer(CISC)
3)This problem is solved by a new design technique called as
Reduced Instruction set computer(RISC)
1)Simple Instruction Set In a RISC processor, the instruction
set consists of simple and basic The complex instructions
can be composed using simple and basic
instructions.2.Reduction of Instruction Set Less numbers of
instructions are used to simplify instruction
decoding.3)Elimination of Microcoding In RISC, microcode is
replaced by hardwired logic gates. Hence all execution units
are hardwired..4)Pipelining Usually, massive pipelining is
used in a RISC processor. Due to pipelined instruction
decoding and executing, more operations are performed in
parallel. Therefore, the speed of RISC processors is
increased.5)Very Few Addressing Modes RISC processors
have very few addressing modes and it supports few
formats.6)extensive utilization of the compiler:-1)when a
program is written in higher level language, during
compilation each statement within a program is converted
into assembly language instruction.
Fuatures of 8051 microcontroller:-1)8bit cpu2)on chip clock
oscillatay.3)4k bytes of on chip program memory.4)256bytes
of on chip data random access memory.4)64k byte of data
memory address space.5)64k bytes of data memory address
space6)32 bit directional I/O lines can be either used as four
8 bit data parts or 32 individual addressable I/O lines.
7)Two 16bit timers counters. 8)16bit address bus
multiplexed of with part 0 and and part 2 and 8 bit data bus
multiplexed with part 0. 9)five vectar interrupt structure
with two priority levels.
8086 ASSEMBLY PROGRAM TO MULTIPLY TWO 32 BIT
NUMBERS:--- data segment/abc dd 12345678H/def dd
12345678H/ghi dq ?/data ends/ code segment/
assume cs:code, ds:dat/start:/mov ax, data/mov
ds, ax/mov ax, word ptr abc/mul word ptr def/mov
word ptr ghi, ax/mov cx, dx/mov ax, word ptr
abc+2/mul word ptr def/add cx, ax/mov bx, dx/jnc
move/add bx,0001H/move: mov ax,word ptr abc/mul
word ptr def+2/add cx, ax/mov word ptr ghi+2,
cx/mov cx,dx/jnc ma/add bx, 0001H/ma: mov ax,
word ptr abc+2/mul word ptr def+2/add cx, ax/jnc
mb/add dx, 0001H/mb: add cx, bx/mov word
ptrghi+4, cx/jnc mc/add dx, 0001H/mc: mov word
ptr ghi+6, dx/int 3/code ends/end start
Features of 8096 Microcontroller:-1.The 8096 is a 16-bit
microcontroller.2.The 8096 is designed to use in applications
which require high speed calculations and fast I/O
operations.3).The high speed I/O section of an 8096 includes a
16 bit timer, a 16 bit counter, a 4 input programmable edge
detector; 4 software timers, and a 6-output programmable
event generator.4).The 8096 has 8 multiplexed input analog to
digital converter with 10 bit It can fully run under interrupt
control.5).Its programmable pulse width modulation output
signals can be used as control signals to drive a motor, and for
any other application.)6.Its serial port has several modes of
operation with programmable baud rates.
PSW:-program status work:-1)The psw or program status word
register is also called as flag register and is one of the impotant
sfrs.2)The esw register consist of flag bits which help the
programmer in checking the condition of the result and also
make decision.3)flags are 1-bit storage elements that store and
indicate the nature of the result that is generated by execution
of certain instruction.
Real mode:1)it uses 16bit of address2)it runs in 8086program TMOD:-Timer mode:-1)Tmod or timer mode register sfr is used
3)pentinum act as a faster 8086. 4)After reset of 80386,it to set the operating modes of the timer to and T1. The lower
starts program execution from the memory location address four bits are used to configure timer o and the higher four bits
offfffffH under the real mode.5)in this mode 80386 work as a are used to configure.
fast 8086 with 32-bit register and data type.
MEMORY addressing in real mode:-1)in the real mode, the Gate c T1 T1 Gate c T0 T0
80386 can address at the most 1 mb of physical memory 1 T1 M1 M0 0 T0 M1 M0
using address line A19-ao.2)in real mode program can access TCON:-Timer control.1)timer control or Tcon register is used to
up to six segment at any time two of these are for data and start or stop the timer of 8051 microcontroller.2)it also
code. 3)another segment is typically used for stack. contains bits to indicate if the times has overflowed.3)the tcon
PROTECTED MODE:-1)it supports sophisticated segmentation scr also consists of interrupt related bits.
2)segment unit translates 32-bit logical address to 32-bit
linear address.3)paging unit translate 32-bit linear address to Tf1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
32-bit physical address.4.paging unit translate 32-bit linear TCON Adress 88h
address to 32-bit phycial address. SCON:-1)The serial control or scon SFR is used to control the
8051microcontroller serial part it is located as a address of 98H
Watch dog timer:1)on chip 16-bit,watchdog timer is available 2)using scon you can control the operation modes of the serial
in 8096 which helps to recover the controller from the port and send bound roal of the serial port and send or receive
software upsets.2)This 16-bit WDT is a counter which is data using serial port.3)scon register also consists of bits that
incremented every state time. This counter is cleared by are automatically set when a byte of data is transmitted or
program after periodic interval and not allowed to overflow. received.
However, it the program does not progress properly by any
reason such as Electron static Discharge(ESD) or due due to SM0 SM1 SM2 REN TB8 RB8 T1 R1
any hardware related problems.the overflow occure.and the Address = 98aH
hardware reset is initiated to restart the microcontroller.
3)Watchdog timer is a piece of hardware in micro-
controller. Watchdog timer is used to generates system reset
if system gets stuck somewhere i.e. if system goes into
endless loop of execution watchdog timer will reset
the system to come out of endless loop. Watchdog is
safety mechanism in embedded system which makes
your system reliable, but it depends on how you make
use of watchdog timer.
INSTRUCTION PARING RULE IN RISC ARCHITECTURE:-1)single-
cycle execution:-In traditional central processing unit(cpu)
designs the peak possible execution rate is one instruction
per basic machine cycle and for a given technology the cycle
time has some fixed lower limit.Even on complex cpus, most
compiler generated instruction are simple generated instruct
ion are simple RISC design emphasize single-cycle execution.
(2)Hard-wired control, little or no microcode — Microcode
adds a layer of interpretive overhead, raising the number of
cycles per instruction, so even the simplest instructions can
require several cycles. 3). Simple instructions, few addressing
modes — Complex instructions and addressing modes, which
entail microcode or multicycle instructions, are avoided.
4) Load and store, register-register design — Only loads and
stores access memory; all others perform register-register
operations. This tends to follow from the previous three
principles.5)Efficient, deep pipelining — To make convenient
use of hardware parallelism without the complexities of
horizontal microcode, fast CPUs use pipelining. An n-stage
pipeline keeps up to “n” instructions active at once, ideally
finishing one (and starting another) every cycle. The
instruction set must be carefully tuned to support pipelining.
fuatures of 80286:-1)The 80286 is a 16-bit processor. The 16
bit ALU allows to process 16-bit data.2)it has 24 bit address
bus,so it can acess upto 16mbytes (𝟐𝟐𝟒 ) of physical memory
or 1 Gigabytes (𝟐𝟑𝟐 ) of virtual memory. 3)The 80286 can be
operated at three different clock speed. This are 4MHZ
(80286-4), 6mhz (80286-6) and 8 mhz(80286).4.The 80286
include special instruction to support operating system. 5)the
80286 was the first family member design specially for use as
cpu in a multi-user.(2)fuatue of 80386:-1)The 80386 is a 32-bit
processor. The 32 alu allows to process 32-bit data. 2)it has
32-bit address bus. So it can access upto 4 gbytes (𝟐𝟑𝟐 )
physical memory or 64 Tetra bytes (𝟐𝟒𝟔 ) of virtual memory
3)The 80386 runs with speed upto20mhz instruction per unit
second.4)it allows programmer to switch between different
operating system such as pc-dox and unix(3)fuature of 80486
:-1)it has highly integrated device containing about 1.2 million
transistors. 2)The 80486 operates on 25MHz , 33mhz, 50mhz,
66mhz or 100mhz. 3)It has built in math co-processor.4)80486
is a 32-bit architecture with on-chip memory management
and cache memory unit.5)The 80486 has 3modes of operation
Real mode, protected mode and virtual 8086 mode.

Interrupt structure:-1)There are 20 different interrupt
sources that can be used on the 8096.The 20 sources vector
though 8 locations or interrupt vectors.2)all these
interrupts are enable and disabled using the 9th bit of psw
register.3)in this bit is set to 1 all the interrupt are enables
and disabled when reset to zero.4)when the hardware
detects one of the 8 interrupts it sets the corresponding bit
in the interrupt pending register. 5)this register can be
read or modified as a byte register.6)the INT MASK register
can be accessed as the lower bits of psw register.
-----------------------------------------------------------------------
INTERUPT MECHANISM IN 8051:- Interrupts are the
events that temporarily suspend the main program, pass the
control to other functions or sources and execute their task. It
then passes the control to the main program where it had left
off. 2)As code size increases and your application handles
multiple modules, sequential coding would be too long and to
complex. The interrupt mechanism helps to embed your
software with hardware in a much simpler and efficient
manner. In this topic, we will discuss the interrupts in 8051
using AT89S52 microcont roller.3)When an interrupt is
received, the controller stops after executing the current
instruction. It transfers the content of the program counter
into the stack. Interrupts in 8051 includes :1)Reset.2)External
Interrupt 0.3)Timer/Counter 0.4)External Interrupt
5)Timer/Counter1,6)Serial Interrupt. Each
interrupt can be enabled or disabled by setting bits of the IE
register and the whole interrupt system can be disabled by
clearing the EA bit of the same register.- Reset interrupt
When the RESET interrupt is received, the controller restarts
executing code from 0000H location. This interrupt is not
available to the programmer.2)Timer interrupts:-Each
Timer is associated with a Timer interrupt. When a
timer has finished counting, the Timer interrupt
will notify the microcontroller by setting the
required flag bit.3)External interrupt:-8051 based
AT89S52 microcontroller has two active-low
external interrupts, INT0 and INT1. 4)Serial
interrupt:-This interrupt is used for serial
communication. When enabled, it notifies the
controller when a byte has been received or
transmitted according to how the interrupt is
configured.
-----------------------------------------------------------------------
Microprocessor microcontroller
Hert of computer system Hert of embedded system
Zero states flag No zero flag
Mainly use in perional Mainly used in washing
computer machine, AC etc.
It is complex and costly Simple and cheep
It can not be used in It can be used in compact
compact system.therefor system.therefore microco -
microprocessor is inefficient ntroller is more efficient
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1) System Address Registers(SAR):-These registers are used in
the protected mode of Intel processors. The Windows
operating system also operates in this mode.1.GDTR — This is
a 6-byte register containing the linear address of the global
descriptor table (GDT).2)TDTR — This is a 6-byte register
containing the 32-bit linear address of the interrupt
descriptor table.3)LDTR — This is a 10-byte register
containing the 16-bit selector (index) for GDT and an 8-byte
descriptor.4)TR — This is a 10-byte register containing the 16-
bit selector for GDT and the entire 8-byte descriptor from
GDT, describing the task state segment (TSS) of the current
task. TSS is a segment of special format that contains all
required information about the given task, and a special field
that ensures task interactions and intercommunications..
A base transceiver station (BTS) is a piece of network
equipment that facilitates wireless communication between a
device and network.-----------------------------------------------------
(2) A base transceiver station (BTS) :-is a piece of network
equipment that facilitates wireless communication between a
device and network.A BTS consists of the following:Antennas
that relay radio messages. 1)Transceivers.2)Duplexer
3)Amplifiers. A BTS is also known as a
base station (BS), radio base station (RBS) or node B (eNB) ---
----------------------------------------------------------------------------
AAM:-ASCII adjust after multiplication. This instruction
adjusts the result of the multiplication of two unpacked BCDs
to create a pair of unpacked (base 10) BCDs. For this
command, it is assumed that the AX register contains the
result of binary multiplication of two decimal system digits
(ranging from 0 to 81). After completion of this operation, the
AX register will contain a 2-byte product in ASCII format. It is
assumed that the least significant digit is contained in AL and
the most significant digit is contained in AH. The AAM
instruction is only useful when it follows an MUL instruction
that multiplies (binary multiplication) two unpacked BCDs
and stores a word result in the AX register. The AAM
instruction then adjusts the contents of the AX register so
that they contain the correct two-digit, unpacked (base 10)
BCD result.
Branch Prediction in Pentium:-The gain produced by
Pipelining can be reduced by the presence of program
transfer instructions eg JMP, CALL, RET etc.They change the
sequence causing all the instructions that entered the
pipeline after program transfer instructions invalidThus no
work is done as the pipeline stages are reloaded.
Branch prediction logic:- To avoid this problem, Pentium
uses a scheme called Dynamic Branch Prediction. In this
scheme, a prediction is made for the branch instruction
currently in the pipeline. The prediction will either be taken
or not taken. If the prediction is true then the pipeline will
not be flushed and no clock cycles will be lost. If the
prediction is false then the pipeline is flushed and starts over
with the current instruction.It is implemented using 4 way
set associated cache with 256 entries. This is called Branch
Target Buffer (BTB). -------------------------------------------------------
--------------------------------------------------------------------------
Floting point unit of pentinum processor:- A floating-
point unit (FPU, colloquially a math coprocessor) is a
part of a computer system specially designed to
carry out operations on floating-point numbers.
Typical operations are addition, subtraction, multiplication,
division, and square root.. A floating point unit is an
integrated circuit which handles all mathematical operations
that have anything to do with floating point numbers or
fractions. It is a dedicated logic unit specifically designed to
work on floating point numbers and nothing else, hence the
name. It can be defined as a specialized coprocessor that can
manipulate numbers quicker than the basic microprocessor
circuitry itself.The FPU performs simple mathematical tasks
which include addition, subtraction, division, multiplication
and square root. Older FPUs process transcendental
functions like exponential and trigonometric calculations but
these can be expensive and complicated to implement, so in
modern FPUs, these are done via software library routines.
Instruction &data cache of pentinum:- Despite the potential
advantages of a unified cache which is used in the 80486
processor, the Pentium microprocessor uses separate code and
data caches. The reason is that the superscalar design and
branch prediction demand more bandwidth than a unified
cache. First, efficient branch prediction requires that the
destination of a branch be accessed simultaneously with data
references of previous instructions executing in the
pipeline.Second,the parallel execution of data memory
references requires simultaneous accesses for loads and
stores.Third, in the context of the overall Pentium
microprocessor design, handling self-modifying code for
separate code and data caches is only marginally more complex
than for a unified cache.The data and instruction caches on the
Pentium processor are each 8 KB, two-way associative designs
with 32 byte lines. Each cache has a dedicated translation
lookaside Buffer (TLB) to translate linear addresses to physical
addresses.----------------------------------------------------------------
RISC CISC
It focuses on the software It focuses on the hardware.
Uses the hardware control It uses hardware as well as
unit microprogrammed control
unit
The instruction have a fixed The size of instruction vary
size.
Fewer register are used It requires more num of
register
Executes in one clock cycle Takes more than one clock
cycle for execution.
Explain program status word of IC 80386:-The program status
word is a register that performs the function of a status of a
status register 4 program counter, & sometimes more. The term
is also applied to a copy of the psw in storage. All through
certain fields within psw may be tested or set by using non-
privileged instruction testing or setting the remaining fields
may only. The program states word or psw is a collection of
data 8 byte (or 64bits) long, mainted by the os.
The data transfer instructions:- are used to transfer
data from one location to another. This transfer of
data can be either from register to register, register
to memory or memory to register.It is important to
note here that the memory to memory transfer of
data directly is not possible. Following are
some instructions that are used for data transfer
purpose:MOV,PUSH,POP,XCHG,LAHF,SAHF,IN,OUT.
1) MOV:This instruction simply copies the data from
the source to the destination.
Syntax: MOV destination , source
Example: MOV AX, BX
2) PUSHThis instruction is used to push data into
the stack.

Syntax: PUSH source

Example: PUSH CX
Working: SP <- SP - 1
[SP] <- CH
SP <- SP - 1
[SP] <- CL

3) POPThis instruction is used to get the data from

the stack.

Syntax: POP destination

Example: POP CX
Working: CL<- [SP]
SP <- SP + 1
CL <- [SP]
SP <- SP+ 1

4) XCHGIt exchanges the contents of the source and

the destination.

Syntax: XCHG destination, source

Example: XCHG BL, AL