MC 88110 RISC Processor

The MC88110 is a RISC type 1.3 million transistors, 0.8 micron CMOS 299 pin
microprocessor. It is a two issue superscalar system having 10 on-chip operational units called
execution units. The block diagram of MC 88110 is shown in the following fig. The architecture
shows mainly two SFUs named as SFU1 used to execute floating point operations and SFU2 to deal
the graphics instructions. SFU3 to SFU7 are reserved for future use.
The execution units are
o Two integer units
o Branch
o Bit –field
o Multiply [both for integer and floating point](pipelined)
o Floating add (pipelined)
o Divide (Integer and Floating Point)
o Two graphics units
o Load and store

The large numbers of execution units permit simultaneous execution of a large number of
fetched instructions simultaneously. Two identical execution units take care of integer arithmetic /
graphics instructions and execute them simultaneously. This feature is called superscalar. The main
part of superscalar unit is the Central Instruction Sequencer (CIS).. The CIS fetched the instructions
from the Icache, identify the resource availability, and directs operand flow between the register file
and the execution units and dispatches the instructions to the necessary execution units.
There is a fully associative 32 entry logically addressed Target Instruction Cache (TIC) is
available. Each entry in the TIC contains the first two instructions of a branch target instructions.
When a branch instruction occurs, the TIC is accessed in parallel with the decoding of the branch
instruction. If there is a TIC hit, the two instructions corresponding to the branch instructions are sent
from the TIC to the instruction unit. This eliminates much of delay
On each clock cycle, the CIS fetches two instructions from the instruction cache and two from
the TIC. It decodes the appropriate instruction pair while fetching data operands from the register file.
MC 88110 has load / store execution unit. The unit provides a stunt box capability or holding memory
references that are waiting for the memory system and allows dynamic reordering of load operations
past stalled store operations.
Stunt box is a device that allows reordering of memory acc references. The data path between
load / store unit and register file is 80 bits wide. On each cycle, the load /store unit can accept one new
load / store instruction from Icache and waits for the access to the Dcache. Store instructions can be
dispatched before the store data operand is available. Store instructions wait in the store queue until
the instruction that computing the required data completes execution. When the operands become
available, the sequencer directs it into the store reservation station, and the associated store instruction
access the data cache.

Fig – Block diagram of MC 88110

The block diagram of MC 88110 is shown in the above fig.MC 88110 provides a reservation
station to avoid stalling or conditional branches. The sequencer predicts the branch direction, and
executes instructions down the predicted path conditionally until the branch operand is resolved. The
branch reservation station provides a place to set aside the branch instruction so that instruction issue
can continue while the branch condition can be resolved. If the prediction was incorrect, the system
backs up to the branch, undo all operations and resumes execution along the correct path.
The MC 88110 has a dual cache of 8KB instruction, 8 KB data for a total of 16KBs. Each
cache is physically addressed two-way set associative, with 32 bytes/line. The data cache in MC
88110 is write back system. The MC 88110 can also be connected to a secondary external cache which
is controlled by a separate IC MC 8840 called cache controller. The size of the secondary cache is of
256 Kb to 1MB. The secondary cache is also write back with 32 / 64 byte per line.
The MC 88110 features two types of ATC.
1) Page ATC (PATC): Fully associative that contains 32 entries containing page number translation
for 4KB pages and is either maintained by hardware or software.
2) Block ATC (BATC): Fully associative eight entries containing address translation of block sizes
ranging from 512 KBs to 64 MBs. The term block stands for a large number of pages in a memory
system.
MC 88110 processor includes the dual MMU called as Instrcution MMU (IMMU) and data
MMU (DMMU). The IMMU and the Icache comprise the instrcution memory unit (IMU) where as
the DMMU and Dcache manages the data memory unit (DMU). Therefore simultaneosu access of
instrction and dat supports more efficient handling of pipeline in superscalar systems.
The paging mechanism and the page table structure is similar to Intel system and the only
difference is the page directory in Intel systems are called Segment tables in MC 88110. The PTE of
Intel processor is called as Page descriptor and PDE is called as Segment descriptor. There are four
pointer entries in MC 88110 to locate the directory.