EE419 Assignment 2022.

Student name: Harry Beggy

E-mail: harry.beggy2@mail.dcu.ie

ID: 18378271

Programme: ME4

Contents
Section 1 – Introduction........................................................................................................................1
Section 2 - Task 1: The Half Wave Rectifier............................................................................................2
Section 2.1 – Designing the full wave rectifier...................................................................................2
Section 2.2 – Building the full wave rectifier circuit...........................................................................4
Section 2.3 – Testing the full wave rectifier.......................................................................................5
Section 2.4 – Implementing the cheapest solution............................................................................6
Section 3 - Task 2: The open-loop DC-DC buck converter......................................................................8
Section 3.1 – Specification of the inductor and capacitor..................................................................8
Section 3.2 – Building the open-loop DC-DC buck converter.............................................................9
Section 3.3 – Testing the open-loop DC-DC buck converter............................................................10
Section 3.4 Implementing the cheapest solution............................................................................13
Section 4 – Connecting the output from task 1 to the input of task 2.................................................15
Section 4.1 - The construction of the circuit....................................................................................15
Section 4.2 – Testing the circuit.......................................................................................................16
Section 5 – Implementing a PI compensator.......................................................................................20
Section 5.1 – Building the circuit.....................................................................................................21
Section 5.2 – Testing the circuit.......................................................................................................23
Section 6 – Results...............................................................................................................................25
Section 7 – Conclusion.........................................................................................................................26
REFRENCESS........................................................................................................................................26

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Section 1 – Introduction.
The goal of the assignment was to design a closed-loop system to meet design specifications given
by a client. The client was a company which wanted circuitry to supply a load of 2.5 ( Ω) with a DC
voltage of 3 (V). The power for the circuity was supplied by a source voltage of 8 sin(2 π ( 500 ) t ).
The specifications for the outputs were a voltage ripple of no more than 5% of the average value and
an inductor current ripple of no more than 10% of the average value. It had to be demonstrated to
the clients that these specifications were met.

The closed-loop system was iteratively designed. The designing process was broken down into four
tasks. As the input to the circuitry was an AC signal, it had to be converted to a DC signal using a full
wave rectifier. Designing the full wave rectifier was the first task. The voltage still needed to be
stepped down to 3 (V). A DC-DC buck converted was used to achieve this. The first two tasks were
done separately. Once they each had the desired outputs, the full wave rectifier output was
connected to the DC-DC buck converted input.

It was found the outputs from task three did not meet those specified by the company. The final task
involved designing a controller to obtain a consistent output that meets the circuitry design
specifications. The sections of this report will detail how each task was completed starting from the
full wave rectifier to the controller.

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Section 2 - Task 1: The Half Wave Rectifier.
The circuitry designed in this task converts the AC input voltage to a DC output voltage (with ripple
superimposed). The design specifications for task one was an output voltage with a peak-to-peak
voltage ripple of no more than 4 (V), implementing the cheapest possible solution. The design had to
be simulated using pSpice schematics and the voltage ripple was measured to demonstrate to the
company that the circuit had met the design specifications.

The following sections will describe how the capacitor value was chosen based off the design
specification.

Section 2.1 – Designing the full wave rectifier.

A full wave rectifier circuit with an RC load was used to convert the signal from AC to DC. By placing a
large capacitor in parallel to a resistive load, a nearly constant output voltage can be produced. This
occurs because, as the fully rectified input voltage sinewave is increasing, the capacitor is charging.
When the sinewave begins to decrease, the diodes go reverse bias, allowing the capacitor to
discharge in the ‘positive’ direction. If the capacitor discharges at a slower rate to the slope of the
sinewave, it will hold the output voltage at a higher voltage to the sinewave as it is decreasing.
Therefore, if the capacitor is very large, it will hold a lot of charge, taking longer to discharge. If the
capacitor is infinitely large, the output would appear as a perfect DC signal. The point at which the
diodes go reverse bias is known as the turn-off angle, θ .

When the sinewave starts to increase faster than the capacitor is decreasing, the diodes go forward
bias and the output voltage is the value of the sinewave. The point at which the diodes go forward
bias is ' π +α ' .

The circuit will have four ideal diodes, one capacitor and a resistor. The diodes transfer current from
one pair to the other when the source voltage changes polarity, giving a fully rectified output signal.
The value of the resistor was 2.5 (Ω). The capacitor was the only component which needed to be
determined based off the specified voltage ripple ¿ ¿).

The following equations were used to determine an appropriate value for the capacitor:

Vmπ
Δ V o= (1)
ωRC
Equation one can be re-arranged to solve for the capacitor value:

Vm π
c= (2)
ωR Δ V o

Filling in the parameter values into equation two:

8π
c= (3)
2 π ( 500 ) ×2.5 × 4

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The result from equation three:

C=0.0008(F ) (4)

As seen in equation four, the capacitance value to give an output voltage ripple of no more
than 4 (V), was 800 ( μF ¿. With this capacitance value, the voltage ripple can also be
predicted using the following equation:
−θ−α −π
sin ( θ ) e ωRC
−sin ( α )=0 (5)

α is found numerically using ‘MATLAB’. All the variables in equation five are filled in and a
π
plot is made going from π to 2 π , in steps of . The α value can then be used to determine
100
the minimum output voltage. This can be subtracted from the maximum voltage, which is 8
(V), because the maximum voltage across a reversed biased diode is the peak value of the
source. The following equations will outline how the minimum voltage was determined:

θ=π −tan−1 (wRC ) (6)

θ=1.7286 ( rad ) (7)

−1.7286−α −π
sin ( 1.7286 ) e 2 π (500 )× 2.5 ×0.0008 −sin ( α )=0 (8)

α =0.816 8 (rad) (9)

The minimum voltage level can now be predicted using the following equation:
Vmin=V m sin( α) (10)
V m is the amplitude of the source voltage. Filling in values for equation 10:

Vmin=8 sin ⁡(0.8168) (11)

Vmin=5.83(V ) (12)

Using the result from equation 12, the voltage ripple can be estimated:
Δ V =Vmax−Vmin (13)
Δ V =8−5.83 (14)
Δ V =2.17(V ) (15)

Equation 15 indicates that the circuit should meet the design requirement for the full wave
rectifier.

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Now that all the components for the full wave rectifier have been calculated, the circuit had
to be built in pSpice.

Section 2.2 – Building the full wave rectifier circuit.

The diodes used in the circuit were ideal. The diodes used were called ‘Dbreak’ and were made ideal
by editing the diode model, and inserting a parameter ‘n’, setting ‘n’ to 0.01. This gives the effect of
having effectively no voltage drop across the components. The source voltage was a sinewave (V1).
The sinewave wave had a frequency of 500 (Hz), and an amplitude of 8 (V).

Figure 1. The full wave rectifier circuit with calculated capacitance (C1).

As seen in fig. one, the capacitor value calculated in equation four, can be seen in parallel to ‘R1’.
The positive terminal of ‘V1’ is connected directly to the positive pin of ‘D1 Dbreak’ and the negative
pin of ‘D3 Dbreak’. The negative terminal of ‘V1’ is connected directly to the positive pin of ‘D2
Dbreak’ and the negative pin of ‘D4 Dbreak’.

It should be observed that the output frequency of the voltage ripple is twice the input voltage
frequency. The output voltage ripple will be measured across ‘R1’ as it is the load. To demonstrate
the output voltage ripple, the circuit in fig. one was simulated using pSpice, and the output voltage
ripple will be measured using MATLAB.

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Section 2.3 – Testing the full wave rectifier

Figure 2. Plot showing the output voltage ripple and the input voltage of the full wave rectifier.

As seen in fig. two, the frequency of the output voltage ripple (Vout), is twice the frequency of the
input voltage (Vsin). The output voltage ripple repeats every π , where the input voltage repeats
every 2 π . Using MATLAB, the output voltage ripple was calculated by filling in the values from
equation 13. The results were as follows:

Δ V o=7.9795−5.6108 (16)
Δ V o=2.3687(V ) (17)

The graph was simulated with a delay in pSpice of 0.002 (s). This meant the minimum value of the
voltage could be taken as the ripples lowest value, instead of the output signals origin at zero.

The output voltage ripple was within the design specification. There was a difference of 0.1987 (V)
between the predicted and measured voltage ripple. The maximum value allowed is a 4 (V) ripple.
Therefore, this is not the cheapest solution. The cheapest solution will be a circuit that has the
smallest possible capacitor value. This will need to be calculated in order fully meet the design
specifications for the full wave rectifier.

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Section 2.4 – Implementing the cheapest solution.
To find out which capacitor value will give an output voltage ripple as close to 4 (V) as possible,
equation five and equation size can be used, by decreasing the size of the capacitor. This would
mean that the turn off angle should increase, allowing the sinewave voltage to be the output voltage
for longer. α will also decrease, meaning the diodes will go forward bias faster, lowering the impact
the capacitor has on the output voltage. The results were as follows:

θ=π −tan−1 (2 π ( 500 ) ×2.5 ×345 μ) (18)

θ=1.9243(rad ) (19)

α =0.5655 (20)

Using equation 11 and equation 13, the new voltage ripple should have been:

Δ V o=3.7134 (V ) (21)

Figure 3. Full wave rectifier circuit with theoretical smallest capacitor.

As seen in fig. three, the capacitor value has been updated to the value that should give the voltage
ripple described in equation 21.

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 Figure 4. Final output voltage ripple for the full wave rectifier.

It can be seen in fig. four, that the output voltage ripple has become much larger. Using MATLAB and
equation 13, the output voltage ripple wax:

Δ V o=3.9670(V ) (22)

The solution from equation 22 shows that the circuit performed better than predicted with a
difference of 0.2536 (V) between them. Equation 22 demonstrates that the design specifications for
the full wave rectifier have been fully met.

The output of the full wave rectifier will need to be stepped down to meet the 3 (V) output
specification from the company. A DC-DC buck converter must be designed to achieve this.

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Section 3 - Task 2: The open-loop DC-DC buck converter.
The circuitry must step-down the input voltage from the full wave rectifier to 3 (V), which is why a
buck converter is being used. The circuit must be designed for the worst-case scenario. The output
voltage ripple must be no more than 5% of the average value. The output inductor current ripple
must be no more than 10% of the average value. Using these design specifications, the inductor and
capacitance values can be determined.

The following section will describe how the component values were deducted from the design
specifications.

Section 3.1 – Specification of the inductor and capacitor.

There are a few assumptions that are made for DC-DC analysis. All components in the circuit are
ideal, meaning the input power is equal to the output power because there is no voltage drop across
ideal components.

Table 1. Specifying inductor and capacitor values.

Vo 3 3
D= = =0.75 D= =0.38
V ¿ 4.01 7.98

Vo
2
3.6
I lm= =1.19 ( A )
R 3.6 3.03
I lm= = =1.20( A)
V S D 3.0075
V O (1−D ) 3 ( 1−0.75 ) 3 ( 1−0.38 )
Ltl = = =2.5(mH ) Ltl = =6.25(mH )
Δ il f ( 1.20 × 0.1 ) × 2500 ( 1.19× 0.1 ) × 2500
L=Ltl × 1.25=6.25 × 1.25=7.813(mH )
R ( 1−D ) 2.5 ( 1−0.38 )
Lmin> → →0.31( mH )
2f 2× 2500
( 1−D ) 1−0.75 1−0.38
C tl = = C
=12.28(= μF ) =31.74 ( μF )

[ ]
tl
ΔV o 2 2
8 × 0.05× 2500 × 7.813m 8 × 0.05× 25002 × 7.813× 10−3
8 f L
Vo
C=C tl ×1.25=31.74 ×1.25=39.69( μF)

As seen in table one, the duty cycle, D, is calculated for both the minimum and maximum input
voltage from the output voltage ripple of the full wave rectifier. By doing this, the worst-case
scenario can be found, and the components can be designed to successfully perform under this
scenario. The inductor current, I lm, was found by equating the input power to the output power and
solving for I lm. The inductor current was found because the current ripple must be no more than
10% of it. A theoretical value for the inductor, Ltl, can be calculated using D and I lm. The bigger Ltl is
chosen to account for the worst-case scenario. This value must be increased by at least 25% when
simulating the circuit in pSpice for the output to work as predicted. To ensure that the inductor
value, L, will allow for continuous inductor current, it must be greater than the minimum inductor
value, Lmin. A theoretical value for the capacitor, C tl, can be calculated. As the output voltage of the
buck converted is DC, the average output voltage, V o , is 3 (V). The largest C tl is chosen and
increased by 25% for the same reasons as the inductor.

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These calculated component values will have to be tested to see if they meet the design
specifications. An open-loop DC-DC buck converter must be simulated in pSpice to determine if the
design specifications have been met.

Section 3.2 – Building the open-loop DC-DC buck converter

The circuit works in two steps. The first step is when the switch is closed allowing current to flow
into the circuit. The diode goes reverse bias, creating a short circuit and allowing current to the
capacitor, charging it up. The capacitor can not charge instantaneously. The inductor also limits the
charging current. These two factors mean that during the switching cycle, the capacitor never
reaches the full voltage of the power source.

Step two is when the switch is open. The inductor is unable to instantaneously discharge its current,
so it creates a voltage across it, while the capacitor discharges. The inductor powers the load
through the diode when the switch is off, maintaining a current output through the switching cycle
[1].

Figure 5. Open-loop DC-DC buck converter.

Fig. five shows the open-loop DC-DC buck converter, constructed on pSpice. The calculated values
for the inductor and capacitor from table one can be seen beside ‘L1’ and ‘C1’ respectively. The
switch is controlled by ‘V2’. ‘V2’ creates a PWM waveform which opens and closes the switch, ‘S1’.
The duty cycle of the PWM, ‘D’, is calculated by dividing the output voltage by the input voltage. The
circuit is tested for an appropriate range of input voltages. The duty cycle will be changed based on
the input voltage, but the component values will remain constant.

To test the circuit, a parametric sweep was performed plotting multiple outputs based off an
increasing input voltage. The ripples were calculated using MATLAB.

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Section 3.3 – Testing the open-loop DC-DC buck converter.
One of the assumptions made when analysing DC-DC converters is that the circuit is in steady state.
To achieve this, only the last five switching cycles were measured. This was achieved in the transient
settings on pSpice. The simulation was run for 250 switching cycles (0.1 seconds) and the
measurements were delayed for the first 245 switching cycles (0.98 seconds) to ensure that the
circuit had reached steady state.
3.00V

2.95V

2.90V

2.85V
98.0ms 98.2ms 98.4ms 98.6ms 98.8ms 99.0ms 99.2ms 99.4ms 99.6ms 99.8ms 100.0ms
V(R1:1)
Time

Figure 6. Output voltage ripples for appropriate range of input voltages. Green = 4 (V). Red = 5 (V).
Blue = 6(V). Yellow = 7 (V). Pink = 8 (V).

In fig. six, there is a continuous output as described in ‘Section 3.2 - Building the open-loop DC-DC
buck converter’ of this report. From visual inspection, the voltage ripple increases as the input
voltage decreases. The circuit has reached a steady state output as well. It can also be observed that
all of the output voltages are nearly at 3 (V). All positive indicators that the circuit has met the design
specifications.

Table 2. MATLAB calculations for the output voltage and voltage ripple.

Input Voltage (V) Output Voltage (V) Voltage Ripple (%)

4 2.96 1.45
5 2.96 2.35
6 2.93 2.94
7 2.92 3.36
8 2.91 3.67

Table two shows the range of input voltages that were tested. MATLAB calculated the ‘Output
Voltage’ by finding the ‘mean’ of the output values. The ‘Voltage Ripple’ was calculated the same
way as for the have wave rectifier in ‘Section 2.3 – Testing the full wave rectifier’ of this report. The
‘Output Voltage’ decreases as the ‘Input Voltage’ increases. This is due to the duty cycle, which is
calculated in table one. The lower the input voltage, the higher the duty and therefor the higher the
output voltage [1]. The ‘Voltage Ripple’ increases as the ‘Input Voltage’ increases. This is because the
capacitor will be charged with more voltage, the higher the ‘Input Voltage’ is. Which means that
during the switching cycle, more power is given to the load as the ‘Input Voltage’ increases.

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Neither the ‘Output Voltage’ nor ‘Input Voltage’ exceeded their design specifications. The inductor
current ripple will need to be measured to ensure all design specifications have been met.

1.25A

1.20A

1.15A

1.10A
98.0ms 98.2ms 98.4ms 98.6ms 98.8ms 99.0ms 99.2ms 99.4ms 99.6ms 99.8ms 100.0ms
I(L1)
Time

Figure 7. Inductor current ripple for an appropriate range of input voltages. Green = 4 (V). Red = 5
(V). Blue = 6 (V). Yellow = 7 (V). Pink = 8 (V).

From visual inspection of fig. seven, the biggest inductor current ripple is the pink wave. The ripple
increases as the input voltage increases. This is due to the inductor being charged with more current
relative to the input voltage, giving it more current to discharge. The current linearly rises and falls.

Table 3. Inductor current ripple for an appropriate range of input voltages.

Input Voltage (V) Inductor current ripple (%)

4 3.35
5 5.38
6 6.72
7 7.68
8 8.93

The results in table three confirm that the inductor current ripple satisfies the design specifications
as there are no values greater than 10%.

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Figure 8. Plot showing the inductor current ripple (IL), output voltage ripple (Vout) and the switching
cycle (PWM).

It can be seen in fig. eight, that IL linearly rises as the switch is open. While the inductor current
rises, the capacitor is charging , (Vout). When the switch closes at 0.0983 (s), which is DT, IL starts to
drop as the inductor is discharging through the diode. The voltage across the inductor and the
capacitor discharging supplies power to the load while the source is disconnected from the load. At
0.094 (s), which is T, the switch opens again, supplying power to the load from the source.

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Section 3.4 Implementing the cheapest solution.
The cheapest solution requires the cheapest components that will meet the design specifications.
The cheapest components will have the smallest value. The capacitor will have the biggest impact on
the output voltage because it has the same voltage across it as the load. The inductor current ripple
is a result of the duty which is why the component being altered is just the capacitor.

Figure 9. The open-loop DC-DC buck converter circuit with the cheapest solution implemented.

In fig. nine, the lowest value of the capacitor that was within the design specifications was 25.4 ( μF ¿
. This value was found through trial and error.

Table 4. The measured voltage outputs with the cheapest capacitor.

Input Voltage (V) Output Voltage (V) Voltage Ripple (%)

4 2.96 1.94
5 2.95 3.15
6 2.93 3.97
7 2.92 4.52
8 2.91 4.93

The results in table four show that the cheapest solution has stayed within the design specifications
of a 5% voltage ripple and a 3 (V) output. The ripple was bigger than in table two. The change in
charge is greater, meaning there is greater difference between the maximum and minimum output
voltage ripple.

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 Figure 10. Illustration and equation describing the size of the charge and its relation to the output
voltage ripple.

As seen in fig. 10, the output voltage ripple becomes larger as the capacitor value decreases. It can
also be seen that the change in charge (Q) is increases when the capacitor is increased.

Table 5. The measured inductor current ripple values for the cheapest capacitor values.

4 3.36%
(V)
5 5.38%
(V)
6 6.72%
(V)
7 7.68%
(V)
8 8.4%
(V)

The values in table five are very similar to the values in table three. This was predicted and still lies
within the design specifications.

Now that both stages of the circuit have been constructed, they need to be connected.

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Section 4 – Connecting the output from task 1 to the input of task 2.
The full wave rectifier and open-loop DC-DC buck converter had to be connected to convert the
input sinewave signal to a 3 (V) DC output signal.

Section 4.1 - The construction of the circuit.

The load was removed from the full wave rectifier circuit and the input voltage was removed from
the buck converter. The output of the rectifier was connected to the input of the converter.

Figure 11. The open-loop control of a buck converter with a rectifier input.

Fig. 11 illustrates how the two circuits are connected. This circuit will be tested to see if the design
specifications set by the company are still adhered too.

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Section 4.2 – Testing the circuit
The circuit will be tested by varying two components and seeing if the circuit can maintain a
constant output with disturbances to the system. The first disturbance added to the system was a
change of duty cycle.

3.5V

3.0V

2.5V

2.0V

1.5V
98.0ms 98.2ms 98.4ms 98.6ms 98.8ms 99.0ms 99.2ms 99.4ms 99.6ms 99.8ms 100.0ms
V(R1:1)
Time

Figure 12. The output voltage ripple from the system.

From visual inspection of fig. 12, there is not a constant output voltage. Some voltages are below 3
(V) and one is roughly 3.4 (V), which exceeds the specification of a 3 (V) output.

The duty cycle was varied using the input voltage, as seen in the ‘PARAMETERS’ block in fig. 11.

Table 6. Output voltage and voltage ripple with varying duty cycle.

Input Voltage (V) Output Voltage (V) Voltage Ripple (%)

4 3.4 4.17
5 2.78 5.27
6 2.3 6.33
7 1.93 7.2
8 1.63 7.84

Nearly all the duty cycles exceeded the output voltage ripple specification of 5%. There is also huge
variation in ‘Output Voltage’ with some falling significantly below the 3 (V) and one being over 3 (V).

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 1.4A

1.2A

1.0A

0.8A

0.6A
98.0ms 98.2ms 98.4ms 98.6ms 98.8ms 99.0ms 99.2ms 99.4ms 99.6ms 99.8ms 100.0ms
I(L1)
Time

Figure 13. The inductor current ripple for a changing duty cycle.

In fig. 11, there is large separation in inductor current values, but the inductor current ripple is more
important. On visual inspection, it is difficult to determine if the inductor current ripples stay within
the specified 10% range.

Table 7. Inductor current ripple for a varying duty cycle.

Input Voltage (V) Inductor Current Ripple (%)

4 6.1
5 8.13
6 10.11
7 11.63
8 13.02

The results in table seven show that the specification for inductor current ripple was exceeded for
most duty cycles.

The next disturbance into the system will be a change in the load. The resistor value will be changed
keeping the duty cycle constant.

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 3.0V

2.5V

2.0V

1.5V
98.0ms 98.2ms 98.4ms 98.6ms 98.8ms 99.0ms 99.2ms 99.4ms 99.6ms 99.8ms 100.0ms
V(R1:1)
Time

Figure 14. Output voltage ripple for a change in load.

Fig. 14 shows there is variations in the output voltage and output voltage ripple. From visual
inspection, the 3 (V) output specification has been adhered too. It is difficult to determine if the
voltage ripple has stayed within 5%.

Table 8. Output voltage and voltage ripple for a varying load.

Load ( Output Voltage (V) Voltage ripple (%)

Ω¿
0.5 1.53 2.96
1.5 2.1 5.1
2.5 2.29 6.33
3.5 2.4 6.93
4.5 2.47 7.21
5.5 2.51 7.43

The results in table eight show that the ‘Output Voltage’ has fallen below the 3 (V) specification, and
the output voltage ripple has exceeded the 5% limit for almost all load values.

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 4.0A

3.0A

2.0A

1.0A

0A
98.0ms 98.2ms 98.4ms 98.6ms 98.8ms 99.0ms 99.2ms 99.4ms 99.6ms 99.8ms 100.0ms
I(L1)
Time

Figure 15. Inductor current ripple for a varying load.

Again, it is evident in fig. 15 that there is a large variation in the inductor current, but it is difficult to
determine if the inductor current ripples have exceeded 10%.

Table 9. Inductor current ripple for a varying load.

Load ( Inductor current ripple (%)

Ω¿
0.5 3.15
1.5 6.1
2.5 10.11
3.5 13.56
4.5 16.94
5.5 20.24

When reading the results from table nine, as the load increases, the inductor current ripple increases
and most of the values exceed the specified 10%.

These test show that the system is unable to meet the specifications when there is a disturbance in
the system. The disturbance of a changing duty cycle had a lesser affect on the output voltage than
the varying load as the output voltages are closer to the 3 (V) specifications than the varying load.
However, both disturbances affected the voltage ripples approximately the same.

Varying the load had a greater affect on the inductor current ripple than varying the duty cycle. The
maximum ripple form varying the load was 20.24% compared to 13.02% for a varying duty cycle.

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Section 5 – Implementing a PI compensator.
Implementing a compensator will enable the system to handle disturbances. This should have the
affect of minimizing the difference between the system’s actual value and the desired value [2]. A PI
(Proportional Integral) compensator combines proportional and integral control action. Proportional
controls have an output signal that has proportionality to the error signal. It is given as:

V con =K p v e (23)

For equation 23, K p has a value of one, which represents the gain. The variable v e is the difference
between a reference voltage and the output voltage.

An integral controller has an output which is the integral of the error signal. It is given as:

V con =K i∫ v e (24)

For equation 24, K i is 300, which is the gain. Integral controllers are unstable. They are slow to
respond to the error, but they are able to respond to continuous deviation. The proportional
controller reduces the steady state error making the system becomes more stable but has does not
offer fine controlling [2]. If both controllers are combined, it gives a highly stable result. The control
signal is given as:

V con =K p v e + K i∫ v e (25)

The control signal from equation 25 will be compared to a ramp signal. If the control signal is greater
than the ramp signal, the switch will be closed. If the opposite is true, the switch will be open.

To see if the PI compensator will counteract disturbances to the system, it must be constructed on
pSpice.

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Section 5.1 – Building the circuit.
The PI compensator is comprised of a reference voltage, integrator, a ramp signal, and a conditional
block. The output of the compensator will be fed into the switch, replacing ‘V2’ from fig. 11. The
output of the buck converter is subtracted from the reference voltage.

Figure 16. The PI compensator added to the circuit.

In fig. 16, it can be seen that v e is created when the output of the circuit is subtracted from ‘Vref’,
which is the desired output. The error signal is then integrated with a gain of 300 for the integral
control. The proportional control is the error signal. The proportional and integral control are
summed together to give the control signal, V con. The ramp signal, ‘Vramp’, was created by making a
pulse signal with a rise time equal to the period of the switching cycle, 0.4 (ms). Setting the pulse
width to 1 (ns) and the fall time to 1 (ns). The period of the signal was the rise time minus the pulse
width and the fall time.

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 Figure 17. PI controller determining if the switch is open or closed.

At the start of the plot in fig. 17, ‘Vcon’ has a greater value than ‘Vramp’. This means that the error
signal is a negative, meaning that the output of the circuit is not the desired output. To bring the
error towards zero and the output closer to the desired output, the switch is closed. This allows the
current to flow from the source, bringing the voltage error closer to zero. This can be seen in fig. 17
as ‘PWM’ is high. When ‘Vcon’ is less than ‘Vramp’, the error is positive. The switch is closed to stop
current flowing and to let the error signal return down to zero. This cycle repeats itself every 0.4
(ms).

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Section 5.2 – Testing the circuit.
To test how the system reacts to disturbances, the load value was changed using a parametric
sweep.

4.0V

3.0V

2.0V

1.0V

0V
0s 40ms 80ms 120ms 160ms 200ms 240ms 280ms 320ms
V(R2:1)
Time

Figure 18. Output voltage of the circuit using a PI compensator. Green = 0.5 (Ω). Red = 1.5 ( Ω). Blue
= 2.5 (Ω). Yellow = 3.5 (Ω). Pink = 4.5(Ω). Turquoise = 5.5(Ω).

Fig. 18 depicts a very constant output voltage except for 0.5 (Ω). From visual inspection, the system
appears to be reaching 3 (V) faster as the load resistance increases. It is difficult to determine the
output voltage ripple, but the largest ripple occurs for a load of 5.5 (Ω).

Table 10. Output voltage and voltage ripple for the PI compensation system.

Load ( Output Voltage (V) Voltage Ripple (%)

Ω¿
0.5 2.3 2.13
1.5 3.02 5.73
2.5 3.03 9.57
3.5 2.95 11.37
4.5 2.93 10.82
5.5 3.02 11.42

The values in table 10 for ‘Output Voltage’, excluding a load of 0.5 ( Ω ¿, show that the output
voltage design specification of 3 (V) have been achieved. The output voltage ripple surpasses the
design specification for a resistive load above approximately 2.5 (Ω ¿. When compared to table
eight, the output voltage ripple is larger then without the PI controller, but the output voltage is
much closer to the design specification.

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 6.0A

4.0A

2.0A

0A
0s 40ms 80ms 120ms 160ms 200ms 240ms 280ms 320ms
I(L1)
Time

Figure 18. The inductor current ripple for the PI compensated system. Green = 0.5 (Ω). Red = 1.5
(Ω). Blue = 2.5 ( Ω). Yellow = 3.5 (Ω). Pink = 4.5(Ω). Turquoise = 5.5(Ω).
It can be observed in fig. 18 that inductor current value decreases as the load increases. A 0.5 (Ω)
load appears to go straight to steady state, but the other loads have overshoot before settling. It is
difficult to determine the inductor current ripple from visual inspection.

Table 11. The inductor current ripple for a PI compensated system.

Load Inductor current ripple (%)

(Ω)
0.5 2.17
1.5 6.45
2.5 11.84
3.5 14.92
4.5 16.91
5.5 18.9

The results in table 11 indicate that the inductor current ripple design specification has been
exceeded for a resistive load above approximately 2.25 (Ω ¿. When compared to table nine, the
results are generally larger for inductor current ripple, except for a load of 5.5 ( Ω).

If the circuit is simulated without any disturbance to the system, it meets all designed requirements.

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 Figure 19. The output voltage and inductor current for the PI compensated system with no
disturbances.

From fig. 19, the output voltage, Vo, is centred on 3 (V). The inductor current ripple, L, appears to be
within the specifications.

Table 12. Outputs from the undisturbed system with PI compensation.

Output voltage Voltage ripple (%) Inductor current ripple (%)

(V)
3 4.63 7.19

The results from table 12 show that all the design specifications were met when no disturbances
were introduced to the system.

Section 6 – Results
The final circuit fails to meet the companies’ specifications. It does not meet two out of the three
design specifications with a disturbance to the system. However, all design specifications were met
when there was no disturbance to the system. The PI compensator was set up to alter the output
voltage if it moves away from the desired 3 (V). For both the disturbed and undisturbed circuits, it
performs this successfully. The controller was not designed to account for any changes in voltage
ripple or inductor current ripple. This meant that a load of above 2.5 ( Ω) saw the design
specifications being exceeded for both voltage and inductor current ripple.

The company can use the circuit if they only need an output voltage of 3 (V), regardless of ripple. If
the circuit will not experience any disturbances, specifically in the load, then the company can use it
for all the designed specifications.

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Section 7 – Conclusion
The assignment benefited my understanding of power electronics. I knew the basics of how a full
wave rectifier worked but I did not fully understand the turn off angle or the turn on angle. Analysing
the circuit from task one taught me how the capacitor creates the wave form and how the
magnitude of the wave is determined. I was not as familiar with the buck converter as the full wave
rectifier. I knew that it stepped down voltages, but I struggled to understand why it stepped down
the voltage, until I analysed task two. I had no previous experience with a PI compensator before
trying to design task four. It was a steep learning curve to understand how to build it, and then
figure out how it works.

There are still gaps in my knowledge with the assignment. For example, I do not understand why a
value of 0.5 Ω produces such a low output voltage compared to the other resistive loads. I also
struggle to define exactly what the worst-case scenario is. I know how to design for it, but I can’t
strictly define it.

There were some links to other modules in this assignment, both past and present. The idea of a
voltage ripple was mentioned in a second year module called Systems. A rectifier had been
mentioned in a previous module in third year called Electromechanical Systems. I had used pSpice
also in a previous module called Analog and Digital Devices. A current module called Control Systems
has the heaviest link. PID controllers were most recently covered. In Control Systems, block diagrams
are used to implement control to a system but in this assignment, the control had to be
implemented practically with electronic components, which was more of a challenge.

I did enjoy this assignment because I was designing a charger, even if it could not be practically
implemented, the basics were covered on how to create a transformer. I struggled with
understanding how the buck converter steps down a voltage and also how the PI compensator fully
works in terms of exactly why everything in it was used.

If I was to do the assignment again, I would probably preform all calculations for each task before
hand and then see what the measured outputs were. I think this would aid in understanding what
was happening and why faster.

REFRENCESS
[1] Buck Converter: Basics, Working, Design and Operation, Components 101, April 26, 2019.
[Online]. Available: https://components101.com/articles/buck-converter-basics-working-design-and-
operation.

[Accessed: November 25, 2021].

[2] Controllers, Proportional, Integral & Derivative Controllers, Electricalvoice, January 8, 2020.
[Online]. Available: https://electricalvoice.com/controllers-proportional-integral-derivative-
controllers/.

[Accessed: November 25, 2021].

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