2.

(ECEN 4797 and ECEN 5797)

Two-Transistor Forward Converter: Modeling, Design and Simulations
The objectives in this problem are to model and design a two-transistor forward converter shown in Figure 1,
and then verify the design using Spice simulations. The converter operation is described in Textbook Section
6.3.2, see Fig. 6.27.

Figure 1 Forward converter.

(a) (30%) Assume transistors Q1 and Q2 are the same and have on-resistance Ron ; diodes D3 and D4 are
the same and have a constant forward voltage drop VD (diode resistance RD can be neglected). All
other losses can be neglected. You may assume that the converter operates in CCM and that inductor
current and capacitor voltage ripples are small. You may also assume that transformer magnetizing
inductance L M is very large, and that the converter operates at duty cycle D ≤ 0.5, so that the mag-
netizing inductance is properly reset in each switching period. Derive a complete equivalent circuit
model for the two-transistor forward converter including conduction losses due to Ron and VD . Solve
the equivalent circuit model to derive analytical expressions for the conversion ratio M = Vout /Vbatt
and for the converter efficiency η. This is the end of Part (a) of the problem.

The rest of the problem refers to the following application example: in an electric vehicle a high volt-
age battery pack powers the vehicle drivetrain. In addition, the high-voltage battery provides power to
various loads on a low-voltage dc bus, which include user interface and entertainment systems, vehicle
control systems, etc. You are tasked with the high-voltage to low-voltage dc-dc converter design.
The two-transistor forward converter has been selected to accomplish the task. The converter should
provide a regulated low-voltage bus VOUT = 14 V at a maximum output current Iout = 20 A from
a high-voltage battery Vbatt . Depending on the battery state of charge, dc battery voltage Vbatt can
be between Vbatt,min = 200 V and Vbatt,max = 340 V. You may assume a control circuit (not shown in
Fig. 1) automatically adjusts the duty cycle D such that the output voltage equals the regulated value
(14 V) regardless of the battery voltage.

1
(b) (20%) The transformer turns ratio is n = 1/N, where N is a positive integer number. Based on the
model derived in Part (a), choose N to minimize conduction losses in the converter. To receive full
credit, you must clearly explain your reasoning.

(c) (10%) You may neglect all losses in this part. Switching frequency is f s = 100 kHz. Assuming N
found in Part (b), find L so that for all possible battery voltages the worst-case maximum inductor
current ripple ∆iL equals 2 A, i.e., 10% of the dc output current Iout = 20. Keep in mind that D is
always such that Vout = 14 V.

(d) (30%) A partially completed LTspice circuit together with necessary library files has been provided.
In this part of the problem, your task is to complete the LTspice circuit and perform simulations to
verify your design:

• Insert values for L and N based on your work in Parts (b) and (c).
• Choose MOSFETs M1 and M2 from the list of available components in LTspice. Make sure
the voltage rating of the MOSFETs is sufficiently high. Justify your choice. The solution is not
unique.
• For any particular value of Vbatt, value of Vm (which sets D) must be determined so that steady-
state dc output voltage meets V(out) = 14 V ± 1%. For a given Vbatt, a good approach is start
from a model-based value for Vm, and make small trial-and-error adjustments as needed to meet
the voltage regulation requirement.

By running appropriate simulations, verify your design. You may need to go back to Parts (b) and/or
(c) if you find that you design does not meet the specifications. Once you have verified your design,
determine the values below for the following two battery voltages: 200 V and 340 V. Make sure that
simulation results are collected in steady-state operation of the converter, after initial transients have
subsided.

• Voltage Vm
• Average output voltage
• Amplitude of the magnetizing current
• Voltage stress on M2 (’voltage stress’ means the maximum voltage a device is exposed to in its
off state)
• Voltage stress on D4
• Inductor current ripple
• Average value of the input current
• Converter efficiency

To receive full credit, you must include a snapshot of your complete LTspice circuit diagram, clearly
explain how you performed simulations, and how you determined the requested results. You must
present your simulation results in a neatly organized table. You must also upload your Spice simula-
tion file for the case when Vbatt is 200 V, but do not assume the grader will open the file or run any
simulations - all work must be included in the file you submit for grading.

(e) (10%) Compare the efficiency results found in Part (d) to the efficiency results based on the model
derived in Part (a). What is the main loss mechanism not included in the model of Part (a) that is
responsible for the lower efficiency obtained by simulations?