INTERFACING PMOD SSD TO THE ZYBO AND .

XDC FILE CONSTRAINTS

The Seven-Segment display is connected across the JC and JD header of the Zybo board as illustrated in
the Fig.1. On the SSD, there are 7 segments AA, AB, AC, AD, AE, AF and AG along with one additional CAT
bit to select between the left and the right digit in the SSD. The SSD is connected to the top layer pins of
both the JC and JD headers. This corresponds to the 4 signals bits of JC and JD each as shown in the Fig. 2
for the PMOD ports (reference: Zybo-Z7 reference manual on Digilent).

Figure-1

Figure-2

To drive the SSD, 8-bit values are to be provided on these PMOD pins! If you open the zybo.xdc file as
shown in Fig.3, there exists 8 mappings interface in total for JC and JD header. That is
pmod_ssd_tri_io[7:0]. Carefully examine how these 8-bits interface to the pins of PMOD on your Zybo
board. The mapping pmod_ssd_tri_io[0] is assigned to the V15 pin which is pin number 1 of the JC header
(keep the Zybo-Z7 reference manual open so that you can relate the pin mapping – Topic number 16:
PMOD Ports).

In the same line, you will find that pmod_ssd_tri_io[7] is located at the pin 4 – R14 of the JD header. On
your SSD, this is the CAT pin to select between the left and the right digit of SSD.
INTERFACING PMOD SSD TO THE ZYBO AND .XDC FILE CONSTRAINTS

Figure-3

Once you are in Xilinx SDK, we have an SSD_Decode function that is responsible for driving these 8-bits
for the display. [7:0] => [CAT,AG,AF,AE,AD,AC,AB,AA]

Using the highlighted part of Fig. 4, to display 1 on any of the digit, [AG:AA] = 0000110 = bits [6:0].

The CAT bit will be 0 or 1 based on the digit you choose. So again, [7:0] = x000 0110 where x=CAT bit.

Figure-4 (Reference: PMOD SSD reference manual)