Point of ● Run CPU ● DI120~150

TCD - 124 PDL Error Application

Detection ○ Speed CPU ● DI180~420

[Meaning] Detecting any errors of PDL unit that uses floor information [Actions to take]
1.Check DOR-230 PCB.
calculated by car slide at power failure as synchronous floor 1)Verify if BAT,CCN1,CCN2,and PWS CONNECT are normally
compensation at power recovery connected to BATTERY and PDL MIC respectively.
2)Verify if a terminal resistance is set up in DIP SW
(ID SW-8).
3)Check PWDT LED status.
- Flickering at 500ms interval: Normal communication.
- Flickering at 2s interval : Normal MICOM,
[Explanation]
Abnormal communication
Variables in which PDL failure causes as below Verify if No.7 S/W of DOC-200 PCB SW5 is Off.
*Address of PDL_Sts_Err is 0x15F6 And then check the below Item. 2.
2. Read $15F6 in NVRAM area by means of DOA-100 PCB and
*PDL_Sts_Err BIT verify if the Bits shown right are set. Then take
When floor height count value is beyond the specification. b0 actions indicated as below.
When increase of floor height count is over ‘1’. b1
BIT Setting Actions to Take
When POSI input is abnormal. b2
When there is a discrepancy between car running direction b0,b1,
b3 Check each connector for connection status.
and count value increase or decrease. b3,b4b5
b2 Verify CCN1 and CCN2 connector for connection.
When there is a discrepancy between floor height value
b4
that is counted by Run CPU and that by PDL unit. Read the spec.($001E) of EEPROM and check
b6
the status of set or reset.
Though synchronous location is compensated into bottom/
b5
top floor, the floor location count of PDL unit is not same. 1)Check P.SOURCE for LON side 22V FUSE(F1,F2).
b7
2)Dismantle battery and check voltage(Over 10V normal)
When PDL unit does not exist or was not enabled by spec.
b6
or communication is not normal.
When PDL back-up memory is damaged. b7 3. After checking above item 1 and 2 take actions by,
moving the car to the bottom or top floor and
clearing the address 0x15F6, 0x2515 in NVRAM area
through DOA-100 PCB.