Digital Electronics and Logic Design MCQs [set-24]

576. Q2 :=Q1 OR X OR Q3 The above ABEL expression will be

A. q2:= q1 $ x $ q3

B. q2:= q1 # x # q3

C. q2:= q1 & x & q3

D. q2:= q1 ! x ! q3
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Answer: B
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577. Above is the circuit diagram of
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A. asynchronous up-counter c
B. asynchronou s down- counter
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C. synchronous up-counter

D. synchrono us down- counter

Answer: A

578. The high density FLASH memory cell is implemented using

A. 1 floating-gate mos transistor

B. 2 floating- gate mos transistors

C. 4 floating- gate mos transistors

D. 6 floating- gate mos transistors

Answer: A

579. A bidirectional 4-bit shift register is storing the nibble 1110. Its input
is LOW. The nibble 0111 is waiting to be entered on the serial data-input
line. After two clock pulses, the shift register is storing .

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 A. 1110

B. 111

C. 1000

D. 1001

Answer: D

580. At T0 the value stored in a 4-bit left shift was “1”. What will be the
value of register after three clock pulses?

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B. 4
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C. 6

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D. 8
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Answer: D
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581. A multiplexer with a register circuit converts

A. serial data to parallel

B. parallel data to serial

C. serial data to serial

D. parallel data to parallel

Answer: B

582. In outputs depend only on the combination of current state and inputs

A. mealy machine

B. moore machine

C. state reduction table

D. state assignmen t table

Answer: A

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583. The input overrides the input

A. asynchronous, synchronous

B. synchronous, asynchronou s

C. preset input (pre), clear input (clr)

D. clear input (clr), preset input (pre)

Answer: A

584. For a gated D-Latch if EN=1 and D=1 then Q(t+1) = o m

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A. 0
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B. 1

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C. q(t)
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D. invalid
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Answer: B

585. If S=1 and R=1, then Q(t+1) = for negative edge triggered flip- flop

A. 0

B. 1

C. invalid

D. input is invalid

Answer: C

586. The sequence of states that are implemented by a n-bit Johnson

counter is

A. n+2

B. 2n

C. 2 raise to power n

D. n raise to power 2

Answer: B

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587. The alternate solution for a multiplexer and a register circuit is

A. parallel in / serial out shift register

B. serial in / parallel out shift register

C. parallel in / parallel out shift register

D. serial in / serial out shift register

Answer: A

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588. THE GLITCHES DUE TO RACE CONDITION
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USING A
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A. gated flip- flops

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B. pulse triggered flip-flops

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C. positive- edge triggered flip-flops

D. negative -edge triggere d flip- flops

Answer: D

589. Flip flops are also called

A. bi-stable dualvibrators

B. bi-stable transformer

C. bi-stable multivibrator s

D. bi-stable singlevibra tors

Answer: C

590. A transparent mode means

A. the changes in the data at the inputs of the latch are seen at the output

B. the changes in the data at the inputs of the latch are not seen at the output

C. propagation delay is zero (output is immediately changed when clock signal is applied)

D. input hold time is zero (no need to maintain input after clock transition)

Answer: A

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591. Given the state diagram of an up/down counter, we can find

A. the next state of a given present state

B. the previous state of a given present state

C. both the next and previous states of a given state

D. the state diagram shows only the inputs/out puts of a given states

Answer: A

592. In Q output of the last flip-flop of the shifto

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data input of the first flip-flop of the shift register.

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A. moore machine

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B. meally machine
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C. johnson counter

D. ring counter
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Answer: D

593. status.

A. 3

B. 7

C. 8

D. 15

Answer: C

594. We have a digital circuit. Different parts of circuit operate at different

clock frequencies (4MHZ, 2MHZ and 1MHZ), but we have a single clock
source having a fix clock frequency (4MHZ), we can get help by

A. using s-r flop- flop

B. d-flipflop

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 C. j-k flip-flop

D. t-flip-flop

Answer: C

595. If S=1 and R=1, then Q(t+1) = for negative edge triggered flip- flop

A. 0

B. 1

C. invalid
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Answer: C
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596. WHEN BOTH THE INPUTS OF EDGE-TRIGGERED J-K FLOP-FLOP
ARE SET TO LOGIC ZERO c
A. the flop- flop is triggered
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B. q=0 and q?=1

C. q=1 and q’=0

D. the output of flip- flop remains unchang ed

Answer: C

597. If an S-R latch has a 1 on the S input and a 0 on the R input and then
the S input goes to 0, the latch will be

A. set

B. reset

C. invalid

D. clear

Answer: A

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598. For a positive edge-triggered J-K flip-flop with both J and K HIGH, the
outputs will if the clock goes HIGH.

A. ?toggle

B. set

C. ?reset

D. ?not change

Answer: A

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599. What is the difference between a D latch and a D flip-flop?
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A. the d latch has a clock input. a
B. the d flip- flop has an enable input.
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C. ?the d latch is used for faster operation.

D. the d flip- flop has a clock input.

Answer: D

600. A frequency counter

A. counts pulse width

B. counts no. of clock pulses in 1 second

C. counts high and low range of given clock pulse

D. none of given options

Answer: B

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