SRM INSTITUTE OF SCIENCE AND TECHNOLOGY

FACULTY OF ENGINEERING AND TECHNOLOGY

RAMAPURAM CAMPUS,CHENNAI-600 089
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

18CSS201J-ANALOG AND DIGITAL ELECTRONICS

UNIT-4 SEQUENTIAL LOGIC CIRCUITS

1. The basic latch consists of ___________

a) Two inverters
b) Two comparators
c) Two amplifiers
d) Two adders
Answer: a

2. In SR Latch if Q = 0, the output is said to be ___________

a) Set
b) Reset
c) Previous state
d) Current state
Answer: a

3. The output of latches will remain in set/reset until ___________

a) The trigger pulse is given to change the state
b) Any pulse given to go into previous state
c) They don’t get any pulse more
d) The pulse is edge-triggered
Answer: a

4. What is a trigger pulse?

a) A pulse that starts a cycle of operation
b) A pulse that reverses the cycle of operation
c) A pulse that prevents a cycle of operation
d) A pulse that enhances a cycle of operation
Answer: a

5. The difference between a flip-flop & latch is ____________

a) Both are same
b) Flip-flop consist of an extra output
c) Latches has one input but flip-flop has two
d) Latch has two inputs but flip-flop has one
Answer: c

6. How is a J-K flip-flop made to toggle?

a) J = 0, K = 0
b) J = 1, K = 0
c) J = 0, K = 1
d) J = 1, K = 1
Answer: d

7. In D flip-flop, D stands for _____________

a) Distant
b) Data
c) Desired
d) Delay
Answer: b

8. The term synchronous means ____________

a) The output changes state only when any of the input is triggered
b) The output changes state only when the clock input is triggered
c) The output changes state only when the input is reversed
d) The output changes state only when the input follows it
Answer: b

9. Master slave flip flop is also referred to as?

a) Level triggered flip flop
b) Pulse triggered flip flop
c) Edge triggered flip flop
d) Edge-Level triggered flip flop
Answer: b

10.In a positive edge triggered JK flip flop, a low J and low K produces?
a) High state
b) Low state
c) Toggle state
d) No Change State
Answer: d
 11.If one wants to design a binary counter, the preferred type of flip-flop is
____________
a) D type
b) S-R type
c) Latch
d) J-K type
Answer: d

12.S-R type flip-flop can be converted into D type flip-flop if S is connected to R

through ____________
a) OR Gate
b) AND Gate
c) Inverter
d) Full Adder
Answer: c

13.D flip-flop is a circuit having ____________

a) 2 NAND gates
b) 3 NAND gates
c) 4 NAND gates
d) 5 NAND gates
Answer: c

14.How are the sequential circuits specified in terms of time sequence?

a. By Inputs
b. By Outputs
c. By Internal states
d. All of the above
Answer: d

15.The behavior of synchronous sequential circuit can be predicted by defining

the signals at ______.
a. discrete instants of time
b. continuous instants of time
c. sampling instants of time
d. at any instant of time
Answer: a
 16.The characteristic equation of D-flipflop implies that _____.
a. the next state is dependent on previous state
b. the next state is dependent on present state
c. the next state is independent of previous state
d. the next state is independent of present state
Answer: d

17.Which circuit is generated from D-flipflop due to addition of an inverter by

causing reduction in the number of inputs?

a. Gated JK- latch

b. Gated SR- latch
c. Gated T- latch
d. Gated D- latch
Answer : d

18.What is the bit storage binary information capacity of any flipflop?

a. 1 bit
b. 2 bits
c. 16 bits
d. infinite bits
Answer: a

19.Which memory elements are utilized in an asynchronous & clocked sequential

circuits respectively?

a. Time- delay devices & registers

b. Time- delay devices & flip-flops
c. Time- delay devices & counters
d. Time-delay devices & latches
Answer: b

20.What is state diagram?

a) It provides the graphical representation of states
 b) It provides exactly the same information as the state table
c) It is same as the truth table
d) It is similar to the characteristic equation
Answer: b

4-mark questions:

21.A master slave flip-flop has the characteristic that

a) Change in the input immediately reflected in the output
b) Change in the output occurs when the state of the master is affected
c) Change in the output occurs when the state of the slave is affected
d) Both the master and slave states are affected at the same time
Answer: d

22.In the latch circuit shown, the NAND gates have non-zero, but unequal
propagation delays. The present input condition is: P = Q = "0‟. If the input
condition is changed simultaneously to P = Q = "1", the outputs X and Y are

a) X = 1,Y=1
b) Either X=1,Y=0 or X=0,Y=1
c) Either X=1,Y=1 or X=0,Y=0
d) X = 0,Y=0
Answer: b

23.The state transition diagram for the logic circuit shown is

Answer: d

24.In the sequential circuit shown below,if the initial value of the output Q1Q0 is
00,what are the next four values of Q1Q0?

a) 11,10,01,00
b) 10,11,01,00
c) 10,00,01,11
d) 11,10,00,01
Answer: a

25.You are given a free running clock with a duty cycle of 50% and a digital
waveform f which changes only at the negative edge of the clock. Which one
of the following circuits (using clocked D flip-flops) will delay the phase of f
by 180°?
Answer: c

26.The below sequential circuit is built using JK flip-flops is initialized with

Q2Q1Q0 = 000. The state sequence for this circuit for the next 3 clock cycle
is

a) 001,010,011
b) 111,110,101
c) 100,110,111
d) 100,011,001
Answer: c
 27. The current state QA QB of a two JK flip-flop system is 00. Assume that the
clock rise-time is much smaller than the delay of the JK flip-flop. The next

state of the system is

a) 00
b) 01
c) 10
d) 11
Answer: d

28. In the following sequential circuit, the initial state (before the first clock pulse
) of the circuit is Q1Q0= 00. The state (Q1Q0), immediately after
the 333rd clock pulse is

a) 00
b) 01
c) 10
d) 11
Answer: b

29. The present output Qn of an edge triggered JK flip-flop is logic 0. If J=1, then
Qn+1
a) Cannot be determind
b) Will be logic 1
c) Will be logic 0
 d) Will race around
Answer: b

30.Consider the circuit in the diagram. The ⊕ operator represents Ex-OR. The D
flipflops are initialized to zeroes (cleared).

The following data: 100110000 is supplied to the “data” terminal in nine

clock cycles. After that the values of q2q1q0 are:
a) 000
b) 001
c) 010
d) 101
Answer: c

12 mark questions

31.Consider the sequential circuit shown in the figure, where both flip-flops used
are positive edge-triggered D flip-flops. The number of states in the state
transition diagram of this circuit that have a transition back to the same state
on some value of "in" is ______

a) 2
b) 3
c) 4
d) 5
Answer: a
 32.Consider the following circuit

The flip-flops are positive edge triggered D FFs. Each state is designated as a two
bit string Q0Q1. Let the initial state be 00. The state transition sequence is:

a)

b)

c)

d)
Answer: d
33.The sequential circuit diagram for the given state diagram is

a.

b.  

c.
 d.

Answer: a

34.Consider a sequential circuit shown in Figure It has one input x, one output Z
and two state variables Q1Q2 (thus having four possible present states 00, 01,
10, 11).Construct the state diagram.

a.
 b. .

c.

d.

Answer: b
35.Design a sequential circuit whose state tables are specified in Table , using D
flip-flops.

a.

b.
c.

d.
Answer: a

36.Design an asynchronous sequential circuit that has two inputs X2 and X1 and
one output Z. when X1 = 0, the output Z is 0. The first change in X2 that
occurs while X1 is 1 will cause output Z to be 1. The output Z will remain 1
until X1 returns to 0.

a.

b.
 c.

d.

Answer: a