Digital Electronics and Logic Design MCQs [set-21]

501. Which of the following flip-flop is free from race-around problem ?

A. q flip-flop

B. t flip-flop

C. sr flip-flop

D. master- slave jk flip-flop

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Answer: D
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behave as a q M
502. If the input J is connected through K input of J-K, then flip-flop will

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A. d type flip-flop M
B. t type flip- flop

C. s-r flip-flop

D. master slave jk flip-flop

Answer: A

503. If a clock with time period 'T' is used with n stage shift register, then
output of final stage will be delayed by

A. nt sec

B. (n-1)t sec

C. n/t sec

D. (2n+1)t sec

Answer: B

504. Register is a

A. set of capacitor used to register input instructions in a digital computer

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 B. set to paper tapes and cards put in a file

C. temporary storage unit within the cpu having dedicated or general purpose use

D. part of the main memory

Answer: C

505. The number of flip-flops required in a decade counter is

A. 3

B. 4
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C. 8
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D. 10
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Answer: B
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506. If in a shift resistor Q0 is fed back to input the resulting counter is

A. twisted ring with n : 1 scale

B. ring counter with n : 1 scale

C. twisted ring with 2n : 1 scale

D. ring counter with 2 n : 1 scale

Answer: C

507. A 8-bit serial in / parallel out shift register contains the value “8”,
clock signal(s) will be required to shift the value completely out of
the register.

A. 1

B. 2

C. 4

D. 8

Answer: D

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508. In a sequential circuit the next state is determined by and

A. state variable, current state

B. current state, flip- flop output

C. current state and external input

D. input and clock signal applied

Answer: D

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509. The divide-by-60 counter in digital clock is implemented by using two
cascading counters: .c
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A. mod-6, mod-10 a
B. mod-50, mod-10
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C. mod-10, mod-50

D. mod-50, mod-6
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Answer: A

510. In NOR gate based S-R latch if both S and R inputs are set to logic 0,
the previous output state is maintained.

A. true

B. false

Answer: A

511. The minimum time for which the input signal has to be maintained at
the input of flip-flop is called of the flip-flop.

A. set-up time

B. hold time

C. pulse interval time

D. pulse stability time (pst)

Answer: B

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512. 74HC163 has two enable input pins which are and

A. enp, ent

B. eni, enc

C. enp, enc

D. ent, eni

Answer: A

513. to change in one input variable o m

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A. clock skew
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B. condition

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C. hold delay
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D. wait
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Answer: B

514. The input overrides the input

A. asynchronous , synchronous

B. synchronous, asynchronou s

C. preset input (pre), clear input (clr)

D. clear input (clr), preset input (pre)

Answer: A

515. A decade counter is .

A. mod-3 counter

B. mod-5 counter

C. mod-8 counter

D. mod-10 counter

Answer: D

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516. In asynchronous transmission when the transmission line is idle,

A. it is set to logic low

B. it is set to logic high

C. remains in previous state

D. state of transmissi on line is not used to start transmissi on

Answer: B

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517. A Nibble consists of bits .c
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A. 2 a
B. 4
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C. 8

D. 16
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Answer: B

518. The output of this circuit is always .

A. 1

B. 0

C. a

D. abar

Answer: C

519. Excess-8 code assigns to “-8”

A. 1110

B. 1100

C. 1000

D. 0

Answer: D

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520. The voltage gain of the Inverting Amplifier is given by the relation

A. vout / vin = - rf / ri

B. vout / rf = - vin / ri

C. rf / vin = - ri / vout

D. rf / vin = ri / vout

Answer: A

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521. LUT is acronym for
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A. look up table

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B. local user terminal
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C. least upper time period

D. none of given options

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Answer: A

522. The three fundamental gates are

A. and, nand, xor

B. or, and, nand

C. not, nor, xor

D. not, or, and

Answer: D

523. Stack is an acronym for

A. fifo memory

B. lifo memory

C. flash memory

D. bust flash memory

Answer: B

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524. is one of the examples of synchronous inputs.

A. j-k input

B. en input

C. preset input (pre)

D. clear input (clr)

Answer: A

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o arrives at different times
525.
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occurs when the same clock signal
. delay
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at different clock inputs due to propagation

at
A. race condition

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B. clock skew
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C. ripple effect

D. none of given options

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Answer: B

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