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M. Sc. 1st Semester (CBCS Scheme w.e.f. 2018-19)

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Examination, March-2022

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PHYSICS
Paper-18 PHY 21C4
Physics of Electronic Devices
Time allowed : 3 hours] [Maximum marks : 80

Note : Attempt five questions in all, selecting at least one

question from each unit. Question No. 1 is
compulsory.

1. (a) What do you mean by intrinsic Fermi level

(Efi) ? Under what condition the interinsic Fermi
level (Efi) lies at the mid gap energy. 4

(b) Show that under equilibrium in a semiconductor

D k T
 B , where the symbols have their usual
μ q
meanings. 4

(c) Briefly explain varactor diode and how it is

used to generate signals whose frequency varies
with voltage applied to it. 4

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(b) Thermal Oxidation

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(d) Explain the use of MOS structure to fabricate

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an IC capacitor. A SiO2 layer of thickness (c) Epitaxial growth

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0.5 μm is used to fabricate a MOS based (d) Packaging and testing
IC capacitor, find its capacitance per unit
area, you are given with ε SiO2 = 3.9 and
ε 0 =8.85 × 10–14 F/cm2. 4

Unit-I

2. In a semiconductor under equilibrium show

that : 12+4=16
(a) Electron concentration (n 0 ) and hole
concentrations (p0) are given as :

 – ( EC  E f )
n0=NC exp  k BT
 & P = N exp
0 V
 

 – (E f – E V ) 
 
 k B T 

(b) Intrinsic carrier concentration (ni) is given as

 – Eg 
ni = N C N V exp  2k T 
 B 

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(b) Consider a semiconductor film of thickness dl Unit-III

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is grown on a substrate of thickness ds. A beam
6. (a) Draw the schematic of p-n junction solar cell
of monochromatic light with intensity I0 falls on
and explain its I-V characteristics. Find the
the sample surface vertically. A detector kept
expression for open circuit voltage (VOC), short
at the backside measures a transmitted intensity
circuit current (ISC), fill factor (F.F.) and
of 1/3 Io. If al and as are the absorption
efficiency (). What are the possible reasons
coefficients for the semiconductor layer and
for its low efficiency ? 12
the substrate, respectively then prove that
al dl + s ds = ln3. 4 (b) A Si solar cell 2 cm  2 cm with IS=1nA has
an optical generation rate of 1018 EHP/cm3-s
5. (a) Describe how the minority carrier mobility ()
within Lh = Le= 2 μm of the junction. If
and diffusion coefficient (D) are measured
the depletion width is 1 μm, calculate the short-
independently using Haynes-Shockley
circuit current and the open-circuit voltage for
experiment. 12
this cell. 4
(b) A p-type Si sample is used in the Haynes-
7. (a) Discuss in detail Zener & Avalanche
Shockley experiment. The length of the sample
mechanisms of junction breakdown. Describe
is 2 cm. and two probes are separated by 1.8
the effect of temperature on Zener & Avalanche
cm. Voltage applied at the two ends in 5 V. A
breakdown voltages. Also explain the working
pulse arrives at the collection point at 0.608 ms,
of voltage regulator circuit using Zener diode
and the separation of the pulse is 180 sec.
for variation in supply voltage and load
Calculate mobility and diffusion coefficient for
resistance. 12
minority carriers. 4
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3. (a) What are direct and indirect band gap

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(b) If the depletion capacitance of a p-n junction

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semiconductors ? Discuss the variation of band
diode is Cd,O at equilibrium and the built-in
gap with alloy composition in AlXGa1–xAs.
potential is 0.5 V, how much reverse-bias voltage
Explain why GaAs cannot be used to fabricate
would have to be applied to reduce the depletion
LED in visible region. Although it is a direct
capacitance to 0.5 Cd.O. 4
band gap semiconductor. 10
Unit-IV (b) Write the expression for conductivity of a
8. (a) Discuss the metallization ICs using thermal and semiconductor sample. Show that the minimum
e-beam evaporation techniques. Out of these two conductivity σ min  of this semiconductor sample

techniques, which one is preferred to minimize μp

occurs when ne = ni and σ min =2 en μe μp .
the contamination from crucible/boat material μn i

and why ? 8 6
Unit-II
(b) Define active and passive circuit components
with examples. Describe the fabrication of IC 4. (a) Discuss diffusion of carriers in semiconductors.

resistor and monolithic diode in ICs. 8 If both an electric field and carrier concentration
gradient are present, then show that total current
9. In context of Planer Technology of IC fabrication, density for electrons and holes are given as
explain the following processes in terms of their dn(x)
Jn(x) = qnn(x)Ex+qDn &
requirement and technique : 4×4=16 dx
(a) Single Crystal Growth
Jp(x) = qp p(x)Ex–qDp dp(x) . 12
dx
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