‫ﺷﻤﺎره داﻧﺸﺠﻮﻳﻲ ‪40027784‬‬ ‫ﺣﺴﻴﻦ ﺻﺪارت‬

‫‪ -2‬واﺣﺪ ﻫﺎي ‪ Entity‬و ‪Architecture‬را ﺑﺮاي ﻳﻚ ﻣﺒﺪل ‪ BCD‬ﺑﻪ ﻧﻤﺎﻳﺸﮕﺮ ‪ 7‬ﻗﺴﻤﺘﻲ ﺑﻨﻮﻳﺴﻴﺪ‪ .‬ﻣﺪار ﻓﻮق را‬
‫روي ﻳﻚ ﺗﺮاﺷﻪ ﻗﺎﺑﻞ ﺑﺮﻧﺎﻣﻪ رﻳﺰي ﭘﻴﺎده ﺳﺎزي ﻛﻨﻴﺪ‪.‬‬

‫در اﻳﻦ ﻣﺜﺎل از ﻳﻚ ﻧﻤﺎﻳﺸﮕﺮ ‪ 7‬ﻗﺴﻤﺘﻲ ﻛﺎﺗﺪ ﻣﺸﺘﺮك اﺳﺘﻔﺎده ﻛﺮدﻳﻢ‪ .‬ﺟﺪول درﺳﺘﻲ زﻳﺮ ﺑﺮ اﺳﺎس ورودي ﻫﺎي‬
‫‪ BCD‬ﭘﻮرت ‪ A‬ﻣﻲ ﺑﺎﺷﺪ ﻛﻪ ﺑﺼﻮرت ‪ Vector‬ﺗﻌﺮﻳﻒ ﺷﺪه اﺳﺖ‪ .‬ﺧﺮوﺟﻲ آن ﺷﺎﻣﻞ ‪ 7‬ﻗﺴﻤﺖ ﺳﮕﻤﻨﺖ اﺳﺖ ﻛﻪ‬
‫ﺗﻮﺳﻂ ‪ Vector‬ﻫﻔﺖ ﺑﻴﺘﻲ ﺗﻌﺮﻳﻒ ﻣﻲ ﺷﻮد‪ .‬ﺣﺎﻟﺖ ‪ 1‬ﺑﻤﻌﻨﻲ روﺷﻦ ﺑﻮدن آن در ﻧﻈﺮ ﮔﺮﻓﺘﻪ ﻣﻲ ﺷﻮد‪.‬‬

‫ﻛﺪ ‪ HEX‬در ﺳﺘﻮن آﺧﺮ از ﺣﺎﻟﺖ ﻫﺎي ﻣﺨﺘﻠﻒ ‪ a,b,c,d,e,f,g‬ﺑﻪ‬

‫‪a‬‬ ‫دﺳﺖ آﻣﺪه اﺳﺖ‪.‬‬

‫‪f‬‬ ‫‪b‬‬ ‫در اﻳﻦ ﺑﺮﻧﺎﻣﻪ از دﺳﺘﻮراﻟﻌﻤﻞ ‪ Case‬اﺳﺘﻔﺎده ﻣﻲ ﺷﻮد و ﺣﺎﻟﺖ ﻫﺎي‬
‫‪g‬‬ ‫ﻣﺨﺘﻠﻒ ورودي ﺑﻪ ﺧﺮوﺟﻲ ﺗﺨﺼﻴﺺ داده ﻣﻲ ﺷﻮد‪.‬‬

‫‪e‬‬ ‫‪c‬‬ ‫ﺑﺮاي اﻳﻨﻜﻪ ﺑﺘﻮاﻧﻴﻢ در اﻧﺘﺼﺎب ﻫﺎ از اﻋﺪاد ‪ HEX‬اﺳﺘﻔﺎده ﻛﻨﻴﻢ ﺑﻪ‬
‫ﺟﺎي ‪ 7‬ﻋﺪد ﺧﺮوﺟﻲ در اﻳﻦ ﻣﺜﺎل ‪ 8‬ﻋﺪد ﺧﺮوﺟﻲ در ﻧﻈﺮ ﮔﺮﻓﺘﻪ و‬
‫‪d‬‬ ‫ﻳﻜﻲ از ﭘﺎﻳﻪ ﻫﺎ را ﺑﻼ اﺳﺘﻔﺎده در ﻧﻈﺮ ﻣﻲ ﮔﻴﺮﻳﻢ‪.‬‬
‫;"‪segment <= X"7F‬‬
 ‫ اﻣﻜﺎن ﭘﺬﻳﺮ اﺳﺖ‬Process ‫ ﻓﻘﻂ در‬case ‫ﻻزم ﺑﻪ ذﻛﺮ اﺳﺖ اﺳﺘﻔﺎده از دﺳﺘﻮر‬

0 1 2 3 4 5 6 7

8 9 A b C d E F

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity B27S is
Port ( BCD : in STD_LOGIC_VECTOR (3 downto 0);
segment : out STD_LOGIC_VECTOR (7 downto 0));
end B27S;

architecture Behavioral of B27S is

begin
PROCESS (BCD) BEGIN

case BCD is
when "0000" => segment <= X"3F";
when "0001" => segment <= X"06";
when "0010" => segment <= X"5B";
when "0011" => segment <= X"4F";
when "0100" => segment <= X"66";
when "0101" => segment <= X"6D";
when "0110" => segment <= X"7D";
when "0111" => segment <= X"07";
when "1000" => segment <= X"7F";
when "1001" => segment <= X"6F";
‫"‪when "1010‬‬ ‫;"‪=> segment <= X"77‬‬
‫"‪when "1011‬‬ ‫;"‪=> segment <= X"7C‬‬
‫"‪when "1100‬‬ ‫;"‪=> segment <= X"39‬‬
‫"‪when "1101‬‬ ‫;"‪=> segment <= X"5E‬‬
‫"‪when "1110‬‬ ‫;"‪=> segment <= X"79‬‬
‫‪when others‬‬ ‫;"‪=> segment <= X"71‬‬
‫;‪end case‬‬

‫;‪END PROCESS‬‬
‫;‪end Behavioral‬‬

‫ﻧﺘﻴﺠﻪ ﺑﺮﻧﺎﻣﻪ در ﺗﺴﺖ ﺑﻨﭻ ﺑﻪ ازاء ﺗﻤﺎﻣﻲ ورودي ﻫﺎي ﻣﺨﺘﻠﻒ ‪ 16‬ﺣﺎﻟﺖ ﺑﺎ در ﻧﻈﺮ ﮔﺮﻓﺘﻦ ﺣﺎﻟﺖ ﻫﺎي ‪A,B,C,D,E,F‬‬
‫ﺑﺎﺷﺪ‪.‬‬ ‫ﺑﺼﻮرت زﻳﺮ اﺳﺖ‪ .‬ﺗﺎﺧﻴﺮ در ﺷﺒﻴﻪ ﺳﺎز ﺑﺮاي ﻫﺮ ﻣﺮﺣﻠﻪ ‪ 50‬ﻧﺎﻧﻮ ﺛﺎﻧﻴﻪ ﻣﻲ‬
 :‫ﻛﺪ ﺗﺴﺖ ﺑﻨﭻ ﺑﺼﻮرت زﻳﺮ ﻣﻲ ﺑﺎﺷﺪ‬
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY bench7 IS
END bench7;

ARCHITECTURE behavior OF bench7 IS

COMPONENT B27S
PORT(
BCD : IN std_logic_vector(3 downto 0);
segment : OUT std_logic_vector(7 downto 0)
;(
END COMPONENT;

-- Inputs
signal BCD : std_logic_vector(3 downto 0) := (others => '0');

--Outputs
signal segment : std_logic_vector(7 downto 0);

--constant <clock>_period : time := 10 ns;

BEGIN

--Instantiate the Unit Under Test (UUT)

uut: B27S PORT MAP (
BCD => BCD,
segment => segment );
stim_proc: process
begin
wait for 50 ns; BCD <= X"0";
 wait for 50 ns; BCD <= X"1";
wait for 50 ns; BCD <= X"2";
wait for 50 ns; BCD <= X"3";
wait for 50 ns; BCD <= X"4";
wait for 50 ns; BCD <= X"5";
wait for 50 ns; BCD <= X"6";
wait for 50 ns; BCD <= X"7";
wait for 50 ns; BCD <= X"8";
wait for 50 ns; BCD <= X"9";
wait for 50 ns; BCD <= X"A";
wait for 50 ns; BCD <= X"B";
wait for 50 ns; BCD <= X"C";
wait for 50 ns; BCD <= X"D";
wait for 50 ns; BCD <= X"E";
wait for 50 ns; BCD <= X"F";
wait;
end process;
END;