S912 Datasheet Revision 0.

Bit(s) R/W Default Description

19 RW 0 Auto stop count 4 Wr_en
18:16 RW 0 Auto stop count 4
15 RW 0 Auto stop count 3 Wr_en
14:12 RW 0 Auto stop count 3
11 RW 0 Auto stop count 2 Wr_en
10:8 RW 0 Auto stop count 2
7 RW 0 Auto stop count 1 Wr_en
6:4 RW 0 Auto stop count 1
3 RW 0 Auto stop count 0 Wr_en
2:0 RW 0 Auto stop count 0

DEMUX_CHANNEL_RESET_O 0x3d
Bit(s) R/W Default Description

31:0 R 0 Bit 31:0 reset channel status - Each Bit reset each channel

DEMUX_SCRAMBLING_STATE_O 0x3e
Bit(s) R/W Default Description

31:0 R 0 Scrambling state of each channel

DEMUX_CHANNEL_ACTIVITY_O 0x3f
Bit(s) R/W Default Description

31:0 R 0 Channel activity of each channel

DEMUX_STAMP_CTL_O 0x40
Bit(s) R/W Default Description
4 RW 0 video_stamp_use_dts
3 RW 0 audio_stamp_sync_1_en
2 RW 0 audio_stamp_insert_en
1 RW 0 video_stamp_sync_1_en
0 RW 0 video_stamp_insert_en

DEMUX_VIDEO_STAMP_SYNC_0_O 0x41
Bit(s) R/W Default Description

31:0 RW 0 Video stamp sync [63:32]

DEMUX_VIDEO_STAMP_SYNC_1_O 0x42
Bit(s) R/W Default Description

31:0 RW 0 Video stamp sync [31:0]

DEMUX_AUDIO_STAMP_SYNC_0_O 0x43
Bit(s) R/W Default Description

31:0 RW 0 Aideo stamp sync [63:32]

DEMUX_AUDIO_STAMP_SYNC_1_O 0x44
Bit(s) R/W Default Description

31:0 RW 0 Aideo stamp sync [31:0]

DEMUX_SECTION_RESET_O 0x45

131/554 AMLOGIC, Inc. Proprietary

 S912 Datasheet Revision 0.1

Bit(s) R/W Default Description

Write : Bit[4:0] secter filter number for reset Read : select according to
output_section_buffer_valid: per bit per section buffer valid status or
31:0 R 0 section_buffer_ignore

DEMUX_INPUT_TIMEOUT_C_O 0x46
Bit(s) R/W Default Description

31:0 RW 0 channel_reset_timeout_disable

DEMUX_INPUT_TIMEOUT_O 0x47
Bit(s) R/W Default Description
31 RW 0 no_match_reset_timeout_disable
30:0 RW 0 input_time_out_int_cnt (0 -- means disable) Wr-setting, Rd-count

DEMUX_PACKET_COUNT_O 0x48
Bit(s) R/W Default Description

31:0 RW 0 channel_packet_count_disable

DEMUX_PACKET_COUNT_C_O0x49
Bit(s) R/W Default Description
31 RW 0 no_match_packet_count_disable
30:0 RW 0 input_packet_count

DEMUX_CHAN_RECORD_EN_O 0x4a
Bit(s) R/W Default Description

31:0 RW 0xffffffff channel_record_enable

DEMUX_CHAN_PROCESS_EN_O 0x4b
Bit(s) R/W Default Description

31:0 RW 0xffffffff channel_process_enable

DEMUX_SMALL_SEC_CTL_O 0x4c
Bit(s) R/W Default Description
31:24 RW 0 small_sec_size ((n+1) * 256 Bytes)
23:16 RW 0 small_sec_rd_ptr
15:8 RW 0 small_sec_wr_ptr
7:2 RW 0 reserved
1 RW 0 small_sec_wr_ptr_wr_enable
0 RW 0 small_section_enable

132/554 AMLOGIC, Inc. Proprietary

 S912 Datasheet Revision 0.1

27. Video Output

27.1 Overview
This section describes S912 -module, including RDMA sub-module, HDMI sub-module and the CVBS sub-module.

27.2 VPU
VPU is designed as the interface of the video input module and the video out module. The main function of VPU is to get data
from DDR and deliver it to CVBS or HDMITX based on different format.

VPU Registers

VPU_VIU_VENC_MUX_CTRL 0x271a
Bit(s) R/W Default Description
11-8 R/W 0 VIU_VDIN_SEL_DATA: Select which data to VDI6 path, must clear it first before switching the data.

Select ENCP data to VDI6

7-4 R/W 0 VIU_VDIN_SEL_CLK: Select which clock to VDI6 path, must clear it first before switching the clock.

3-2 R/W 0 VIU2_SEL_VENC: Select which one of the encI/P/T/L that Viu2 connects to.
0: ENCL
1: ENCI
2: ENCP
3: ENCT
1-0 R/W 0 VIU1_SEL_VENC: Select which one of the encI/P/T/L that Viu1 connects to.
0: ENCL
1: ENCI
2: ENCP
3: ENCT

VPU_HDMI_SETTING 0x271b
Bit(s) R/W Default Description
15-12 R/W 0 RD_RATE: Read rate to the async FIFO between VENC and HDMI.
0: One read every rd_clk
1: One read every 2 rd_clk
2: One read every 3 rd_clk

15: One read every 16 rd_clk

11-8 R/W 0 WR_RATE: Write rate to the async FIFO between VENC and HDMI.
0: One write every wr_clk
1: One write every 2 wr_clk
2: One write every 3 wr_clk

15: One write every 16 wr_clk

7-5 R/W 0 DATA_COMP_MAP: Input data is CrYCr(BRG), map the output data to desired format:
0: output CrYCb (BRG)
1: output YCbCr (RGB)
2: output YCrCb (RBG)
3: output CbCrY (GBR)

133/554 AMLOGIC, Inc. Proprietary

 S912 Datasheet Revision 0.1

Bit(s) R/W Default Description

4: output CbYCr (GRB)
5: output CrCbY (BGR)
6,7: Reserved
4 R/W 0 INV_DVI_CLK: If true, invert the polarity of clock output to external DVI interface. (NOT internal HDMI).
3 R/W 0 INV_VSYNC: If true, invert the polarity of VSYNC input from VENC
2 R/W 0 INV_HSYNC: If true, invert the polarity of HSYNC input from VENC
1-0 R/W 0 SRC_SEL: Select which HDMI source from between ENCI and ENCP.

data to HDMI

ENCI_INFO_READ 0x271c
Bit(s) R/W Default Description
31-29 R 0 Current ENCI field status.
28-25 R 0 Reserved
24-16 R 0 Current ENCI line counter status.
15-11 R 0 Reserved
10-0 R 0 Current ENCI pixel counter status.

ENCP_INFO_READ 0x271d
Bit(s) R/W Default Description
31-29 R 0 Current ENCP field status.
28-16 R 0 Current ENCP line counter status.
15-13 R 0 Reserved
12-0 R 0 Current ENCP pixel counter status.

ENCT_INFO_READ 0x271e
Bit(s) R/W Default Description
31-29 R 0 Current ENCT field status.
28-16 R 0 Current ENCT line counter status.
15-13 R 0 Reserved
12-0 R 0 Current ENCT pixel counter status.

ENCL_INFO_READ 0x271f
Bit(s) R/W Default Description
31-29 R 0 Current ENCL field status.
28-16 R 0 Current ENCL line counter status.
15-13 R 0 Reserved
12-0 R 0 Current ENCL pixel counter status.

VPU_SW_RESET 0x2720
Bit(s) R/W Default Description
3 R/W 0 vpuarb2_mmc_arb_rst_n
2 R/W 0 vdisp_mmc_arb_rst_n
1 R/W 0 vdin_mmc_arb_rst_n
0 R/W 0 viu_rst_n

VPU_D2D3_MMC_CTRL 0x2721
Bit(s) R/W Default Description
30 R/W 0 d2d3_depr_req_sel, 0:vdisp_pre_arb, 1: vpuarb2_pre_arb
27-22 R/W 0x3f d2d3_depr_brst_num
21-16 R/W 0x2d d2d3_depr_id
14 R/W 0x0 d2d3_depw_req_sel, 0: vdin_pre_arb, 1: vdisp_pre_arb
11-6 R/W 0x3f d2d3_depw_brst_num
5-0 R/W 0x2e d2d3_depw_id

134/554 AMLOGIC, Inc. Proprietary