S912 Datasheet Revision 0.

23:16 R/W 0d25 reg_adp_hcti_con_2_gain0 : , default = 25 . unsigned , default = 25

15: 8 R/W 0d60 reg_adp_hcti_con_2_gain1 : , default = 60 . unsigned , default = 60
7: 0 R/W 0d0 reg_adp_hcti_con_2_gain2 : 0;, default = 0 . unsigned , default = 0

SRSHARP1_HCTI_CON_2_GAIN_1 0x32b2
Bit(s) R/W Default Description
31:24 R/W 0d96 reg_adp_hcti_con_2_gain3 : 96;, default = 96 . unsigned , default = 96
23:16 R/W 0d5 reg_adp_hcti_con_2_gain4 : 5;, default = 5 . unsigned , default = 5
15: 8 R/W 0d80 reg_adp_hcti_con_2_gain5 : 80;, default = 80 . unsigned , default = 80
7: 0 R/W 0d20 reg_adp_hcti_con_2_gain6 : 20;, default = 20 . unsigned , default = 20

SRSHARP1_HCTI_OS_MARGIN 0x32b3
Bit(s) R/W Default Description
7: 0 R/W 0d0 reg_adp_hcti_os_margin : : margin for hcti overshoot, default = 0 . unsigned , default = 0

SRSHARP1_HLTI_FLT_CLP_DC 0x32b4
Bit(s) R/W Default Description
28 R/W 0d1 reg_adp_hlti_en : , 0: no cti, 1: new cti, default = 1 . unsigned , default = 1
27:26 R/W 0d2 reg_adp_hlti_vdn_flt : , 0: no lpf; 1:[0,2,4,2,0], 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 2 . unsigned , default =
2
25:24 R/W 0d2 reg_adp_hlti_hdn_flt : , 0: no lpf; 1:[0, 0, 0, 4, 8, 4, 0, 0, 0], 2:[0, 0, 2, 4, 4, 4, 2, 0, 0], 3: [1, 2, 2, 2, 2, 2, 2, 2, 1],
default = 2. unsigned , default = 2
23:22 R/W 0d2 reg_adp_hlti_ddn_flt : , 0: no lpf; 1:[0,2,4,2,0], 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 2 . unsigned , default =
2
21:20 R/W 0d2 reg_adp_hlti_lpf0_flt : , 0:no filter; 1:sigma=0.75, 2: sigma = 1.0, 3: sigma = 1.5, default = 2 . unsigned , default
=2
19:18 R/W 0d2 reg_adp_hlti_lpf1_flt : , 0:no filter; 1:sigma= 2.0, 2: sigma = 3.0, 3: sigma = 4.0, default = 2 . unsigned , default
=2
17:16 R/W 0d2 reg_adp_hlti_lpf2_flt : , 0:no filter; 1:sigma=5.0, 2: sigma = 9.0, 3: sigma = 13.0, default = 2 . unsigned , default
=2
15:12 R/W 0d2 reg_adp_hlti_hard_clp_win : , window size, 0~8, default = 2 . unsigned , def
default = 2
11: 8 R/W 0d1 reg_adp_hlti_hard_win_min : , window size, 0~8, default = 1 . unsigned , default = 1
4 R/W 0d0 reg_adp_hlti_clp_mode : , 0: hard clip, 1: adaptive clip, default = 0 . unsigned , default = 0
2: 0 R/W 0d4 reg_adp_hlti_dc_mode : , 0:dn, 1:lpf0, 2:lpf1, 3:lpf2, 4: lpf3: 5: vdn result; 6/7:org, default = 4 . unsigned , default
=4

SRSHARP1_HLTI_BST_GAIN 0x32b5
Bit(s) R/W Default Description
31:24 R/W 0d40 reg_adp_hlti_bst_gain0 : : gain of the bandpass 0 (lpf1
(lpf1-lpf2)- LBP, default = 40 . unsigned , default =
40
23:16 R/W 0d48 reg_adp_hlti_bst_gain1 : : gain of the bandpass 1 (lpf0
(lpf0-lpf1)- BP, default = 48 . unsigned , default =
48
15: 8 R/W 0d32 reg_adp_hlti_bst_gain2 : : gain of the bandpass 2 (hdn-lpf0)- HP, default = 32 . unsigned , default =
32
7: 0 R/W 0d16 reg_adp_hlti_bst_gain3 : : gain of the unsharp band (yuvin-hdn) - US, default = 16 . unsigned , default
= 16

SRSHARP1_HLTI_BST_CORE 0x32b6
Bit(s) R/W Default Description
31:24 R/W 0d5 reg_adp_hlti_bst_core0 : : core of the bandpass 0 (lpf1-lpf2)- LBP, default = 5 . unsigned , default =
5
23:16 R/W 0d5 reg_adp_hlti_bst_core1 : : core of the bandpass 1 (lpf0-lpf1)- BP, default = 5 . unsigned , default =
5
15: 8 R/W 0d5 reg_adp_hlti_bst_core2 : : core of the bandpass 2 (hdn-lpf0)- HP, default = 5 . unsigned , default =
5
7: 0 R/W 0d3 reg_adp_hlti_bst_core3 : : core of the unsharp band (yuvin-hdn) - US, default = 3 . unsigned , default
=3

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 S912 Datasheet Revision 0.1

SRSHARP1_HLTI_CON_2_GAIN_0 0x32b7
Bit(s) R/W Default Description
31:29 R/W 0d2 reg_adp_hlti_con_mode : : con mode 0:[0, 0,-1, 1, 0, 0, 0]+[0, 0, 0, 1,-1, 0, 0], 1: [0, 0,-1, 0, 1, 0, 0], 2: [0,-1, 0, 0, 0,
1, 0], 3:[-1, 0, 0, 0, 0, 0, 1], 4: ....., default = 2. unsigned , default = 2
28:26 R/W 0d3 reg_adp_hlti_dx_mode : : dx mode 0: [-1 1 0]; 1~7: [-1 (2x+1)"0" 1], default = 3 . unsigned , default =
3
25:24 R/W 0d1 reg_adp_hlti_con_lpf : : lpf mode of the con: 0: [1 2 1]/4; 1:[1 2 2 2 1]/8, default = 1 . unsigned , default =
1
23:16 R/W 0d25 reg_adp_hlti_con_2_gain0 : 25;, default = 25 . unsigned , default = 25
15: 8 R/W 0d60 reg_adp_hlti_con_2_gain1 : 60;, default = 60 . unsigned , default = 60
7: 0 R/W 0d90 reg_adp_hlti_con_2_gain2 : 0;, default = 90 . unsigned , default = 90

SRSHARP1_HLTI_CON_2_GAIN_1 0x32b8
Bit(s) R/W Default Description
31:24 R/W 0d96 reg_adp_hlti_con_2_gain3 : 96;, default = 96 . unsigned , defa
default = 96
23:16 R/W 0d95 reg_adp_hlti_con_2_gain4 : 5;, default = 95 . unsigned , defa
default = 95
15: 8 R/W 0d80 reg_adp_hlti_con_2_gain5 : 80;, default = 80 . unsigned , default = 80
7: 0 R/W 0d20 reg_adp_hlti_con_2_gain6 : 20;, default = 20 . unsigned , defa
default = 20

SRSHARP1_HLTI_OS_MARGIN 0x32b9
Bit(s) R/W Default Description
7: 0 R/W 0d0 reg_adp_hlti_os_margin : : margin for hlti overshoot, default = 0 . unsigned , defaul
default = 0

SRSHARP1_VLTI_FLT_CON_CLP 0x32ba
Bit(s) R/W Default Description
14 R/W 0d1 reg_adp_vlti_en : : enable bit of vlti, default = 1 . unsigned , default = 1
13:12 R/W 0d3 reg_adp_vlti_hxn_flt : : 0: no dn; 1: [1 2 1]/4; 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 3 . unsigned , default =
3
11:10 R/W 0d3 reg_adp_vlti_dxn_flt : : 0: no dn; 1: [1 2 1]/4; 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 3 . unsigned , default =
3
9: 8 R/W 0d3 reg_adp_vlti_han_flt : : 0: no dn; 1: [1 2 1]/4; 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 3 . unsigned , default =
3
7: 6 R/W 0d3 reg_adp_vlti_dan_flt : : 0: no dn; 1: [1 2 1]/4; 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 3 . unsigned , default =
3
5: 4 R/W 0d2 reg_adp_vlti_dx_mode : : 0:[0:[-1 1] 1:[-1 0 -1]; 2/3: [-1 0 0 0 -1], default = 2 . unsigned , default = 2
2 R/W 0d1 reg_adp_vlti_con_lpf : : lpf mode of the con: 0: [1 2 1]/4; 1:[1 2 2 2 1]/8, default = 1 . unsigned , default =
1
0 R/W 0d1 reg_adp_vlti_hard_clp_win : : window size; 0: 1x3 window; 1: 1x5 window, default = 1 . unsigned ,
default = 1

SRSHARP1_VLTI_BST_GAIN 0x32bb
Bit(s) R/W Default Description
23:16 R/W 0d32 reg_adp_vlti_bst_gain0 : : gain to boost filter [-1 2 -1];, default = 32 . unsigned , default = 32
15: 8 R/W 0d32 reg_adp_vlti_bst_gain1 : : gain to boost filter [-1 0 2 0 -1];, default = 32 . unsigned , default = 32
7: 0 R/W 0d32 reg_adp_vlti_bst_gain2 : : gain to boost filter usf, default = 32 . unsigned , default = 32

SRSHARP1_VLTI_BST_CORE 0x32bc
Bit(s) R/W Default Description
23:16 R/W 0d5 reg_adp_vlti_bst_core0 : : coring to boost filter [-1 2 -1];, default = 5 . unsigned , default = 5
15: 8 R/W 0d5 reg_adp_vlti_bst_core1 : : coring to boost filter [-1 0 2 0 -1];, default = 5 . unsigned , default = 5
7: 0 R/W 0d3 reg_adp_vlti_bst_core2 : : coring to boost filter usf, default = 3 . unsigned , default = 3

SRSHARP1_VLTI_CON_2_GAIN_0 0x32bd
Bit(s) R/W Default Description
31:24 R/W 0d25 reg_adp_vlti_con_2_gain0 : 25;, default = 25 . unsigned , default = 25
23:16 R/W 0d69 reg_adp_vlti_con_2_gain1 : 60;, default = 69 . unsigned , default = 60
15: 8 R/W 0d90 reg_adp_vlti_con_2_gain2 : 0;, default = 90 . unsigned , default = 90

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 S912 Datasheet Revision 0.1

7: 0 R/W 0d96 reg_adp_vlti_con_2_gain3 : 96;, default = 96 . unsigned , default = 96

SRSHARP1_VLTI_CON_2_GAIN_1 0x32be
Bit(s) R/W Default Description
31:24 R/W 0d95 reg_adp_vlti_con_2_gain4 : 5;, default = 95 . unsigned , default = 95
23:16 R/W 0d80 reg_adp_vlti_con_2_gain5 : 80;, default = 80 . unsigned , default = 80
15: 8 R/W 0d20 reg_adp_vlti_con_2_gain6 : 20;, default = 20 . unsigned , default = 20
7: 0 R/W 0d0 reg_adp_vlti_os_margin : : margin for vlti overshoot, default = 0 . unsigned , default = 0

SRSHARP1_VCTI_FLT_CON_CLP 0x32bf
Bit(s) R/W Default Description
14 R/W 0d1 reg_adp_vcti_en : : enable bit of vlti, default = 1 . unsigned , default = 1
13:12 R/W 0d3 reg_adp_vcti_hxn_flt : : 0: no dn; 1: [1 2 1]/4; 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 3 . unsigned , default =
3
11:10 R/W 0d3 reg_adp_vcti_dxn_flt : : 0: no dn; 1: [1 2 1]/4; 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4,
4, default = 3 . unsigned , default =
3
9: 8 R/W 0d3 reg_adp_vcti_han_flt : : 0: no dn; 1: [1 2 1]/4; 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 3 . unsigned , default =
3
7: 6 R/W 0d3 reg_adp_vcti_dan_flt : : 0: no dn; 1: [1 2 1]/4; 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 3 . unsigned , default =
3
5: 4 R/W 0d2 reg_adp_vcti_dx_mode : : 0:[-1 1] 1:[-1 0 -1]; 2/3: [-1 0 0 0 -1],
1], default = 2 . unsigned , default = 2
2 R/W 0d1 reg_adp_vcti_con_lpf : : lpf mode of the con: 0: [1 2 1]/4; 1:[1 2 2 2 1]/8, default = 1 . unsigned , default =
1
0 R/W 0d1 reg_adp_vcti_hard_clp_win : : window size; 0: 1x3 window; 1: 1x5 window, default = 1 . unsigned ,
default = 1

SRSHARP1_VCTI_BST_GAIN 0x32c0
Bit(s) R/W Default Description
23:16 R/W 0d0 reg_adp_vcti_bst_gain0 : : gain to boost filter [[-1 2 -1];, default = 0 . unsigned , default = 0
15: 8 R/W 0d0 reg_adp_vcti_bst_gain1 : : gain to boost filter [[-1 0 2 0 -1];, default = 0 . unsigned , default = 0
7: 0 R/W 0d0 reg_adp_vcti_bst_gain2 : : gain to boost filter usf, default = 0 . unsigned , default = 0

SRSHARP1_VCTI_BST_CORE 0x32c1
Bit(s) R/W Default Description
23:16 R/W 0d0 reg_adp_vcti_bst_core0 : : coring to boost filter [[-1 2 -1];, default = 0 . unsigned , default = 0
15: 8 R/W 0d0 reg_adp_vcti_bst_core1 : : coring to boost filter [[-1 0 2 0 -1];, default = 0 . unsigned , default = 0
7: 0 R/W 0d0 reg_adp_vcti_bst_core2 : : coring to boost filter usf, default = 0 . unsigned , default = 0

SRSHARP1_VCTI_CON_2_GAIN_0 0x32c2
Bit(s) R/W Default Description
31:24 R/W 0d25 reg_adp_vcti_con_2_gain0 : 25;, default = 25 . unsigned , defa
default = 25
23:16 R/W 0d60 reg_adp_vcti_con_2_gain1 : 60;, default = 60 . unsigned , default = 60
15: 8 R/W 0d90 reg_adp_vcti_con_2_gain2 : 0;, default = 90 . unsigned , default = 90
7: 0 R/W 0d96 reg_adp_vcti_con_2_gain3 : 96;, default = 96 . unsigned , default = 96

SRSHARP1_VCTI_CON_2_GAIN_1 0x32c3
Bit(s) R/W Default Description
31:24 R/W 0d95 reg_adp_vcti_con_2_gain4 : 5;, default = 95 . unsigned , default = 95
23:16 R/W 0d80 reg_adp_vcti_con_2_gain5 : 80;, default = 80 . unsigned , default = 80
15: 8 R/W 0d20 reg_adp_vcti_con_2_gain6 : 20;, default = 20 . unsigned , default = 20
7: 0 R/W 0d0 reg_adp_vcti_os_margin : : margin for vcti overshoot, default = 0 . unsigned , default = 0

SRSHARP1_SHARP_3DLIMIT 0x32c4
Bit(s) R/W Default Description
28:16 R/W 0d0 reg_3d_mid_width : ,width of left part of 3d input, dft = half size of input width default = 0 . unsigned , default
= 960

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 S912 Datasheet Revision 0.1

12: 0 R/W 0d0 reg_3d_mid_height : ,height of left part of 3d input, dft = half size of input height default = 0 . unsigned , default
= 540

SRSHARP1_DNLP_EN 0x32c5
Bit(s) R/W Default Description
0 R/W 0d1 reg_dnlp_en : . unsigned , default = 1

SRSHARP1_DNLP_00 0x32c6
Bit(s) R/W Default Description
31: 0 R/W 0x08060402 reg_dnlp_ygrid0 : : dnlp00 . unsigned , default = 0x08060402

SRSHARP1_DNLP_01 0x32c7
Bit(s) R/W Default Description
31: 0 R/W 0x100e0c0a reg_dnlp_ygrid1 : : dnlp01 . unsigned , default = 0x100e0c0a

SRSHARP1_DNLP_02 0x32c8
Bit(s) R/W Default Description
31: 0 R/W 0x1a171412 reg_dnlp_ygrid2 : : dnlp02 . unsigned , default = 0x1a171412

SRSHARP1_DNLP_03 0x32c9
Bit(s) R/W Default Description
31: 0 R/W 0x2824201d reg_dnlp_ygrid3 : : dnlp03 . unsigned , default = 0x2824201d

SRSHARP1_DNLP_04 0x32ca
Bit(s) R/W Default Description
31: 0 R/W 0x3834302c reg_dnlp_ygrid4 : : dnlp04 . unsigned , default = 0x3834302c

SRSHARP1_DNLP_05 0x32cb
Bit(s) R/W Default Description
31: 0 R/W 0x4b45403c reg_dnlp_ygrid5 : : dnlp05 . unsigned , default = 0x4b45403c

SRSHARP1_DNLP_06 0x32cc
Bit(s) R/W Default Description
31: 0 R/W 0x605b5550 reg_dnlp_ygrid6 : : dnlp06 . unsigned , default = 0x605b5550

SRSHARP1_DNLP_07 0x32cd
Bit(s) R/W Default Description
31: 0 R/W 0x80787068 reg_dnlp_ygrid7 : : dnlp07 . unsigned , default = 0x80787068

SRSHARP1_DNLP_08 0x32ce
Bit(s) R/W Default Description
31: 0 R/W 0xa0989088 reg_dnlp_ygrid8 : : dnlp08 . unsigned , default = 0xa0989088

SRSHARP1_DNLP_09 0x32cf
Bit(s) R/W Default Description
31: 0 R/W 0xb8b2aca6 reg_dnlp_ygrid9 : : dnlp09 . unsigned , default = 0xb8b2aca6

SRSHARP1_DNLP_10 0x32d0
Bit(s) R/W Default Description
31: 0 R/W 0xc8c4c0bc reg_dnlp_ygrid10 : : dnlp10 . unsigned , default = 0xc8c4c0bc

SRSHARP1_DNLP_11 0x32d1
Bit(s) R/W Default Description
31: 0 R/W 0xd4d2cecb reg_dnlp_ygrid11 : : dnlp11 . unsigned , default = 0xd4d2cecb

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 S912 Datasheet Revision 0.1

SRSHARP1_DNLP_12 0x32d2
Bit(s) R/W Default Description
31: 0 R/W 0xdad8d7d6 reg_dnlp_ygrid12 : : dnlp12 . unsigned , default = 0xdad8d7d6

SRSHARP1_DNLP_13 0x32d3
Bit(s) R/W Default Description
31: 0 R/W 0xe2e0dedc reg_dnlp_ygrid13 : : dnlp13 . unsigned , default = 0xe2e0dedc

SRSHARP1_DNLP_14 0x32d4
Bit(s) R/W Default Description
31: 0 R/W 0xf0ece8e4 reg_dnlp_ygrid14 : : dnlp14 . unsigned , default = 0xf0ece8e4

SRSHARP1_DNLP_15 0x32d5
Bit(s) R/W Default Description
31: 0 R/W 0xfffcf8f4 reg_dnlp_ygrid15 : : dnlp15 . unsigned , default = 0xfffcf8f4

SRSHARP1_DEMO_CRTL 0x32d6
Bit(s) R/W Default Description
18:17 R/W 0d2 demo_disp_position : . unsigned , default = 2
16 R/W 0d0 demo_hsvsharp_enable : . unsigned , default = 0
12: 0 R/W 0d360 demo_left_top_screen_width : : . unsigned , de
default = 360

SRSHARP1_SHARP_SR2_CTRL 0x32d7
Bit(s) R/W Default Description
31:25 R/W reserved
24 R/W 0 sr2_dejaggy_en, 1 to enable dejaggy
23:22 R/W reserved
21:16 R/W 24 sr2_pk_la_err_dis_rate, low angle and high angle error should not be no less than nearby_error* rate/64
15: 8 R/W 16 sr2_pk_sad_diag_gain, gain to sad[2] and sad[6], 16 normalized to 1
7 R/W 0 sr2_vert_outphs, vertical output pixel phase, 0: 0 phase; 1: 1/2 phase
6 R/W 0 sr2_horz_outphs, horizontal output pixel phase, 0: 0 phase; 1: 1/2 phase
5 R/W 0 sr2_vert_ratio , vertical scale ratio, 0
0-> 1:1; 1-> 1:2
4 R/W 0 sr2_horz_ratio , horizontal scale ratio, 0
0-> 1:1; 1-> 1:2
3 R/W 1 sr2_ bic_norm , normalization of bicubical: 0: 128; 1: 64
2 R/W 0 sr2_ enable , 1 to enable super scaler
1 R/W 0 sr2_ sharp_prc_lr_hbic,
0 R/W 0 sr2_ sharp_prc_lr, 1: LTI/CTI/NR/Peaking processing using LR grid. 0: on HR grid; 1:on LR grid, horizontally no
upscale, but using simple bic.

SRSHARP1_SHARP_SR2_YBIC_HCOEF0
_SR2_YBIC_HCOEF0 0x32d8
Bit(s) R/W Default Description
31:24 R/W 0 sr2_y_bic_hcoeff03, signed
23:16 R/W 0 sr2_y_bic_hcoeff02, signed
15: 8 R/W 64 sr2_y_bic_hcoeff01, signed
7: 0 R/W 0 sr2_y_bic_hcoeff00, signed

SRSHARP1_SHARP_SR2_YBIC_HCOEF1 0x32d9
Bit(s) R/W Default Description
31:24 R/W -4 sr2_y_bic_hcoeff13 , signed
23:16 R/W 36 sr2_y_bic_hcoeff12 , signed
15: 8 R/W 36 sr2_y_bic_hcoeff11 , signed
7: 0 R/W -4 sr2_y_bic_hcoeff10 , signed

SRSHARP1_SHARP_SR2_CBIC_HCOEF0 0x32da

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 S912 Datasheet Revision 0.1

Bit(s) R/W Default Description

31:24 R/W 0 sr2_c_bic_hcoeff03 , signed
23:16 R/W 21 sr2_c_bic_hcoeff02 , signed
15: 8 R/W 22 sr2_c_bic_hcoeff01 , signed
7: 0 R/W 21 sr2_c_bic_hcoeff00 , signed

SRSHARP1_SHARP_SR2_CBIC_HCOEF1 0x32db
Bit(s) R/W Default Description
31:24 R/W -4 sr2_c_bic_hcoeff13 , signed
23:16 R/W 36 sr2_c_bic_hcoeff12 , signed
15: 8 R/W 36 sr2_c_bic_hcoeff11 , signed
7: 0 R/W -4 sr2_c_bic_hcoeff10 , signed

SHARP_SR2_YBIC_VCOEF0 0x32dc
Bit(s) R/W Default Description
31:24 R/W 0 sr2_y_bic_vcoeff03 , signed
23:16 R/W 0 sr2_y_bic_vcoeff02 , signed
15: 8 R/W 64 sr2_y_bic_vcoeff01 , signed
7: 0 R/W 0 sr2_y_bic_vcoeff00 , signed

SRSHARP1_SHARP_SR2_YBIC_VCOEF1 0x32dd
Bit(s) R/W Default Description
31:24 R/W -4 sr2_y_bic_vcoeff13 , signed
23:16 R/W 36 sr2_y_bic_vcoeff12 , signed
15: 8 R/W 36 sr2_y_bic_vcoeff11 , signed
7: 0 R/W -4 sr2_y_bic_vcoeff10 , signed

SRSHARP1_SHARP_SR2_CBIC_VCOEF0 0x32de
Bit(s) R/W Default Description
31:24 R/W 0 sr2_c_bic_vcoeff03 , signed
23:16 R/W 21 sr2_c_bic_vcoeff02 , signed
15: 8 R/W 22 sr2_c_bic_vcoeff01 , signed
7: 0 R/W 21 sr2_c_bic_vcoeff00 , signed

SRSHARP1_SHARP_SR2_CBIC_VCOEF1 0x32df
Bit(s) R/W Default Description
31:24 R/W -4 sr2_c_bic_vcoeff13 , signed
23:16 R/W 36 sr2_c_bic_vcoeff12 , signed
15: 8 R/W 36 sr2_c_bic_vcoeff11 , signed
7: 0 R/W -4
4 sr2_c_bic_vcoeff10 , signed

SRSHARP1_SHARP_SR2_MISC 0x32e0
Bit(s) R/W Default Description
31:2 R/W reserved
1 R/W 0 sr2_cmpmux_bef , 0 : no swap for YUV/RGB; 1: swap for YUV/RGB, YUV/RGB->UVY/GBR
0 R/W 0 sr2_cmpmux_aft , 0 : no swap for YUV/RGB; 1: swap for YUV/RGB, UVY/GBR->YUV/RGB

SRSHARP1_SHARP_DEJ2_PRC 0x32e1
Bit(s) R/W Default Description
31:24 R/W 5 sr2_dejaggy2_hcon_thrd, hcon threshold, only pixels with hcon equal or larger than this value can be detected
as jaggy2
23:16 R/W 30 sr2_dejaggy2_svdif_thrd, abs(sum(vdif[4])) threshold to decide jaggy2.
15: 8 R/W 32 sr2_dejaggy2_svdif_rate, sum(abs(vdif[4])) <= (rate*abs(sum(vdif[4]))/16), rate to decide jaggy2
7: 0 R/W -3 sr2_dejaggy2_vdif_thrd, vdif threshold for same trend decision, these value is the margin for not same trend,
if >0, means need to be same trend, if <0, can be a little bit glitch.

259/554 AMLOGIC, Inc. Proprietary