EXPERIMENT NUMBER: 6

Date of Performance :

Date of Submission :

AIM : Design and simulate S-R Latch circuit.

SOFTWARE REQUIRED : dsch 3.5, Microwind 3.5

CIRCUIT DIAGRAM :

THEORY :

1) Operation of S-R Lach : A latch is an example of a bistable multivibrator, that is, a device with exactly
two stable states. These states are high-output and low-output. A latch has a feedback path, so
information can be retained by the device. Therefore latches can be memory devices, and can store one
bit of data for as long as the device is powered.
An SR latch (Set/Reset) is an asynchronous device. It works independently of control signals and relies
only on the state of the S and R inputs. An SR latch can be created with two NOR gates that have a cross-
feedback loop.
 When a high is applied to the Set line of an SR latch, the Q output goes high (and Q low). The feedback
mechanism, however, means that the Q output will remain high, even when the S input goes low again.
This is how the latch serves as a memory device. Conversely, a high input on the Reset line will drive the
Q output low (and Q high), effectively resetting the latch's "memory". When both inputs are low, the
latch "latches" – it remains in its previously set or reset state.
When both inputs are high at once, however, there is a problem: it is being told to simultaneously
produce a high Q and a low Q. This produces a "race condition" within the circuit. Ideally, both gates are
identical and the device will be in an undefined state for an indefinite period.

2) Design of S-R Latch : CMOS SR latch based on NOR gate is shown in the figure given below.

If the S is equal to VOH and the R is equal to VOL, both of the parallel-connected transistors M1 and M2 will be ON.
The voltage on node Q will assume a logic-low level of V OL = 0. At the same time, both M3 and M4 are turned off,
which results in a logic-high voltage V OH at node Q. If the R is equal to V OH and the S is equal to VOL, M1 and M2
turned off and M3 and M4 turned on.

The operation modes of transistors are given below:

PROCEDURE : 1) Draw the circuit diagram using components from library in dsch software.

2) Simulate the circuit.

3) Click on timing diagram to get waveform.

4) Create a verilog file to get the verilog code.

5) Open and compile verilog file in microwind software.

6) Run the layout, start simulation and observe output waveforms.

RESULT : ‘printouts’

CONCLUSION : Thus simulation waveforms seen in the output window verifies the operation of S-R Latch.

SIGN and REMARK :