LIST OF EXPERIMENTS

1. Verification of Boolean Theorems using basic gates.

2. Design and implementation of combinational circuits using basic gates for arbitrary
functions, code converters.
3. Design and implement Half/Full Adder and Subtractor.
4. Design and implement combinational circuits using MSI devices:
5. 4-bit binary adder / subtractor
6. Parity generator / checker
7. Magnitude Comparator
8. Application using multiplexers
9. Design and implement shift-registers.
10. Design and implement synchronous counters.
11. Design and implement asynchronous counters.
12. Coding combinational circuits using VHDL.
13. Coding sequential circuits using VHDL.
14. Design and implementation of a simple digital system (Mini Project).
DEMORGAN ’S THEOREM:

a) (x+y)’=x’y’

x x+y (x+ y)’

U 4A U 5A
1
3 1 2
2
74A C 04
y 74A LS 1032A

TRUTH TABLE:

x Y (x+y)’ x’ y’ x’y’
0 0 1 1 1 1
0 1 0 1 0 0
1 0 0 0 1 0
1 1 1 0 0 1

1
EXPT NO : VERFICATION OF BOOLEAN THEORM USING
DATE : LOGIC GATES

AIM:

To design the following Boolean theorem and verify the truth table.

APPARATUS REQUIRED:

SI.NO APPARATUS NAME RANGE QUANTITY

1. Digital trainer kit - 1
2. IC’s 7432,7408,740 each
4
3. Connecting wires - As required

THEOREM:

DEMORGAN,S THEOREM:
(x+y)=x’y’
(xy)’=x’+y’

ABSORBTION THEOREM:
x+xy=x
x(x+y)=x

DISTRIBUTION THEOREM:
x+(y+z)=(x+y)+z
x(yz)=(xy)z

OTHER THEORM:
x+x’=x
x+x’=1
x*x=x

THEORY:
The theorem of the algebra can be shown the find mean of truth table in the truth
side relations are possible combination of variable involved the variable truth
verification of demorgan’s absorption theorem.

2
b) (xy)’=x’+y’

TRUTH TABLE:

x Y (xy)’ x’ y’ x’+y’

0 0 1 1 1 1
0 1 1 1 0 1
1 0 1 0 1 1
1 1 0 0 0 0

3
PROCEDURE:
1. Make a circuit connections are as the circuit diagram.
2. Given the VCC ’s on all IC’s.
3. Given the input and output for the following theorem connection in DTK.
4. Verify the output of the truth table for the following theorem.
(i) Demorgan’stheorem.
(ii) Distributive theorem.
(iii) Absorption theorem
(iv) Basic Boolean theorem.

DUALITY THEOREM:

 It is states that changing each states sign to an AND sign.

 Changing each AND sign to an OR sign.
 Complementing the 0’s & 1’s then general even
A(B+C)=AB+AC
A+(BC)=(A+B)(A+C)

PROCEDURE:
1. Making the circuit connection as for the circuit diagram.
2. Given the VCC &ground too all IC’s used in the circuit.
3. Verify the output with the following
(i) Demorgan ’s theorem.
(ii) Duality theorem.

4
ABSORBTION THEOREM:

(a) x+xy=x

TRUTH TABLE:

X y x+xy x

0 0 0 0
0 1 0 0
1 0 1 1
1 1 1 1

b) x(x+y)=x

TRUTH TABLE:

x Y x+y x(x+y) x

0 0 0 0 0
0 1 1 0 0
1 0 1 1 1
1 1 1 1 1

5
6
DISTRIBUTIVE THEOREM:

(a) x+(y+z)=(x+y)+z

TRUTH TABLE:

x y z y+z x+(y+z) x+y (x+y)+z

0 0 0 0 0 0 0
0 0 1 1 1 0 1
0 1 0 1 1 1 1
0 1 1 1 1 1 1
1 0 0 0 1 1 1
1 0 1 1 1 1 1
1 1 0 1 1 1 1
1 1 1 1 1 1 1

7
8
(b) x(yz)=(xy)z

TRUTH TABLE:

x Y z yz x(yz) xy (xy)z
0 0 0 0 0 0 0
0 0 1 0 0 0 0
0 1 0 0 0 0 0
0 1 1 1 0 0 0
1 0 0 0 0 0 0
1 0 1 0 0 0 0
1 1 0 0 0 1 0
1 1 1 1 1 1 1

9
10
OTHER THEOREM:

a) x+x=x
b) x+x’=1

TR
UTH TABLE:

x x x+x
0 0 0
1 1 1

TRUTH TABLE:

x x’ x+x’
0 1 1
1 0 1

11
12
DUALITY THEOREM:

TRUTH TABLE:

A B C A+BC (A+B)(A+C)
0 0 0 0 0
0 0 1 0 0
0 1 0 0 0
0 1 1 1 1
1 0 0 1 1
1 0 1 1 1
1 1 0 1 1
1 1 1 1 1

13
RESULT:

14
 Thus the Boolean theorem was verified using logic gates.

EXPRESSION:

Y=A’B’CD+AC’D+BC’

Y=A’C+B’

TRUTH TABLE:

A B C Y
0 0 0 1
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 0
1 1 1 0

K MAP:

BC B’C’ B’C BC BC’

A
A’ 1 1 1 0
A 1 1 0 0

LOGIC DIAGRAM:

15
EXPT NO : Design and implementation of combinational circuits
DATE : using basic gates for arbitrary functions, code converters

AIM:
To design and implement the combinational circuits using logic gates arbitrary
function and code converters and verify the truth table.

APPARATUS REQUIRED:

SI.NO APPARATUS QUANTITY

1 Digital trainer kit 1
2 IC 7408,7432,7411,7404 Each1

THEORY:
The availability of large variety of codes for the same discrete elements of
information results in the use of different codes by different systems. A conversion
circuit must be inserted between the two systems if each uses different codes for
same information. Thus, code converter is a circuit that makes the two systems
compatible even though each uses different binary code.
The bit combination assigned to binary code to gray code. Since each code
uses four bits to represent a decimal digit. There are four inputs and four outputs.
Gray code is a non-weighted code. The input variable are designated as B3, B2, B1,
B0 and the output variables are designated as C3, C2, C1, Co. from the truth table,
combinational circuit is designed. The Boolean functions are obtained from K-Map
for each output variable.
A code converter is a circuit that makes the two systems compatible even
though each uses a different binary code. To convert from binary code to Excess-3
code, the input lines must supply the bit combination of elements as specified by

16
code and the output lines generate the corresponding bit combination of code. Each
one of the four maps represents one of the four outputs of the circuit as a function of
the four input variables.
A two-level logic diagram may be obtained directly from the Boolean
expressions derived by the maps. These are various other possibilities for a logic
diagram that implements this circuit. Now the OR gate whose output is C+D has
been used to implement partially each of three outputs.

PROCEDURE:
A B C D Y 1. Connection are
0 0 0 0 0 made as per the circuit
0 0 0 1 1 diagram.
0 0 1 0 1 2. Inputs are given
0 0 1 1 1 and corresponding gates
0 1 0 0 1 are noted.
0 1 0 1 1 3. The truth table
0 1 1 0 0 for corresponding gates
0 1 1 1 0 are verified.
1 0 0 0 0
1 0 0 1 1
1 0 1 0 1
1 0 1 1 1
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0 EXPRESSION:

Y=A’B’CD’+AC’D+BC’

Y’=B’C’D’+AB+BC

TRUTH TABLE:

17
K MAP:

Y=(B+C+D)(A’+B’)(B’+C’)

Y=(A’+B’+C+D)(A+B’+C’+D)(A+B’+C’+D’)
=(A’+B+C+D)(A+B’+C’+D)(A+B’+C’+D)

Y=(B+C+D)(A’+B’)(B’+C’)

18
LOGIC DIAGRAM:

19
LOGIC DIAGRAM:

BINARY TO GRAY CODE CONVERTOR

20
K-Map for G3:

G 3 = B3

K-Map for G2:

21
K-Map for G1:

22
K-Map for G0:

TRUTH TABLE:

23
| Binary input | Gray code output |

B3 B2 B1 B0 G3 G2 G1 G0

0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

24
LOGIC DIAGRAM:

GRAY CODE TO BINARY CONVERTOR

25
K-Map for B3:

B3 = G3

26
K-Map for B2:

27
K-Map for B1:

K-Map for B0:

28
TRUTH TABLE:

29
| Gray Code | Binary Code |
G3 G2 G1 G0 B3 B2 B1 B0

0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 1 1 0 1 0
1 1 1 0 1 0 1 1
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 0
1 0 0 0 1 1 1 1

LOGIC DIAGRAM:

BCD TO EXCESS-3 CONVERTOR

30
K-Map for E3:

31
E3 = B3 + B2 (B0 + B1)

K-Map for E2:

32
K-Map for E1:

33
K-Map for E0:

34
TRUTH TABLE:

| BCD input | Excess – 3 output |

35
B3 B2 B1 B0 G3 G2 G1 G0

0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
1 0 1 0 x x x x
1 0 1 1 x x x x
1 1 0 0 x x x x
1 1 0 1 x x x x
1 1 1 0 x x x x
1 1 1 1 x x x x

LOGIC DIAGRAM:

EXCESS-3 TO BCD CONVERTOR

36
K-Map for A:

37
 A = X1 X2 + X3 X4 X1

K-Map for B:

K-Map for C:

38
K-Map for D:

39
TRUTH TABLE:

| Excess – 3 Input | BCD Output |

B3 B2 B1 B0 G3 G2 G1 G0

0 0 1 1 0 0 0 0
0 1 0 0 0 0 0 1
0 1 0 1 0 0 1 0
0 1 1 0 0 0 1 1
0 1 1 1 0 1 0 0
1 0 0 0 0 1 0 1
1 0 0 1 0 1 1 0
1 0 1 0 0 1 1 1
1 0 1 1 1 0 0 0
1 1 0 0 1 0 0 1

40
RESULT:
Thus the design and the implementation of circuit using logic gates for arbitary
function was done the truth table was verified.

41
 PIN DIAGRAM FOR IC 7483:

LOGIC DIAGRAM:

4-BIT BINARY ADDER

EXPT NO : DESIGN OF 4-BIT ADDER AND SUBTRACTOR

42
DATE :

AIM:
To design and implement 4-bit adder and subtractor using IC 7483.

APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. IC IC 7483 1
2. EX-OR GATE IC 7486 1
3. NOT GATE IC 7404 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 40

THEORY:

4 BIT BINARY ADDER:

A binary adder is a digital circuit that produces the arithmetic sum of two binary
numbers. It can be constructed with full adders connected in cascade, with the
output carry from each full adder connected to the input carry of next full adder in
chain. The augends bits of ‘A’ and the addend bits of ‘B’ are designated by subscript
numbers from right to left, with subscript 0 denoting the least significant bits. The
carries are connected in chain through the full adder. The input carry to the adder is
C0 and it ripples through the full adder to the output carry C 4.

4 BIT BINARY SUBTRACTOR:

The circuit for subtracting A-B consists of an adder with inverters, placed between
each data input ‘B’ and the corresponding input of full adder. The input carry C 0 must
be equal to 1 when performing subtraction.

4 BIT BINARY ADDER/SUBTRACTOR:

The addition and subtraction operation can be combined into one circuit with one
common binary adder. The mode input M controls the operation. When M=0, the
circuit is adder circuit. When M=1, it becomes subtractor.

4 BIT BCD ADDER:

Consider the arithmetic addition of two decimal digits in BCD, together with an
input carry from a previous stage. Since each input digit doesnot exceed 9, the
output sum cannot be greater than 19, the 1 in the sum being an input carry. The
output of two decimal digits must be represented in BCD and should appear in the
form listed in the columns.
ABCD adder that adds 2 BCD digits and produce a sum digit in BCD. The 2
decimal digits, together with the input carry, are first added in the top 4 bit adder to
produce the binary sum.

43
LOGIC DIAGRAM:

4-BIT BINARY SUBTRACTOR

44
PROCEDURE:
1. Connections were given as per circuit diagram.
2. Logical inputs were given as per truth table
3. Observe the logical output and verify with the truth tables.

45
TRUTH TABLE:

Input Data A Input Data B Addition Subtraction

A A3 A A1 B4 B B2 B1 C S4 S3 S2 S B D4 D D2 D1
4 2 3 1 3
1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0

1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0

0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0

0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0

1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1

1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1

1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1

LOGIC DIAGRAM:

4-BIT BINARY ADDER / SUBTRACTOR

46
47
LOGIC DIAGRAM:

BCD ADDER

K MAP:

Y = S4 (S3 + S2)

48
49
TRUTH TABLE:

BCD SUM CARRY

S4 S3 S2 S1 C
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1

50
RESULT:
Thus the 4 bit binary adder, 4 bit binary subtractor and BCD adder were
designed using logic gates and their truth table was verified.

51
 PIN DIAGRAM FOR IC 74180:

FUNCTION TABLE:

INPUTS OUTPUTS
Number of High Data PE PO ∑E ∑O
Inputs (I0 – I7)
EVEN 1 0 1 0
ODD 1 0 0 1
EVEN 0 1 0 1
ODD 0 1 1 0
X 1 1 0 0
X 0 0 1 1

52
EXPT.NO : DESIGN AND IMPLEMENTATION OF 8BIT ODD/EVEN
DATE : PARITY CHECKER /GENERATOR USING MSI DEVICES

AIM:
To design and implement 16 bit odd/even parity checker generator using IC
74180.

APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. IC 74180 1
2. IC TRAINER KIT - 1
3. PATCH CORDS - 30

THEORY:
A parity bit is used for detecting errors during transmission of binary
information. A parity bit is an extra bit included with a binary message to make the
number is either even or odd. The message including the parity bit is transmitted and
then checked at the receiver ends for errors. An error is detected if the checked
parity bit doesn’t correspond to the one transmitted. The circuit that generates the
parity bit in the transmitter is called a ‘parity generator’ and the circuit that checks the
parity in the receiver is called a ‘parity checker’.

In even parity, the added parity bit will make the total number is even amount.
In odd parity, the added parity bit will make the total number is odd amount. The
parity checker circuit checks for possible errors in the transmission. If the information
is passed in even parity, then the bits required must have an even number of 1’s. An
error occur during transmission, if the received bits have an odd number of 1’s
indicating that one bit has changed in value during transmission.

PROCEDURE:
1. Connections are given as per circuit diagram.
2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.

53
LOGIC DIAGRAM:

8 BIT ODD / EVEN PARITY CHECKER

TRUTH TABLE:

I7 I6 I5 I4 I3 I2 I1 I0 I7’ I6’ I5’ I4’ I3’ I2’ 11’ I0’ Active ∑E ∑O

0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0
0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 1 0
0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 1 0 1

LOGIC DIAGRAM:

8 BIT ODD / EVEN PARITY GENERATOR

TRUTH TABLE:

I7 I6 I5 I4 I3 I2 I1 I0 I7 I6 I5 I4 I3 I2 I1 I0 Active ∑E ∑O
1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0
1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1
1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0

54
RESULT:

Thus the parity checker and parity generator circuit was designed using
logic gates and their truth table was verified.

55
LOGIC DIAGRAM:

2 BIT MAGNITUDE COMPARATOR

56
EXPT NO : DESIGN AND IMPLEMENTATION OF
DATE : MAGNITUDE COMPARATOR

AIM:
To design and implement
(i) 2 – bit magnitude comparator using basic gates.
(ii) 8 – bit magnitude comparator using IC 7485.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. AND GATE IC 7408 2
2. X-OR GATE IC 7486 1
3. OR GATE IC 7432 1
4. NOT GATE IC 7404 1
5. 4-BIT MAGNITUDE IC 7485 2
COMPARATOR
6. IC TRAINER KIT - 1
7. PATCH CORDS - 30

THEORY:
The comparison of two numbers is an operator that determine one number is greater
than, less than (or) equal to the other number. A magnitude comparator is a
combinational circuit that compares two numbers A and B and determine their
relative magnitude. The outcome of the comparator is specified by three binary
variables that indicate whether A>B, A=B (or) A<B.
A = A 3 A2 A1 A0
B = B 3 B2 B1 B0
The equality of the two numbers and B is displayed in a combinational circuit
designated by the symbol (A=B).This indicates A greater than B, then inspect the
relative magnitude of pairs of significant digits starting from most significant position.
A is 0 and that of B is 0. We have A<B, the sequential comparison can be expanded
as
A>B = A3B31 + X3A2B21 + X3X2A1B11 + X3X2X1A0B01
A<B = A31B3 + X3A21B2 + X3X2A11B1 + X3X2X1A01B0
The same circuit can be used to compare the relative magnitude of two BCD
digits. Where, A = B is expanded as,
A = B = (A3 + B3) (A2 + B2) (A1 + B1) (A0 + B0)
   
x3 x2 x1 x0

PROCEDURE:

1. Connections are given as per circuit diagram.

2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.

57
K MAP:

58
59
TRUTH TABLE:

A1 A0 B1 B0 A>B A=B A<B

0 0 0 0 0 1 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 1 0 0
0 1 0 1 0 1 0
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 0 1 0
1 0 1 1 0 0 1
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 1 0

60
PIN DIAGRAM FOR IC 7485:

61
LOGIC DIAGRAM:

8 BIT MAGNITUDE COMPARATOR

TRUTH TABLE:

A B A>B A=B A<B

0000 0000 0000 0000 0 1 0
0001 0001 0000 0000 1 0 0
0000 0000 0001 0001 0 0 1

62
RESULT:
Thus the magnitude comparator circuit was designed using logic gates and
their truth table was verified.

63
BLOCK DIAGRAM FOR 4:1 MULTIPLEXER:

FUNCTION TABLE:

S1 S0 INPUTS Y
0 0 D0 → D0 S1’ S0’
0 1 D1 → D1 S1’ S0
1 0 D2 → D2 S1 S0’
1 1 D3 → D3 S1 S0

Y = D0 S1’ S0’ + D1 S1’ S0 + D2 S1 S0’ + D3 S1 S0

EXPT NO : DESIGN AND IMPLEMENTATION OF MULTIPLEXER

64
DATE :

AIM:
To design and implement multiplexer and demultiplexer using logic gates.

APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. 3 I/P AND GATE IC 7411 2
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
2. IC TRAINER KIT - 1
3. PATCH CORDS - 32

THEORY:
MULTIPLEXER:
Multiplexer means transmitting a large number of information units over a smaller
number of channels or lines.Adigital multiplexer is a combinational circuit that selects
binary information from one of many input lines and directs it to a single output line.
The selection of a particular input line is controlled by a set of selection lines.
Normally there are 2n input line and n selection lines whose bit combination
determine which input is selected.

PROCEDURE:

1. Connections are given as per circuit diagram.

2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.

65
CIRCUIT DIAGRAM FOR MULTIPLEXER:

Y = D0 S1’ S0’ + D1 S1’ S0 + D2 S1 S0’ + D3 S1 S0

TRUTH TABLE:

S1 S0 Y = OUTPUT
0 0 D0
0 1 D1
1 0 D2
1 1 D3

66
RESULT:

Thus the multiplexer circuit was designed using logic gates and their truth
table was verified.

67
PIN DIAGRAM:

LOGIC DIAGRAM:

SERIAL IN SERIAL OUT:

TRUTH TABLE:

CLK Serial in Serial out

1 1 0
2 0 0
3 0 0
4 1 1
5 X 0
6 X 0
7 X 1

68
EXPT NO : DESIGN AND IMPLEMENTATION OF SHIFT REGISTER
DATE :

AIM:
To design and implement
(i) Serial in serial out
(ii) Serial in parallel out
(iii) Parallel in serial out
(iv) Parallel in parallel out

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. D FLIP FLOP IC 7474 2
2. OR GATE IC 7432 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 35

THEORY:
A register is capable of shifting its binary information in one or both directions
is known as shift register. The logical configuration of shift register consist of a D-Flip
flop cascaded with output of one flip flop connected to input of next flip flop. All flip
flops receive common clock pulses which causes the shift in the output of the flip
flop. The simplest possible shift register is one that uses only flip flop. The output
of a given flip flop is connected to the input of next flip flop of the register. Each clock
pulse shifts the content of register one bit position to right.

PROCEDURE:

1. Connections are given as per circuit diagram.

2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.

LOGIC DIAGRAM:
69
SERIAL IN PARALLEL OUT:

TRUTH TABLE:

OUTPUT
CLK DATA QA QB QC QD
1 1 1 0 0 0
2 0 0 1 0 0
3 0 0 0 1 1
4 1 1 0 0 1

LOGIC DIAGRAM:

PARALLEL IN SERIAL OUT:

TRUTH TABLE:

CLK Q3 Q2 Q1 Q0 O/P
0 1 0 0 1 1
1 0 0 0 0 0
2 0 0 0 0 0
3 0 0 0 0 1

70
71
LOGIC DIAGRAM:

PARALLEL IN PARALLEL OUT:

TRUTH TABLE:

DATA INPUT OUTPUT

CLK DA DB DC DD QA QB QC QD
1 1 0 0 1 1 0 0 1
2 1 0 1 0 1 0 1 0

72
RESULT:

Thus the various shift registers were designed successfully using flip-flops
and their truth tables were verified successfully.

73
LOGIC DIAGRAM FOR UP COUNTER:

TRUTH TABLE:

CLK QA QB QC QN
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1

74
EXPT NO : DESIGN AND IMPLEMENTATION OF 4 BIT SYNCHRONOUS
DATE : UP AND DOWN COUNTER

AIM:
To design and implement 4 bit synchronous up and down counter.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. JK FLIP FLOP IC 7476 2

2. 3 I/P AND GATE IC 7411 1
3. OR GATE IC 7432 1
4. XOR GATE IC 7486 1
5. NOT GATE IC 7404 1
6. IC TRAINER KIT - 1
7. PATCH CORDS - 35

THEORY:
A counter is a register capable of counting number of clock pulse arriving at its clock
input. Counter represents the number of clock pulses arrived. An up/down counter is
one that is capable of progressing in increasing order or decreasing order through a
certain sequence. An up/down counter is also called bidirectional counter. Usually
up/down operation of the counter is controlled by up/down signal. When this signal is
high counter goes through up sequence and when up/down signal is low counter
follows reverse sequence.

PROCEDURE:

1. Connections are given as per circuit diagram.

2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.

75
LOGIC DIAGRAM FOR DOWN COUNTER:

TRUTH TABLE:

CLK QA QB QC QN

0 1 1 1 1
1 1 1 1 0
2 1 1 0 1
3 1 1 0 0
4 1 0 1 1
5 1 0 1 0
6 1 0 0 1
7 1 0 0 0
8 0 1 1 1
9 0 1 1 0
10 0 1 0 1
11 0 1 0 0
12 0 0 1 1
13 0 0 1 0
14 0 0 0 1
15 0 0 0 0

76
RESULT:

Thus Up counter and Down counter was designed successfully using IC

7476 and its truth table was verified successfully.

77
LOGIC DIAGRAM FOR UP COUNTER:

TRUTH TABLE:

CLK QA QB QC QD
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1

78
EXPT NO : DESIGN AND IMPLEMENTATION OF 4 BIT
DATE : ASYNCHRONOUS UP AND DOWN COUNTER

AIM:
To design and implement 4 bit asynchronous up and down counter.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. JK FLIP FLOP IC 7476 2
2. 3 I/P AND GATE IC 7411 1
3. OR GATE IC 7432 1
4. XOR GATE IC 7486 1
5. NOT GATE IC 7404 1
6. IC TRAINER KIT - 1
7. PATCH CORDS - 35

THEORY:
A counter is a register capable of counting number of clock pulse arriving at its clock
input. Counter represents the number of clock pulses arrived. An up/down counter is
one that is capable of progressing in increasing order or decreasing order through a
certain sequence. An up/down counter is also called bidirectional counter. Usually
up/down operation of the counter is controlled by up/down signal. When this signal is
high counter goes through up sequence and when up/down signal is low counter
follows reverse sequence.

PROCEDURE:

1. Connections are given as per circuit diagram.

2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.

79
LOGIC DIAGRAM FOR DOWN COUNTER:

TRUTH TABLE:

CLK QA QB QC QN

0 1 1 1 1
1 1 1 1 0
2 1 1 0 1
3 1 1 0 0
4 1 0 1 1
5 1 0 1 0
6 1 0 0 1
7 1 0 0 0
8 0 1 1 1
9 0 1 1 0
10 0 1 0 1
11 0 1 0 0
12 0 0 1 1
13 0 0 1 0
14 0 0 0 1
15 0 0 0 0

80
RESULT:

Thus Up counter and Down counter was designed successfully using IC

7476 and its truth table was verified successfully.

81
PROGRAM:

HALF ADDER

modulehalf_adder(in_x, in_y, out_sum, out_carry);

input in_x;
input in_y;
outputout_sum;
outputout_carry;
xor (out_sum, in_x, in_y);
and (out_carry, in_x, in_y);
end module;

FULL ADDER

modulefull_adder(x, y, z, sum, carry);

input x;
input y;
output sum;
output carry;
wire a, b, c;
xor (sum, x, y, z);
and (a, x, y);
and (b, y, z);
and (c, z, x);
or (carry, a, b, c);
end module;

82
EXPT NO : SIMULATION OF COMBINATIONAL CIRCUIT USING HDL
DATE :

AIM:
To design and simulate
(i) Adder and Subtractor
(ii) Multiplexer and De-multiplexer

TOOLS REQUIRED:
 XILINX Software
 Modelsim simulator

PROCEDURE:
 Write and draw the Digital logic system.
 Write the Verilog HDL code for above system.
 Open project navigator.
 Select File  New project
 Give the file name and press next.
 Give the entity name and select Verilog HDL module and press next.
 Give the inputs and outputs and specify input or output or in-out and select
next.
 Then give finish and the entity and the architecture details appear by itself.
 Enter the Verilog HDL code in after architecture.
 Check the syntax and simulate the above Verilog HDL code (using ModelSim
or Xilinx) and verify the output waveform as obtained.
 Verify the graph with the truth table.

83
 MULTIPLEXER

module mux_4 to 1 ( y, I1, I2, I3, I4, S0, S1);

input I1, I2, I3, I4, S0, S1;
output y;
wire S1bar, S0bar, a, b, c, d;
not (S1bar, S1);
not (S0bar, S0);
and (a, S1bar, S0bar, I1);
and (b, S1bar, S0, I2);
and (c, S1, S0bar, I3);
and (d, S1, S0, I4);
or (y, a, b, c, d);
end module;

DE-MULTIPLEXER

module mux_4 to 1 ( Y1, Y2, Y3, Y4, I, S0, S1);

input I, S0, S1;
output Y1, Y2, Y3, Y4;
wire S1bar, S0bar;
not (S1bar, S1);
not (S0bar, S0);
and (Y1, S1bar, S0bar, I);
and (Y2, S1bar, S0, I);
and (Y3, S1, S0bar, I);
and (Y4, S1, S0, I);
or (y, a, b, c, d);
end module;

84
RESULT:

Thus the simulation of adders, subtractors, multiplexer and de-multiplexer

using XILINX software and simulated their circuit using modelsim simulator.

85
PROGRAM

RIPPLE COUNTER

module counter (count, load, in, clk, clr, a, c);

input count, load, clk, clr;
input [3:0] in;
output c;
output [3:0] a;
reg [3:0] a;
assign c = count & ~load & (a = = 4’b1111);
always @ (posedge CLK or negedgeclr)
if (~clr) A = 4’b0000;
else if (load) a = in;
else if (count) a = a + 1’b1;
else a = a;
end module;

SISO SHIFT REGISTER

module shift (clk, SE, SI, SO);

input SE, SI;
output SO;
reg [3:0] temp;
always @ (posedgeclk)
begin
if (SE)
begin
temp = temp << 1;
temp[0] = SI;
end;
begin
assign SO = temp [3];
end module;

86
EXPT NO : SIMULATION OF SEQUENTIAL CIRCUITS USING HDL
DATE :

AIM:
To design and simulate
(i) Ripple counter
(ii) Shift registers

TOOLS REQUIRED
 XILINX Software
 Modelsim simulator

PROCEDURE
 Write and draw the Digital logic system.
 Write the Verilog HDL code for above system.
 Open project navigator
 Select File  New project
 Give the file name and press next
 Give the entity name and select Verilog HDL module and press next
 Give the inputs and outputs and specify input or output or in-out and select
next
 Then give finish and the entity and the architecture details appear by itself
 Enter the Verilog HDL code in after architecture.
 Check the syntax and simulate the above Verilog HDL code (using
ModelSim  or Xilinx) and verify the output waveform as obtained.
 Verify the graph with the truth table

87
 SIPO SHIFT REGISTER

module shift (clk, SE, SI, PO);

input SE, SI;
output PO [3:0];
reg [3:0] temp;
always @ (posedgeclk)
begin
if (SE)
begin
temp = {temp [2:0], SI};
end;
begin
assign PO = temp;
end module;

88
RESULT:

Thus the simulation of ripple counter, shift registers using XILINX software
and simulated their circuit using modelsim simulator.

89