ECE414: Digital Systems I

CHAPTER 1 : WEEK 4
Decoder & Encoder

YASMIN – ECE414
 Decoders
• A combinational circuit that converts binary
information from n coded inputs to a
maximum 2n decoded outputs
 n-to- 2n decoder
• n-to-m decoder, m ≤ 2n
• Examples: BCD-to-7-segment decoder,
where n=4 and m=7

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 Decoders (cont.)

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2-to-4 Decoder

F0
X 2-to-4
Y Decoder F1

F2

F3

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2-to-4 Active Low Decoder

F0
X 2-to-4
F1
Y Decoder
F2

F3

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 2-to-4 Decoder IC 74LS139

O0
A1 2-to-4
Decoder O1
A0

O2
E
O3

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 3-to-8 Decoder
• Three inputs, x, y, z, are decoded into
eight outputs, F0 through F7
• Each output Fi represents one of the
minterms of the 3 input variables.
• Fi = 1 when the binary number xyz = i
• Shorthand: Fi = mi
• The output variables are mutually
exclusive; exactly one output has the
value 1 at any time, and the other seven
are 0.
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 3-to-8 Decoder (cont)
x y z F0 F1 F2 F3 F4 F5 F6 F7 F0 = x'y'z'
0 0 0 1 0 0 0 0 0 0 0
F1 = x'y'z
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0 F2 = x'yz'
0 1 1 0 0 0 1 0 0 0 0

data
F3 = x'yz
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0 F4 = xy'z'
1 1 0 0 0 0 0 0 0 1 0 F5 = xy'z
1 1 1 0 0 0 0 0 0 0 1
F6 = xyz'
F0
F1 F7 = xyz
X F2
Y
3-to-8 F3
Z
Decoder F4
F5 x y z
F6 address
F7

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 3-to-8 Decoder IC 74LS138

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 3-to-8 Decoder IC 74LS138 (cont)

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 Implementing Functions Using
Decoders
• Any n-variable logic function, in canonical sum-of-
minterms form can be implemented using a single n-to-
2n decoder to generate the minterms, and an OR gate to
form the sum.
– The output lines of the decoder corresponding to the
minterms of the function are used as inputs to the or gate.
• Any combinational circuit with n inputs and m outputs
can be implemented with an n-to-2n decoder with m OR
gates.
• Suitable when a circuit has many outputs, and each
output function is expressed with few minterms.

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 Implementing a Binary Adder
Using a Decoder (eg Full Adder)
x y z C S
S(X,Y,Z) = Σm(1,2,4,7)
0 0 0 0 0
0 0 1 0 1 C(X,Y,Z) = Σm(3,5,6,7)
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

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 Decoder Expansions
Larger decoders can be constructed using a
number of smaller ones.
-> HIERARCHICAL design!

3-to-8 decoder
using two 2-to-4
decoders

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 3-to-8 decoder using two 2-to-4 decoders

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 7-Segment Display
• It is a numerical display device used to show digital
outputs as decimal digits or alphabetic characters
• It is called 7-segment display because it consists of 7
luminous segments, usually LEDs or liquid crystal.
• 7-segment display are configured as common anode and
common cathode

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COMMON CATHODE(CC) COMMON ANODE(CA)
• The cathodes of all LEDs are • The common anode display has
connected together and brought
out to one or more pin
connections on the display
package.
• The cathode pins are wired
externally to the circuit ground •
• We illuminate the segments by
applying logic HIGHs to individual
anodes.
YASMIN – ECE414
the anodes of the segments
brought out to one or more
common pins. These pins must
be tied to the circuit power
supply (VCC).
The segments illuminate when a
decoder/driver makes their
individual cathodes LOW.
16
 BCD to 7-Segment Decoder/Driver
• Input is a 4-bit BCD code  4
inputs (D, C, B, A).
• Output is a 7-bit code
(a,b,c,d,e,f,g) that allows for the
decimal equivalent to be
displayed.

• EXERCISE: write truth table for active

low BCD to 7-segmant decoder

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 Encoders
• An encoder is a digital circuit that performs
the inverse operation of a decoder. An
encoder has 2n input lines and n output
lines.
• The output lines generate the binary
equivalent of the input line whose value is
1.

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 Encoders (cont.)

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 Encoder Example
• Example: 8-to-3 binary encoder (octal-to-
binary)

A0 = D1 + D3 + D5 + D7
A1 = D2 + D3 + D6 + D7
A2 = D4 + D5 + D6 + D7

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 Encoder Example (cont.)

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 Simple Encoder Design Issues
• There are two ambiguities associated
with the design of a simple encoder:
1. Only one input can be active at any given
time. If two inputs are active simultaneously,
the output produces an undefined
combination (for example, if D3 and D6 are 1
simultaneously, the output of the encoder will
be 111.
2. An output with all 0's can be generated when
all the inputs are 0's,or when D0 is equal to 1.

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 Priority Encoders
• Solves the ambiguities mentioned above.
• Multiple asserted inputs are allowed; one
has priority over all others.
• Separate indication of no asserted inputs.

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 Example: 4-to-2 Priority Encoder
Truth Table

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 4-to-2 Priority Encoder (cont.)
• The operation of the priority encoder is
such that:
• If two or more inputs are equal to 1 at the
same time, the input in the highest-
numbered position will take precedence.
• A valid output indicator, designated by V,
is set to 1 only when one or more inputs
are equal to 1. V = D3 + D2 + D1 + D0 by
inspection.

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 Example: 4-to-2 Priority Encoder
K-Maps

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 Example: 4-to-2 Priority Encoder
Logic Diagram

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 8-to-3 Priority Encoder

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