CS 140 Lecture 12

Standard Combinational Modules

Professor CK Cheng
CSE Dept.
UC San Diego

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 Part III - Standard Combinational
Modules

•Decoder: Decode address

•Encoder: Encode address
•Multiplexer (Mux): Select data by address
•Demultiplexier (DeMux): Direct data by address
•Shifter: Shift bit location
•Adder: Add two binary numbers
•Multiplier: Multiply two binary numbers

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Interconnect: Decoder, Encoder, Mux, DeMux

Data 1 Arbiter
Mux, Memory Bank
P1

Address 1 Data

P2
Demux
n-m
Address 2 Mux
Address

Address k n m 2m
Decoder
Data k
Pk

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 1. Decoder
• Definition
• Logic Diagram
• Application (Universal Set)
• Tree of Decoders

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1. Decoder: Definition
EN (enable)

0 y0
I0 0 1 y1
2
.
I1 1 3
4
5
.
I2 2 6
7 y7
n to 2n decoder
n inputs 2n outputs
n= 3 23 = 8 function:
yi = 1 if En= 1 & (I2, I1, I0 ) = i
yi= 0 otherwise
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1. Decoder: Definition
• N inputs, 2N outputs
• One-hot outputs: only one output HIGH at once

2:4
Decoder
11 Y3
A1 10 Y2
A0 01 Y1
00 Y0

A1 A0 Y3 Y2 Y1 Y0
0 0 0 0 0 1
0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 0 0 0

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Decoder: Logic Diagram
En yi = mi En
y0 = 1 if (I2, I1, I0 ) = (0,0,0) & En = 1
I0’
I1’ y0
I2’

I0’
I1’ y1
I2

.
.

I0
I1 y7 y7 = I2I1I0En
I2

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Decoder Application: universal set {Decoder, OR}
Example: Implement functions f1(a,b,c) = m(1,2,4)
f2(a,b,c) = m(2,3), and f3(a,b,c) = m(0,5,6)
with a 3-input decoder and OR gates.
y1
y2
En y4 f1

0 y0 y2
c I0 1 y1
2
b I1 y3
3
4
. f2
5 .
a I2 6
7 y7
y0
y5
y6 f3

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 Decoders
• OR minterms

2:4
Decoder Minterm
11 AB
A 10 AB
B 01 AB
00 AB

Y = AB + AB
= A  B Y

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Tree of Decoders
Implement a 4-24 decoder with 3-23 decoders.

0 y0
d I0 1
2
y1

c I1 3
4
5
b I2 6
7 y7

0 y8
I0 1 y9
2
I1 3
4
5
I2 6
7 y15

a
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Tree of Decoders
Implement a 6-26 decoder with 3-23 decoders.
En

En
y0
I2, I1, I0 D0
y7
I5, I4, I3 y8
I2, I1, I0 D1
y15
…
…
y56
I2, I1, I0 D7
y63
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 2. Encoder
• Definition
• Logic Diagram
• Priority Encoder

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2. Encoder: Definition
En

I2n-1…I0 yn-1 …y0

A
Encoder Description:
En
At most one Ii = 1.
I0 0
1 0 y0 (yn-1,.., y0 ) = i if Ii = 1 & n = 1
2
1 y1
3
4
(yn-1,.., y0 ) = 0 otherwise.
5 2 y2
I7
6
7
A = 1 if En = 1 and one i s.t. Ii = 1
A = 0 otherwise.
8 inputs A 3 outputs
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Encoder: Logic Diagram
En

y0
I1
I3
I5
I7

En

y1
I2
I3
I6
I7

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Encoder: Logic Diagram
En

y2
I4
I5
I6
I7

En

I0 A
I1
..

I6
I7

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 Priority Encoder: Definition
Description: Input (I2n-1,…, I0), Output (yn-1 ,…,,y0)
(yn-1 ,…,,y0) = i if Ii = 1 & En = 1 & Ik = 0
for all k > i (high bit priority) or
En
for all k< i (low bit priority).

I0
Eo = 1 if En = 1 & Ii = 0 for all i,
0
1 0 y0 Gs = 1 if En = 1 & i s.t. Ii = 1.
E
2
3 1 y1
4
5 2 (Gs is like A, and Eo tells us if
6 y2
7 enable is true or not).
I7

Eo Gs

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Priority Encoder: Implement a 32-input priority
encoder w/ 8 input priority encoders (high bit priority).
En

I31-24 y32, y31, y30

Eo Gs

I25-16 y22, y21, y20

Eo Gs

I15-8 y12, y11, y10

Eo Gs

I7-0 y02, y01, y00

Eo Gs

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