9.2 Electronic Testing Rev

9.
TESTING ELECTRONIC PRODUCTS

AND
STRESS SCREENING
1
9.2. TESTING ELECTRONIC PRODUCTS
2
Testing of electronic products does not cover design verification and has three
objectives:
– Detection of improper product operation
– Isolation of defects → Rework
– Identification of out-of-control manufacturing processes
3
As the complexity of electronic products continues to increase, the cost to test

these products will also increase.
Electronic testing is likely to become an increasingly important component of the

manufacturing process.
4
Product testing must be fully integrated with manufacturing.
Test Philosophy should be decided during design phase, long before

manufacturing starts.
This would prevent many errors altogether.
5
The Order-of-Magnitude Rule
The cost of detecting a fault increases exponentially as the manufacturing

process progresses.
Finding a fault at any stage in the manufacturing process costs 10 times what
it costs to find that same fault at the preceding stage.
6
Test Cost of finding fault
Incoming Inspection (comp. Level) 1$
In-Circuit Testing (board level) 10$
Function or System Test (sys. Level) 100$
Field Repair 1000$
For field repair, 10 times the cost may even be optimistic.
7
8
The test failure is usually observed through an improper response to a stimuli

applied to the unit being tested.
However biggest cost contributor at every test level is troubleshooting time after
test failures.
For troubleshooting, defect or fault isolation is needed .
9
The rework proccess requires specially trained technicians not to give damage to
the product.
10
Levels of Testing :
A variety of product testing levels exist :
1. Component-Level Testing
2. Subassembly-Level Testing
3. Systems-Level Testing
Test complexity and cost increases with test level
11
Component-Level Testing
Component testing is the lowest testing level and is carried out at either
• the component manufacturer’s facilities before they leave the factory
or
• the “Incoming Inspection department” of the (product/system) manufacturer
12
Although some times both are required normally one of these should be enough
to lower down the cost of testing.
A “Certificate of Conformance” (COC) provided by the manufacturer should

normally be enough.
Advantages of component-level testing include
– low test cost
– easy fault isolation.
13
A disadvantage of component testing is :
“the difficulty of accurately determining what the effect of the fault in the
component will be in the final product’s functionality.
And off course,
“Component-Ievel testing fails to consider defects resulting from

• component insertion
and
• soldering”
14
Subassembly- Level (Loaded Board) Testing
This is the next level of test following the component testing.
It is usually of the following types :

– Shorts and opens
– Manufacturing defects analyzer
– In-circuit
– Functional
– Combinational
– "Hot mockup"
– Emulation
15
– Shorts and Opens,

– Manufacturing Defects Analyzer and
– In-Circuit testers
are bed-of-nails (BON) based auotomatic test equipment.
They generally perform analog

measurements using the
operational-amplifier configuration.
16
Positive input is tied to ground and ideally the amplifier is stable only when the
negative input is also at virtual ground and no current flows into the OpAmp.
The value of the unknown resistor is determined as Rm =(Vin/Vout)xRref
17
The bed of nails (BON) method was one of the first approaches to production
level automated testing of printed circuit boards.
In BON method the purpose is to dedect any
 manufacturing flaws (opens and shorts) and
 wrong, missaligned components.
It does not test for functionality of the circuit.
18
Shorts-and-Opens Testers
The simplest test we can perform on a bare or loaded board would be to identify
unwanted shorts and opens
Shorts-and-opens testers gain access to board nodes through a bed-of-nails.
19
In this test, measurement determines the resistance between two nodes, calling
 anything less than some small value a short
and
 any resistance more than some high value an open.
20
Purchase prices for these testers are quite low, generally less than $50,000.
Testing is fast and accurate within the limits of their mission.
Test-program generation is easy and usually means
copying the response of a known good board and comparing it with the board
under test.
21
Therefore, many board manufacturers position these testers
to prescreen
more expensive and more difficult-to-program in-circuit and functional

machines.
22
Manufacturing-Defects Analyzers
Manufacturing-defects analyzers (MDAs) also perform gross resistance

measurements on bare and loaded boards using the opamp arrangement.
The difference is MDAs actually calculate
resistance and impedance values,
and can therefore identify many problems that shorts-and-opens testers cannot
find.
It detects assembly defects such as wrong device, wrong value, wrong

orientation, bad device, wrong alignment and missing devices for components
such as resistors, capacitors, inductors, diodes, transistors and jumpers.
23
Actual measurement results, however, may not conform to designer

specifications, because of surrounding-circuitry effects.
Like shorts-and-opens testers, MDAs can learn test programs from a known-good
board.
24
MDAs are also fairly inexpensive, generally costing less than $100,000 and often
much less.
Tests are fast, and self-Iearn programming minimizes test-programming efforts.
MDAs serve even better as prescreeners for in-circuit, functional, or "hot-

mockup" testing.
25
In-Circuit Testers
In-circuit testers represent the ultimate in bed-of-nails capability.
A fixture containing a bed-of-nails is used to

access individual components on the board
through test lands laid into the copper

interconnect.
26
These sophisticated machines attempt to measure each analog component to its

own specifications
regardless of surrounding circuitry.
Its methods also permit functionally verifying individual digital components.
27
These testers
• apply stimulus to a chosen device, or collection of devices,
• and measure the response from that device or cluster.
Other devices that are electrically connected to the device-under-test are usually
placed into a safe state (a process called “guarding”).
28
The process of grounding strategic points in the circuit during testing is called
guarding, and node Z is known as a guard point.
29
In this way, the tester is able to check the
• presence,
• orientation, and
• bonding
of the device-under-test in place on the board.
30
A bed-of-nails interface made specially for the circuit card to be tested is used
for testing.
The bed-of-nails consists of several spring-loaded contacts which serve as

probes, interfacing with board components and the contact points.
31
32
33
In-circuit-tester manufacturers generally provide
a library of analog device models.
When using program-generation software, tests are picked for actual board
components,
and nominal values and tolerances are assigned depending on the specifications.
34
Digital in-circuit testing follows the same philosophy of
isolating the device under test from others in the circuit.
In this case,
 the tester injects a pattern of signals at a component's inputs that are large
enough to override any preexisting logic state,
 then reads the output pattern.
35
Figure shows an in-circuit configuration for testing a two-input NAND gate.
36
Constructing in-circuit test programs for boards whose designs consist primarily
of known standard devices requires merely
– "knitting" individual device tests together, and
– generating analog and digital guard points where necessary
– assigning tolerances .
37
The actual connections between

test instruments and test nails are
made by program-controllable
relays.
These relays route both the test

instruments and the test nails to a
common set of lines called
Instrument Bus .
38
Many of today's complex boards require a large number of bed-of-nails access

pins, sometimes as many as several thousand.
Tester vendors can minimize the number of actual pin drivers and receivers
through a technique known as multiplexing.
39
With multiplexing, each pin driver switches to address one of several board
nodes.
The number of nodes a pin driver can reach to represents the multiplex ratio.
An 8:1 multiplex ratio, for example, means that one tester pin can contact any of
eight test nails on the board.
The technique reduces in-circuit-tester costs.
40
On the other hand, it introduces a switching step during test execution that can
increase test times.
In addition (and perhaps more important), it significantly complicates the tasks of

test-program generation and fixture construction.
41
When buying an in-circuit tester,
ascertain
• whether the pins are multiplexed,
• how much, and
• how that will affect your day-to-day operation.
42
Revising a fixture to accommodate the frequent changes in board design may

also be very difficult.
43
In-Circuit Testers
– checks for continuity or short circuits that may occure due to solder
bridges or open circuits.
– checks for the wrong component or improper component orientation.
– they also test and locate the components defected due to electrostatic
discharge.
44
Functional Testing :
In functional testing we test the functions of the board, as a whole or in sections
by using
PCB edge connectors and/or bed of nails .
45
A functional board tester simulates

 inputs and
 the output loads
for normal operation of the board,
then determines proper overall functional

operation of the board.
Functional Testers usually include

facilities for diagnosing the location of
causes of incorrect function.
46
Depending on the volume and complexity of the PCB’s, functional testing can be
done with
– dedicated testers which are in-house built test systems or
– with commercially available ATE’s.
– with hot mockup where the PWB is simply connected to a known

good system.
47
The functional ATE is basically a digital phenomenon* and typically requires long
• setup
and
• software generation times.
Programming is difficult and expensive.
Functional testing with ATEs is an expensive technique.
48
Combinational Testing :
This is done by combinational ATEs which provide

• in-circuit
and
• functional
test capability in a single system.
Combinational ATEs usually represent expensive alternatives.
49
Test programmers subdivide a board's circuitry and create the most effective test
on each section.
For example,
– where bed-of-nails access is possible or where there is a lot of analog

circuitry,
an in circuit test is generally the best choice.
– where measurements are time-critical or surface mounting or other

mechanical board features prevent convenient probing,
a functional test is a better choice.
50
Emulation :
A microprocessor or PC is replaced with a test

microprocessor or a PC.
The test pod mimics the board's behavior, stopping at

convenient points to examine registers and other hardware
states.
51
Substitution Testing (Hot Mock Up)
The board or product under test is plugged into a working system that is
complete except for that board or product,
and then is tested for correct outcomes.
As it is relatively cheap and easy to set up, many manufacturers follow in-circuit
test with a hot mockup.
52
COMPUTER BASED TESTING :

Computer based testing can reduce the cost of test equipment and provides :
– storage,
– analyses
and
– transmission
of test data.
53
According to their testing architecture, PC Based Testing can be divided into

three types :
– monolithic,
– rack-and-stack,
– hybrid systems.
54
Monolithic testers
They are
– single and generally large boxes,
– have a computer and a collection of stimulus and measurement
electronics.
– generally unique to that vendor.
Individual instruments may also be connected over a standard bus, such as

IEEE-488.
55
Monolithic testers :
Unit Under Test (UUT)
A functional Tester
56
Advantages of the monolithic approach are
– no unnecessary features, such as front panels, displays,
and
– no excess software
57
Disdvantages of the monolithic approach are
– inflexible. If a customer wants a capability that the tester

does not aIready have, the only option is IEEE-488
and
– Add-on instruments often do not integrate well into

system software.
58
Rack-and-stack systems
They consist of
– a computer,
– a switching matrix, and
– an array of instruments, communicating over a common

I/O bus (IEEE-488).
Instruments from any vendor with appropriate communication bus can be

connected.
59
A Rack-and-stack type ATE
Programmable instruments controlled by a desktop computer via an

IEEE-488 interface bus.
60
Disadvantages are time consuming
– test-program generation
– fixture manufacturing
– preparation of interfaces between tester and board under test.
The IEEE-488 bus has a practical data-speed limit of about 1 MHz
and
permits a maximum of 14 instruments on the bus at a time, only one of which

can be a talker.
61
Hybrid systems
They are a combination of monolithic and rack-and-stack alternatives.
They consist of
– an embedded or stand-alone computer,
– and a collection of printed-circuit-board-based instrument modules

connected through a standard I/O bus (VXI).
This systems allow for board-based instruments from any vendor* to be

connected into a standard chassis.
62
VXI* provides
• I/O speeds of about 10 MHz
• and as many as 255 individual instruments, all of which may be talkers.
VXI-module manufacturers and third parties offer
software-development tools
which allow test engineers to write programs in highlevel languages such as

BASIC and C.
63
Systems-level Testing :
This is a functional test performed when
PCB’s, Cables, Cable trees and mechanical casing are all put together and
the final equipment is produced*.
It checks if the final equipment works to the promised specifications.
ESS can be applied according to the requirements of the customer.
64
A commonly used procedure for systems-level testing is to start with a

system that is initially known to be good.
New PCBs are inserted into the system, one at a time.
As each PWB is inserted, the system is tested.
65
Disadvantages of systems-level testing are
– difficulty of fault isolation.
– cost.
66
Today,
– Digital designs became more and more complex
– available time and board space for test became limited
– Circuit boards changed to multilayer boards
– time to market became very short
Therefore reducing
– test times and
– physical connections (bed of nails) for testing
became a necessity.
Flying probe testing and Boundary Scan testing were developped to ovecome the
difficulties BON methdods.
67
1. Flying Probe Testing
In this method a flying test probe is positioned above the circuit board. and
is automatically moved in the three axis to make contact with the specified test
points. The movement of the probe is controlled by software that uses the physical
layout of the board. Often the number of probes is more than one.
68
Unlike the BON method flying probe method does not require fixtures (BON).
Also the number of test points will not be limited by the bed of nails structure.
However it is slower than the BON and is generally limited to testing protptypes
and small production quantities.
69
Boundary Scan Tests :
Joint Test Automation Group (JTAG) developped in 1994 the
Boundary Scan Testing standards for accessing the pins of a digital device
for controlling or testing purposes without the need for a bed-of -nails .
70
The boundary scan test architecture provides
• “testing internal and external connections of complex digital components
• as well as their interconnections
without using physical test probes.
It adds boundary-scan cells to each pin of the device.
For normal operation, with the help of multiplexers and latches, they are set so
that they have no effect on the circuit.
71
Boundary-scan cells in a device can be programmed to
– capture data from pins
or
– force data onto pins
or
– capture data from core logic signals,
72
When the circuit is set into a test mode, captured data is
– serially shifted out
and
– externally compared to the expected results.
73
This will find common manufacturing defects such as
– solder shorts or opens,
– fractured leads,
– broken circuit traces,
– cold solder joints, and
– ESD-induced IC register failures.
74
Reset
Mode Select
Clock
75
When boundary scan cells are used to test the internal functionality of the device,
the test mode is called INTEST.
A pattern shifted in via the TDI pin is placed on the programmable logic inputs.
The resulting output bits are then shifted out on the TDO pin and checked for
errors.
An incorrect output, indicates a fault in

• the programmed logic,
• I/O cells,
• or boundary scan cells.
76
Example of a bit pattern in the boundary scan Intest for the internal logic.
77
For testing external connections to the device (EXTEST)
we place a known value on the output register of one of the device
and
monitore the input buffer of the next device.
78
monitore
known the input
value buffer of
from the the next
output device
register
of one
device
Example of a bit pattern in the boundary scan Extest for external faults.
79
As an example we assume two boundary-scan compliant devices,
U1 and U2 connected with four nets.
U1 includes four outputs that are driving the four inputs of U2.
We will assume that the circuit

includes two faults:
– A short between Nets 2 and 3,
–an open on Net 4.
80
We assume that
– a short between two nets behaves as a wired-AND
– an open is sensed as logic 1.
The tester is shifting into the U1 boundary-scan register the patterns shown in
Figure and applying these patterns to the inputs of U2.
The inputs values of U2

boundary-scan register are shifted
out and compared to the expected
results.
81
The results (marked in red) on Nets 2, 3, and 4, do not match the expected values
and therefore the tester detects the faults on Nets 2, 3, and 4.
Boundary-scan tests can isolate the faults to specific nets, devices, and pin
numbers.
82
Potential benefits realized from the use of boundary-scan are
– The ability to control and observe logical inputs and outputs without
external physical access to each input and output pin
– The reduction of the number of test points needed on a printed circuit

assembly
– The reduction of the number of nodes/pins needed for a “bed-of-nails

(BON)” fixture.
83
– Increased speed of test, with resulting faster identification and isolation of

defects
– Interoperability between vendors
– shorter test times,
– higher test coverage,
– increased diagnostic capability and
– lower capital equipment cost
84
With Boundary Scan Testing the following tests were possible :
– device testing,
– incoming inspection,
– board test,
– system test,
and
– field maintenance and repair.
85
Boundary scan can also be used to
– test a complete board,
– to verify assembly of daughter boards to mother boards,
– to verify assembly and integrity of backplane systems.
Additionally, the hardware and software associated with boundary scan can
allow CPLDs and FPGAs to be programmed after they have been installed on
a system PCB.
86
Many parts are becoming available with boundary scan built in.
ATE becomes faster if boundary scan is available.
ECAD users can make use of boundary-scan techniques for schematic capture,
board design, and simulation.
ASIC design is also commonly performed incorporating boundary-scan

hardware and support software.
87
QUIZ QUESTION : 1 puan değerinde
Bed of Nails gerektirmeyen 2 test metodunu

yazınız
1………………….
2……………………………
88

9.2 Electronic Testing Rev

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

9.2 Electronic Testing Rev

Uploaded by

Copyright:

Available Formats

9.

TESTING ELECTRONIC PRODUCTS

– Detection of improper product operation

– Isolation of defects → Rework

– Identification of out-of-control manufacturing processes

As the complexity of electronic products continues to increase, the cost to test

Electronic testing is likely to become an increasingly important component of the

Product testing must be fully integrated with manufacturing.

Test Philosophy should be decided during design phase, long before

This would prevent many errors altogether.

The Order-of-Magnitude Rule

The cost of detecting a fault increases exponentially as the manufacturing

For field repair, 10 times the cost may even be optimistic.

The test failure is usually observed through an improper response to a stimuli

For troubleshooting, defect or fault isolation is needed .

A variety of product testing levels exist :

Test complexity and cost increases with test level

• the component manufacturer’s facilities before they leave the factory

• the “Incoming Inspection department” of the (product/system) manufacturer

A “Certificate of Conformance” (COC) provided by the manufacturer should

Advantages of component-level testing include

– low test cost

– easy fault isolation.

A disadvantage of component testing is :

And off course,

“Component-Ievel testing fails to consider defects resulting from

Subassembly- Level (Loaded Board) Testing

This is the next level of test following the component testing.

It is usually of the following types :

– Shorts and Opens,

They generally perform analog

The value of the unknown resistor is determined as Rm =(Vin/Vout)xRref

In BON method the purpose is to dedect any

 manufacturing flaws (opens and shorts) and

 wrong, missaligned components.

It does not test for functionality of the circuit.

Shorts-and-opens testers gain access to board nodes through a bed-of-nails.

 anything less than some small value a short

 any resistance more than some high value an open.

Testing is fast and accurate within the limits of their mission.

Test-program generation is easy and usually means

Therefore, many board manufacturers position these testers

more expensive and more difficult-to-program in-circuit and functional

Manufacturing-defects analyzers (MDAs) also perform gross resistance

The difference is MDAs actually calculate

resistance and impedance values,

It detects assembly defects such as wrong device, wrong value, wrong

Actual measurement results, however, may not conform to designer

Tests are fast, and self-Iearn programming minimizes test-programming efforts.

MDAs serve even better as prescreeners for in-circuit, functional, or "hot-

In-circuit testers represent the ultimate in bed-of-nails capability.

A fixture containing a bed-of-nails is used to

through test lands laid into the copper

These sophisticated machines attempt to measure each analog component to its

regardless of surrounding circuitry.

Its methods also permit functionally verifying individual digital components.

• apply stimulus to a chosen device, or collection of devices,

• and measure the response from that device or cluster.

In this way, the tester is able to check the

of the device-under-test in place on the board.

The bed-of-nails consists of several spring-loaded contacts which serve as

In-circuit-tester manufacturers generally provide

a library of analog device models.