DLCOA important Topics/ Questions

1. Number system conversion numericals

→ These are numericals for converting decimal to binary etc that's why I haven't
added any theory for it
2. Binary codes/ Weighted and non weighted codes with example.

→ In the coding, when numbers, letters or words are represented by a specific group of
symbols, it is said that the number, letter or word is being encoded. The group of symbols
is called as a code. The digital data is represented, stored and transmitted as group of
binary bits. This group is also called as binary code. The binary code is represented by
the number as well as alphanumeric letter.

Advantages of Binary Code

Following is the list of advantages that binary code offers.
● Binary codes are suitable for the computer applications.
● Binary codes are suitable for the digital communications.
● Binary codes make the analysis and designing of digital circuits if we use the binary
codes.
● Since only 0 & 1 are being used, implementation becomes easy.

Classification of binary codes

The codes are broadly categorized into following four categories.
● Weighted Codes
● Non-Weighted Codes
● Binary Coded Decimal Code
● Alphanumeric Codes
● Error Detecting Codes
● Error Correcting Codes

Weighted Codes
Weighted binary codes are those binary codes which obey the positional weight principle.
Each position of the number represents a specific weight. Several systems of the codes
are used to express the decimal digits 0 through 9. In these codes each decimal digit is
represented by a group of four bits.
Non-Weighted Codes
In this type of binary codes, the positional weights are not assigned. The examples of
non-weighted codes are Excess-3 code and Gray code.

Excess-3 code
The Excess-3 code is also called as XS-3 code. It is non-weighted code used to express
decimal numbers. The Excess-3 code words are derived from the 8421 BCD code words
adding (0011)2 or (3)10 to each code word in 8421. The excess-3 codes are obtained as
follows −

Example
3. Write note on Gray code/excess code

→ It is the non-weighted code and it is not arithmetic codes. That means there are no
specific weights assigned to the bit position. It has a very special feature that, only one bit
will change each time the decimal number is incremented as shown in fig. As only one bit
changes at a time, the gray code is called as a unit distance code. The gray code is a
cyclic code. Gray code cannot be used for arithmetic operation.

Application of Gray code

● Gray code is popularly used in the shaft position encoders.
● A shaft position encoder produces a code word which represents the angular
position of the shaft.

4. Binary to gray code conversion /gray to binary

→ Binary to Gray conversion :

1. The Most Significant Bit (MSB) of the gray code is always equal to the MSB of
the given binary code.
2. Other bits of the output gray code can be obtained by XORing binary code bit at
 that index and previous index.

Gray to binary conversion :

1. The Most Significant Bit (MSB) of the binary code is always equal to the MSB
of the given binary number.
2. Other bits of the output binary code can be obtained by checking gray code bit at
that index. If current gray code bit is 0, then copy previous binary code bit, else
copy invert of previous binary code bit.

5. Prove Nand and Nor gates are universal gates

→ NAND Gate
The truth table and symbol of the NAND gate is as shown below. The two inputs are A
and B.

NAND Gate as NOT Gate

NAND Gate as OR Gate

NAND Gate as AND Gate

NOR Gate

The truth table and symbol of the NOR gate is as shown below.
NOR Gate as NOT Gate

NOR Gate as OR Gate

NOR Gate as AND Gate

The above diagrams makes it clear that the combination of NAND and NOR Gates can
result into any of the basic gates (AND, OR and NOT Gates). Hence, NAND and NOR
Gates are called as Universal Gates

6. State Boolean algebra laws.

→ There are six types of Boolean Laws.

Commutative law
Any binary operation which satisfies the following expression is referred to as
commutative operation.

Commutative law states that changing the sequence of the variables does not have any
effect on the output of a logic circuit.

Associative law
This law states that the order in which the logic operations are performed is irrelevant as
their effect is the same.

Distributive law
Distributive law states the following condition.

AND law
These laws use the AND operation. Therefore they are called as AND laws.

OR law
These laws use the OR operation. Therefore they are called as OR laws.

INVERSION law
This law uses the NOT operation. The inversion law states that double inversion of a
variable results in the original variable itself.

7. Differentiate between Computer Organization and computer architecture.

1. Architecture describes what Organization

the computer does. describes how it does
it.

2. Computer Architecture deals Computer

with functional behavior of Organization deals
computer system. with structural
relationship.

3. In above figure, its clear that In above figure, its

it deals with high-level design also clear that it deals
issue. with low-level design
issue.

4. Architecture indicates its Where, Organization

hardware. indicates its
performance.

5. For designing a computer, its For designing a

architecture is fixed first. computer,
organization is
decided after its
 architecture.

6. Computer Architecture is Computer

also called as instruction set Organization is
architecture. frequently called as
micro architecture.

7. Computer Architecture Computer

comprises logical functions Organization consists
such as instruction sets, of physical units like
registers, data types and circuit designs,
addressing modes. peripherals and
adders.

8. Architecture coordinates Computer

between the hardware and Organization handles
software of the system. the segments of the
network in a system.

8. Explain Von Neumann architecture.

Von Neuman architecture design consists of a Control Unit, Arithmetic and Logic
Unit (ALU), Memory Unit, Registers and Inputs/Outputs.
Von Neumann architecture is based on the stored-program computer concept, where
instruction data and program data are stored in the same memory. This design is still
used in most computers produced today.

Central Processing Unit (CPU)

The Central Processing Unit (CPU) is the electronic circuit responsible for executing
the instructions of a computer program.
It is sometimes referred to as the microprocessor or processor.
The CPU contains the ALU, CU and a variety of registers.

Registers
Registers are high speed storage areas in the CPU. All data must be stored in a
register before it can be processed.

MAR Memory Address Register Holds the memory location of data that needs
to be accessed
MDR Memory Data Register Holds data that is being transferred to or from
memory
AC Accumulator Where intermediate arithmetic and logic results are stored
PC Program Counter Contains the address of the next instruction to be executed
CIR Current Instruction Register Contains the current instruction during
processing

Arithmetic and Logic Unit (ALU)

The ALU allows arithmetic (add, subtract etc) and logic (AND, OR, NOT etc)
operations to be carried out.

Control Unit (CU)

The control unit controls the operation of the computer’s ALU, memory and
input/output devices, telling them how to respond to the program instructions it has
just read and interpreted from the memory unit.
The control unit also provides the timing and control signals required by other
computer components.

Buses
Buses are the means by which data is transmitted from one part of a computer to
another, connecting all major internal components to the CPU and memory.
A standard CPU system bus is comprised of a control bus, data bus and address bus.

Address BusCarries the addresses of data (but not the data) between the processor
and memory
Data Bus Carries data between the processor, the memory unit and the
input/output devices
Control Bus Carries control signals/commands from the CPU (and status signals
from other devices) in order to control and coordinate all the activities within the
computer
Memory Unit
The memory unit consists of RAM, sometimes referred to as primary or main
memory. Unlike a hard drive (secondary memory), this memory is fast and also
directly accessible by the CPU.
RAM is split into partitions. Each partition consists of an address and its contents
(both in binary form).
The address will uniquely identify every location in the memory.
Loading data from permanent memory (hard drive), into the faster and directly
accessible temporary memory (RAM), allows the CPU to operate much quicker.

→
9. Explain Booth’s algorithm with example

→ Booth algorithm gives a procedure for multiplying binary integers in signed

2’s complement representation in efficient way, i.e., less number of
additions/subtractions required.

1. Multiplier and multiplicand are placed in the Q and M register respectively.

2. Result for this will be stored in the AC and Q registers.

3. Initially, AC and Q-1 register will be 0.

4. Multiplication of a number is done in a cycle.

5. A 1-bit register Q-1 is placed right of the least significant bit Q0 of the register Q.

6. In each of the cycle, Q0 and Q-1 bits will bechecked.

i. If Q0 and Q-1 are 11 or 00 then the bits of AC, Q and Q-1 are shifted to the right
by 1 bit.

ii. If the value is shown 01 then multiplicand is added to AC. After addition, AC, Q0,
Q- 1

register are shifted to the right by 1 bit.

iii. If the value is shown 10 then multiplicand is subtracted from AC. After
subtraction AC,

Q0, Q-1 register is shifted to the right by 1 bit.

EXAMPLE
10. Draw flowchart of Booth’s algorithm for two’s complement
multiplication.
11. Explain restoring method of binary division with algorithm.(both
signed and unsigned)

→
12. Explain Non-Restoring division with algorithm
→
13. Explain IEEE-754 floating point representation format for 32 and 64 bit.

→ IEEE Standard 754 floating point is the most common representation today for
real numbers on computers, including Intel-based PC’s, Macs, and most Unix
platforms.
There are several ways to represent floating point number but IEEE 754 is the
most efficient in most cases. IEEE 754 has 3 basic components:
1. The Sign of Mantissa –
This is as simple as the name. 0 represents a positive number while 1
represents a negative number.
2. The Biased exponent –
The exponent field needs to represent both positive and negative
exponents. A bias is added to the actual exponent in order to get the
stored exponent.
3. The Normalised Mantissa –
The mantissa is part of a number in scientific notation or a floating-point
number, consisting of its significant digits. Here we have only 2 digits, i.e.
O and 1. So a normalised mantissa is one with only one 1 to the left of
the decimal.

IEEE 754 numbers are divided into two based on the above three
components: single precision and double precision.
5r
14. Numericals on floating point representation

→
15.Design a full adder using half adders.

→ The full adder can be thought of as two half adders connected together, with the
first half adder passing its carry to the second half adder as shown.

Sum = A ⊕ B ⊕ C
Carry = AB + (A ⊕ B). C
= AB + ( A. B + A. B). C
= AB + A. BC + A. B. C
= B (A + A. C) + A. B. C
= B [(A+ A) (A + C)] + A. B. C
= AB + AC + A. B. C
 = AB + C (B + A. B)
= AB + C [(B + A) (B + B)]
= AB + BC + AC

16. Difference between full adder and half adder

→
Half Adder Full Adder
S.No.

Half Adder is a
Full adder is a combinational logical
combinational logic
circuit that performs an addition
circuit which adds two
1 operation on three one-bit binary
1-bit digits. The half adder
numbers. The full adder produces a sum
produces a sum of the two
of the three inputs and carry value.
inputs.

2 Previous carry is not used. Previous carry is used.

In Half adder there are In full adder there are three input bits (A,
3
two input bits ( A, B). B, C-in).
 Logical Expression for
Logical Expression for Full adder is :
half adder is :
4
S=a⊕b⊕Cin; Cout=(a*b)+(Cin*(a⊕b)).
S=a⊕b ; C=a*b.

It consists of one EX-OR It consists of two EX-OR, two AND gate

5
gate and one AND gate. and one OR gate.

It is used in Calculators,
It is used in Multiple bit addition, digital
6 computers, digital
processors etc.
measuring devices etc.

17. What is demultiplexer? Why is it called a data distributor?

→ A demultiplexer is a device that takes a single input line and routes it to one of
several digital output lines.
• A demultiplexer of 2n outputs has n select lines, which are used to select which
output line to send the input.
• We have 1x2,1x4,….Demultiplexers.
A 1-to-4 demultiplexer has a single input (D), two selection lines (S1 and S0) and
four outputs (Y0 to Y3). The input data goes to any one of the four outputs at a given
time for a particular combination of select lines.
This demultiplexer is also called as a 2-to-4 demultiplexer which means that two
select lines and 4 output lines. The block diagram of 1:4 DEMUX is shown below.
The truth table of this type of demultiplexer is given below. From the truth table it is
clear that, when S1=0 and S0= 0, the data input is connected to output Y0 and when
S1= 0 and s0=1, then the data input is connected to output Y1.
Similarly, other outputs are connected to the input for other two combinations of
select lines.
The truth table of this type of demultiplexer is given below. From the truth table it is
clear that, when S1=0 and S0= 0, the data input is connected to output Y0 and when
S1= 0 and s0=1, then the data input is connected to output Y1.
Similarly, other outputs are connected to the input for other two combinations of
select lines.

From the table, the output logic can be expressed as min terms and are given below.
Where D is the input data, Y0 to Y3 are output lines and S0 & S1 are select lines.
From the above Boolean expressions, a 1-to-4 demultiplexer can be implemented by
using four 3-input AND gates and two NOT gates as shown in figure below. The two
selection lines enable the particular gate at a time.
So depends on the combination of select inputs, input data is passed through the
selected gate to the associated output.

Demultiplexers are also called data distributors, since they transmit the same data
which is received at the input to different destinations.
18. Differentiate between multiplexer and demultiplexer
→
Demultiplexer
Multiplexer

Multiplexer processes the digital Demultiplexer receives digital information

information from various sources from a single source and converts it into
into a single source. several sources

It is known as Data Selector It is known as Data Distributor

Multiplexer is a digital switch Demultiplexer is a digital circuit

It follows combinational logic type It also follows combinational logic type

It has n data input It has single data input

It has a single data output It has n data outputs

It works on many to one operational It works on one to many operational

principle principle

In time division Multiplexing,

In time division Multiplexing,
multiplexer is used at the transmitter
demultiplexer is used at the receiver end
end
19. Differentiate between encoder and decoder.

→
ENCODER DECODER
S.No.

Encoder circuit basically converts Decoder performs reverse operation

1 the applied information signal into and recovers the original information
a coded digital bit stream. signal from the coded bits.

In case of an encoder, the applied Decoder accepts coded binary data as

2
signal is the active signal input. its input.

The number of inputs accepted by The number of input accepted by

3
an encoder is 2n. decoder is only n inputs.

The output lines for an encoder is

4 The output lines of an decoder is 2n.
n.

The decoder generates an active

The encoder generates coded data
5 output signal in response to the coded
bits as its output.
data bits.

6 The operation performed is simple. The operation performed is complex.

7
The encoder circuit is installed at The decoder circuit is installed at the
 the transmitting end. receiving side.

OR gate is the basic logic element AND gate along with NOT gate is the
8
used in it. basic logic element used in it.

It is used in E-mail, video encoders It is used in Microprocessors, memory

9
etc. chips etc.

20. Differentiate between Combinational and sequential circuits

→ Combinational circuits are defined as the time independent circuits which do

not depend upon previous inputs to generate any output are termed as combinational
circuits. Sequential circuits are those which are dependent on clock cycles and
depend on present as well as past inputs to generate any output.
Combinational Circuit –
1. In this output depends only upon present input.
2. Speed is fast.
3. It is designed to be easy.
4. There is no feedback between input and output.
5. This is time independent.
6. Elementary building blocks: Logic gates
7. Used for arithmetic as well as boolean operations.
8. Combinational circuits don’t have capability to store any state.
9. As combinational circuits don’t have a clock, they don’t require triggering.
10.These circuits do not have any memory element.
11.It is easy to use and handle.
Examples – Encoder, Decoder, Multiplexer, Demultiplexer
Sequential Circuit –
1. In this output depends upon present as well as past input.
2. Speed is slow.
3. It is designed tough as compared to combinational circuits.
 4.
There exists a feedback path between input and output.
5.
This is time dependent.
6.
Elementary building blocks: Flip-flops
7.
Mainly used for storing data.
8.
Sequential circuits have capability to store any state or to retain earlier
state.
9. As sequential circuits are clock dependent they need triggering.
10.These circuits have memory elements.
11.It is not easy to use and handle.
Examples – Flip-flops, Counters

21. Flip flop is a sequential circuit. Explain

→ A Sequential circuit combinational logic circuit that consists of an input
variable (X), logic gates (Computational circuit), and output variable (Z).
Combinational circuit produces an output based on input variable only, but a
Sequential circuit produces an output based on current input and previous input
variables. That means sequential circuits include memory elements which are
capable of storing binary information. That binary information defines the state of
the sequential circuit at that time. A latch capable of storing one bit of information.
Flip-flop is a basic digital memory circuit, which stores one bit of information.Flip
flops are the fundamental blocks of most sequential circuits. It is also known as a
bistable multivibrator or a binary or one-bit memory. Flip-flops are used as memory
elements in sequential circuits.
The output is obtained in a sequential circuit from combinational circuit or flip-flop
or both. The state of flip-flop changes at the active state of clock pulses and remains
unaffected when the clock pulse is not active. In particular, clocked flip flops serve
as memory elements in synchronous sequential Circuits and unclocked flip-flops
(i.e., latches) serve as memory elements in asynchronous sequential circuits.
22. What is latch ?Difference between latch and flip flop?

→ Latch is an electronic device, which changes its output immediately based on

the applied input. It is used to store either 1 or 0 at any specified time. It consists of
two inputs namely “SET” and RESET and two outputs, which are complement to
each other.
A latch has a feedback path, so information can be retained by the device. Therefore
latches can be memory devices, and can store one bit of data for as long as the device
is powered.
• Latches are used to "latch onto" information and hold in place.
• Latches are very similar to flip-flops, but are not synchronous devices, and do not
operate on clock edges as flip-flops do. Latch is a level sensitive device.
 Flip-flop Latch
SNO

Flip-flop is a bistable device i.e., it has Latch is also a bistable device

1 two stable states that are represented whose states are also
as 0 and 1. represented as 0 and 1.

It checks the inputs but changes the It checks the inputs

output only at times defined by the continuously and responds to
2
clock signal or any other control the changes in inputs
signal. immediately.

3 It is an edge triggered device. It is a level triggered device.

Gates like NOR, NOT, AND, NAND These are also made up of
4
are building blocks of flip flops. gates.
 They are classified into asynchronous There is no such classification
5
or synchronous flip flops. in latches.

These can be used for the

It forms the building blocks of many designing of sequential
6
sequential circuits like counters. circuits but are not generally
preferred.

latch doesn’t have a clock

7 a, Flip-flop always have a clock signal
signal

8 Flip-flop can be build from Latches Latches can’t build from gates

9 ex:D Flip-flop, JK Flip-flop ex:SR Latch, D Latch

23. Draw the logic diagram of JK flip flop. Describe its working.( Same type of
question for SR, D and T flip flops can be asked)

→
JK Flip Flop :

• The JK flip-flop is basically an SR flip flop with feedback

which enables only one of its two input terminals, either

SET or RESET to be active at any one time thereby

eliminating the invalid condition seen previously in the SR

flip flop circuit.

• Also when both the J and the K inputs are at logic level ―1

at the same time, and the clock input is pulsed ―HIGH,

the circuit will ―toggle from its SET state to a RESET

state, or vice-versa.

• This results in the JK flip flop acting more like a T-type

toggle flip-flop when both terminals are―HIGH.

• Both the S and the R inputs of the previous SR bistable have now been

replaced by two inputs called the J and K inputs. Then this equates to: J = S

and K = R.

• The two 2-input NAND gates of the gated SR bistable have now been

replaced by two3-input NAND gates with the third input of each gate

connected to the outputs at Q and Q'.

• This cross coupling of the SR flip-flop allows the previously invalid condition

of S = 1and R = 1state to be used to produce a toggle action as the two

inputs are now interlocked.

• If the circuit is now SET the J input is inhibited by the 0

status of Q through the lower NAND gate. If the circuit is

RESET the K input is inhibited by the 0 status of Q

through the upper NAND gate.

• When both inputs J and K are equal to logic 1, the JK flip

flop toggles.

Truth table:
→SR CLOCKED Flip-Flop

• The most basic sequential logic circuit possible.

• This simple flip-flop is basically a one-bit memory bistable device that has two
inputs, one which will ―SET the device (meaning the output = 1), and is labelled S
and one which will ―RESET the device (meaning the output = 0), labelled R.

• The reset input resets the flip-flop back to its original state with an output Q.

• Abasic NAND gate SR flip-flop circuit provides feedback from both of its outputs
back to its opposing inputs and is commonly used in memory circuits to store a
single data bit.

• Then the SR flip-flop actually has inputs, Set, Reset and its current output Q.
→ D Flip Flop

• The D-type flip-flop is a modified Set-Reset flip-flop with the addition of an

inverter to prevent the S and R inputs from being at the same logic level

• One of the main disadvantages of the basic SR NAND Gate Bistable circuit is that
the indeterminate input condition is forbidden when both S and R inputs are 1. This
state will force both outputs to be at logic 1

• But in order to prevent this from happening an inverter can be connected between
the―SET‖ and the ―RESET‖ inputs to produce another type of flip flop circuit
known as a Data Latch, Delay flip flop, D-type Bistable, D-type Flip Flop or just
simply a D Flip Flop as it is more generally called the D Flip Flop

• D flip flop is by far the most important of the clocked flip-flops as it ensures that
inputs S and R are never equal to one at the same time.

• The D-type flip flops are constructed from a gated SR flip-flop with an inverter
added between the S and the R inputs to allow for a single D (data) input.

• Then this single data input, labelled ―D‖ and is used in place of the ―Set‖ signal,
and the inverter is used to generate the complementary ―Reset‖ input.

• The D'Flip flop will store and output whatever logic level is applied to its data
terminal so long as the clock input is HIGH. Once the clock input goes LOW the
―set and ―reset inputs of the flip-flop are both held at logic level ―1 so it will not
change state and store whatever data was present on its output before the clock
transition occurred. In other words the output is ―latched at either logic ―0 or logic
―1.

D Qn Qn+1

0 X 0 RESET

1 X 1 SET
→ Toggle Flip Flop / T Flip Flop

Toggle flip flop is basically a JK flip flop with J and K terminals permanently
connected together. It has only input denoted by T .

We can construct a T flip flop by any of the following methods. Connecting the
output

feedback to the input, in SR flip flop. Connecting the XOR of T input and Q
PREVIOUS

output to the Data input, in D flip flop. Hard – wiring the J and K inputs together and
connecting it to T input, in JK flip – flop.

• If the output Qn = 0, then the upper NAND is in enable state and

the lower NAND gate is in disable condition. This allows the trigger to

pass the inputs to make the flip – flop in SET state i.e. Qn+1 = 1.

• If the output Qn = 1, then the upper NAND is in disable state and

the lower NAND gate is in enable condition. This allows the trigger to

pass the inputs to make the flip – flop in RESET state i.e. Qn+1 =0.
24. Describe register organization within the CPU

→ Registers are the smaller and the fastest accessible memory units in the central
processing unit (CPU).

• According to memory hierarchy, the

registers in the processor, function

a level above the main

memory and cache memory. The

registers used by the central unit are

also called as processor registers.

• A register can hold the instruction,

address location, or operands.

Sometimes, the instruction has register

as a part of itself.
Register Organization is the arrangement of the registers in the processor.

The processor designers decide the organization of the registers in a processor.

Different processors may have different register organization.

The registers in the processor performs two roles:

• User Visible Registers :

• Minimize main memory

references by optimizing use of

registers

• Control and Status Registers:

• Used by control unit to control

the operation of processor

General Purpose Registers

• General-purpose registers can be assigned to a

variety of functions by the programmer

• Sometimes their use within the instruction set is

orthogonal to the operation

• That is, any general-purpose register can contain

the operand for any opcode.

• This provides true general-purpose register use

• Often, however, there are restrictions. For

example, there may be dedicated registers for

floating-point and stack operations

• In some cases, general-purpose registers can

be used for addressing functions (e.g., register

indirect, indexed)

• In other cases, there is a partial or clean

separation between data registers and

address registers.

Data Registers

• Data registers may be used only to hold data

and cannot be employed in the calculation of

an operand address.

Address Registers
• Address registers may themselves be somewhat

general purpose, or they may be devoted to a

particular addressing mode

• Examples include the following:

▪ Segment pointers: In a machine with segmented

addressing, a segment register holds the address of the

base of the segment

▪ Index registers: These are used for indexed addressing

▪ Stack pointer: If there is user-visible stack addressing,

then typically there is a dedicated register that points

to the top of the stack

Control and Status Registers

Control Registers : Four registers essential for

instruction execution are

• Program counter (PC): Contains the address of an

instruction to be fetched

• Instruction register (IR): Contains the instruction

most recently fetched

• Memory address register (MAR): Contains the

address of a location in memory

• Memory buffer register (MBR): Contains a word

of data to be written to memory or the word

most recently read

Status Register

• A register or set of registers that contain status

information is called Program Status Word (PSW)

• PSW contains condition codes and other status

information

• PSW contains :

– Sign: Sign bit of last operation

– Zero: Set when result is 0.

– Carry: Set when a carry/borrow is generated /taken.

– Overflow: When arithmetic overflow occurs

– Interrupt Enable/Disable: Used to enable / disable

interrupts

– Supervisor: Indicates whether in supervisor/user

mode.

25. Explain in detail different types of addressing modes

→ • The different modes are:

– Immediate

– Register

– Direct

– Indirect

– Register Indirect

– Displacement/ Indexed

– Base relative plus index addressing mode

Immediate Addressing

• Operand is part of instruction or operand is

specified in instruction itself.

• e.g. ADD 5

– Add 5 to contents of accumulator

– 5 is operand

• Adv:

– No memory reference to fetch data

– Fast

• Disadv:

– Instruction size big

Register Addressing

• Address field refers to a register

• EA = R

• Adv:

– Only a small address field is needed in the

instruction

– Less access time

• Disadv:

– Limited number of registers

– Limited address space

Direct Addressing

• Address field contains memory location of

operand

• e.g. ADD A

– Look in memory at address A for operand

• Adv:
– Single memory reference to access data

– No additional calculations to work out effective

address

• Disadv: Limited address space

Indirect Addressing
• Memory location pointed to by address field

contains the address of (pointer to) the

operand.

• Effective Address EA = (A)

– Look in A, find address (A) and look there for

operand

• e.g. ADD (A)

– Add contents of location pointed to by contents of

A to accumulator

• Adv:

– Large address space

• Disadv: Multiple memory accesses to find

operand and hence slower

Various types of indirect addressing modes

• Register Indirect Addressing

• Register relative

• Base indexed

• Base relative plus indexed/ displacement

Register Indirect Addressing

• Address in register i.e. EA = (R)

• Operand is in memory location pointed to by

contents of register R

• MOV CL, [BX];

• Square bracket means BX is memory location.

• BX register is used to store memory location.

• BX will act as a pointer to location in memory that

contains data which is moved to register CL.

Direct vs Indirect

• When you need data from single location or

just one value is required----Use Direct

Addressing mode.

• If there is requirement to access data from

series of location--------- Use Indirect

Addressing mode.

Displacement/Indexed Addressing

• Combines direct and register indirect

addressing

• EA = A + (R)

• Address field hold two values

– A = base value

– R = register that holds displacement

Displacement Addressing

• Register Relative Addressing

• Base + Indexed Addressing

• Base relative + Indexed Addressing

Register Relative Addressing

• Relative address means an address specified

by indicating its distance from

another address, called the base address.

For example, a relative address might be

B+15, B being the base address and 15 the

distance (called the offset).

• Address = Register + displacement

• i.e. get operand by using memory location stored

in register as a reference point

• The referenced register (R) may contain

– A main memory address

• Exploits locality of reference

• If memory references are near to the instruction

being executed, this saves address bits in the

instruction
Example: MOV CL, [ BX+ 05H]

CL ←[ BX+ 05H]

• If BX = 2000H, then to access data from location

2005 we just add 05 constant to it.

• No need to waste time in changing contents of

register BX to get required location

Base Indexed Addressing

• Address field contains main memory address

= base

• Register contains displacement

Indexed reg = displacement

• Address = BASE + INDEXED REGISTER

• Good for accessing arrays

Example:

• MOV CL, [BX+ SI]

CL← [BX+ SI]

• BX consists of 2000 memory location and we

want data from 2000 TO 2020 location then

to 2040.

• Initialize SI TO 20 . We can increment or

decrement indexed register.

Base relative plus indexed

• Address = base + index + displacement

• Example:

MOV CL, [BX + SI + 05H];

CL← [BX + SI + 05H]

• Within the group of addresses if you want to

access any particular value.

Implied addressing mode

• The operand is not specified in the instruction

at all, it is implied in the instruction by the

processor.

• Without actually giving operand, processor

can manage the operation, its called implied

addressing mode.

• Example:

STC; (SET THE CARRY FLAG) CF=1

CLC; (COMPLEMENT CARRY FLAG ) CF=0

26. Explain different instruction formats and instruction cycle.

→ Instruction Formats
• Defines the layout of bits in an instruction
• Includes opcode & operands
• Usually more than one instruction format in an instruction set
Zero-address instruction

• 0 (zero) addresses
– All addresses implicit
– Example: stack
• push a
• push b
• pop c
One-address instruction

• 1 address
– Implicit second address : Usually a register
(accumulator)
– E.g. Add C // C=C+A(accumulator)
Two-address instruction
• 2 addresses
– To store result
–a=a+b
– Reduces length of instruction
– Requires temporary storage to hold some results
Three-address instruction

• 3 addresses
– Operand 1, Operand 2, Result
– a = b + c;
– Not common
– Needs very long words to hold everything
• The Instruction Cycle
– Basic View
– Intermediate View
– Exceptions
– Operation - the operation code does
not denote a valid operation
– Execution - the instruction logic fails,
typically due to the input data
• divide by zero
• integer addition/subtraction
overflow
• floating point underflow/overflow
27. Explain role of different registers.

→ Types of Registers are as Followings

MAR stand for Memory Address Register

This register holds the memory addresses of data and instructions. This register is used to access
data and instructions from memory during the execution phase of an instruction. Suppose CPU
wants to store some data in the memory or to read the data from the memory. It places the
address of the-required memory location in the MAR.
Program Counter

The program counter (PC), commonly called the instruction pointer (IP) in Intel x86
microprocessors, and sometimes called the instruction address register, or just part of the
instruction sequencer in some computers, is a processor register
It is a 16 bit special function register in the 8085 microprocessor. It keeps track of the the next
memory address of the instruction that is to be executed once the execution of the current
instruction is completed. In other words, it holds the address of the memory location of the
next instruction when the current instruction is executed by the microprocessor.
Accumulator Register

This Register is used for storing the Results those are produced by the System. When the CPU
will generate Some Results after the Processing then all the Results will be Stored into the AC
Register.
Memory Data Register (MDR)

MDR is the register of a computer’s control unit that contains the data to be stored in the
computer storage (e.g. RAM), or the data after a fetch from the computer storage. It acts like
a buffer and holds anything that is copied from the memory ready for the processor to use it.
MDR holds the information before it goes to the decoder.
MDR which contains the data to be written into or readout of the addressed location. For example,
to retrieve the contents of cell 123, we would load the value 123 (in binary, of course) into the
MAR and perform a fetch operation. When the operation is done, a copy of the contents of cell
123 would be in the MDR. To store the value 98 into cell 4, we load a 4 into the MAR and a 98
into the MDR and perform a store. When the operation is completed the contents of cell 4 will
have been set to 98, by discarding whatever was there previously.
The MDR is a two-way register. When data is fetched from memory and placed into the MDR, it
is written to in one direction. When there is a write instruction, the data to be written is placed into
the MDR from another CPU register, which then puts the data into memory.
The Memory Data Register is half of a minimal interface between a micro program and computer
storage, the other half is a memory address register.
Index Register

A hardware element which holds a number that can be added to (or, in some cases, subtracted
from) the address portion of a computer instruction to form an effective address. Also known as
base register. An index register in a computer’s CPU is a processor register used for modifying
operand addresses during the run of a program.
Memory Buffer Register

MBR stands for Memory Buffer Register. This register holds the contents of data or instruction
read from, or written in memory. It means that this register is used to store data/instruction coming
from the memory or going to the memory.
Data Register

A register used in microcomputers to temporarily store data being transmitted to or from a

peripheral device.

28. Explain different techniques for design of control unit

→Control unit generates timing and control signals for the operations of the computer. The control
unit communicates with ALU and main memory. It also controls the transmission between
processor, memory and the various peripherals. It also instructs the ALU which operation has to be
performed on data.

Control unit can be designed by two methods which are given below:

Hardwired Control Unit

It is implemented with the help of gates, flip flops, decoders etc. in the hardware. The inputs to the
control unit are the instruction register, flags, timing signals etc. This organization can be very
complicated if we have to make the control unit large.
If the design has to be modified or changed, all the combinational circuits have to be modified
which is a very difficult task.
Microprogrammed Control Unit
It is implemented by using a programming approach. A sequence of micro operations is carried out
by executing a program consisting of micro-instructions. In this organization any modifications or
changes can be done by updating the microprogram in the control memory by the programmer.

29. Describe a hardwired control unit using a diagram.

→ Hardwired: The control signals are generated as an output of a set of basic

logic gates, the input of which derives from the binary bits in the Instruction
Register.
The control hardware can be viewed as a state machine that changes from one state to
another in every clock cycle, depending on the contents of the instruction register, the
condition codes and the external inputs. The outputs of the state machine are the control
signals. The sequence of the operation carried out by this machine is determined by the
wiring of the logic elements and hence named as “hardwired”.
● Fixed logic circuits that correspond directly to the Boolean expressions are used
to generate the control signals.
● Hardwired control is faster than micro-programmed control.
● A controller that uses this approach can operate at high speed.
● RISC architecture is based on hardwired control unit
30. What is a micro program?

● The process of code generation for the control memory is called

microprogramming.
● A sequence of microinstructions constitutes a micro program.
● Since alterations of the microprogram are not needed once the control unit is
in operation, the control memory can be a read-only memory (ROM).
● ROM words are made permanent during the hardware production of the unit.
● The use of a micro program involves placing all control variables in words of
ROM for use by the control unit through successive read operations.
● The content of the word in ROM at a given address specifies a
microinstruction.

Alternate :

● A program is a set of instructions.

● An instruction requires a set of Micro-operations.
● Micro operations are performed by control signals.
● Instead of generating these control signals by hardware, we use
microinstructions.
● This means every instruction requires a set of micro-instructions.
● This is called its micro-program.

31. Explain micro programmed control unit using diagram

→ Micro Programmed control unit :

• It Produces control signals by software, using micro-instructions..

• A program is a set of instructions.

• An instruction requires a set of Micro-operations.

• Micro operations are performed by control signals.

• control signals are generated using micro-instructions.

• This is called its microprogram

• Microprograms are stored in control memory

• The control memory is present inside the processor.

• Consider an instruction that is fetched from the main memory into the instruction
register.

• The processor uses its unique opcode to identify the address of the first micro
instruction.

• That address is loaded into CMAR( Control memory address register)

• This address is decoded to identify the corresponding micro instruction from the
control memory.

• There is a big improvement over Wilke’s design, to reduce the size of micro
instructions.

• Most micro instructions will only have a control field.

• The control field indicates control signals to be generated.

• Most micro instructions will not have an address field

• Instead the microprogram counter(micro PC) will simply get incremented after
every micro instruction.

• This is as long as the micro program is executed sequentially.

• If there is a branch microinstruction only then there will be an address field.

• If the branch is unconditional, the branch address will be directly loaded into
CMAR.

• For conditional branches, the branch condition will check the appropriate flag.

• This is done using a Mux which has all flag inputs.

• If the condition is true, then the Mux will inform CMAR to load the

branch address.

• If the condition is false CMAR will simply get incremented.

• The control memory is usually implemented using FLASH ROM as it is

writable yet non volatile.

32. Explain Wilke’s design in detail

→ • Micro programs for all instructions are stored in a small memory called
control memory.

• The control memory is present inside the processor.

• Consider an instruction that is fetched from the main memory into the instruction
register.

• The processor uses its unique opcode to identify the address of the first micro
instruction.

• That address is loaded into CMAR( Control Memory Address Register)

• CMAR passes the address to the decoder.

• The decoder identifies the corresponding micro instruction from the control
memory.

• A micro instruction has two fields: a control field and an address field.

• Control field: indicates the control signals to be generated.

• Address field: indicates the address of the next micro instruction.

• This address is further loaded into CMAR to fetch the next micro instruction.

• For a conditional micro instruction, there are two address fields.

• This is because the address of the next micro instruction depends on the condition.

• The condition(true or false) is decided by the appropriate control flag.

• The control memory is usually implemented using FLASH ROM as it is writable

yet non volatile.
Advantages :

• The biggest advantage is flexibility.

• Any change in the control unit can be performed by simply changing the micro
instruction.

• This makes modifications and upgradation of the control unit very easy.

• Moreover, software can be easily debugged as compared to large hardwired control

units.

Disadvantages :

• Control memory has to be present inside the processor, increasing its size.

• This also increases the cost of the processor.

• The address field in every micro-instruction adds more space to the control
memory. This can be avoided by proper micro-instruction sequencing.
33. Explain microinstruction sequencing.

→ Microinstruction Sequencing is the method of determining the flow of the

microprogram. There are two main techniques:

1) Dual Address Field

2) Single Address Field

1) Dual Address Field

• In this approach micro instructions are not executed in sequential manner

• The IR gives the address of the first micro-instruction

• Thereafter each micro instruction gives the address of the next micro instruction.

• If it is a conditional micro instruction, it will contain two address fields.

• One for the condition to be true and other for false.

• Hence it is called dual address field.

The multiplexer will decide the address to be loaded into the control

memory address register(CMAR) based on the status flags.

2) Single Address Field

• The micro instructions are executed in sequential manner

• The IR gives the address of the first micro –instruction into CMAR.

• Thereafter the address is simply incremented

• Hence every microinstruction need not carry the address of the next instruction.

• This is true so long micro program is executed in sequential manner

• For unconditional branches, the micro instruction contains the branch address. This
address will be loaded into CMAR.

• For a conditional branch, micro instruction contains the branch address for true
condition.

• If the condition is false the current address in CMAR, will be simply incremented.
• This means even in the worst case the micro instruction will carry only one
address. Hence it is called Single address field.

• The multiplexer will decide the address to be loaded into the control memory
address register(CMAR) based on the status flags

34. What are applications of microprogramming?

→ Micro programming has various advantages like flexibility, easy

upgradation. As a result it plays a major role in following applications:

• Development of control unit: Modern processors have very large and

complex instruction set. Microprogramming is suited for making

control unit of such processors as they are far less complex and can

be easily modified.

• User tailoring of the control unit: CU is developed using software, it

can be easily reprogrammed. Custom made modification of CU.

• Improving the OS: can be used to implement complex and secure

functions of the OS. It provides high degree of protection from

malicious virus attacks.

• High level language support: it provides support directly from the

processor level, language becomes easy to compile and faster to

execute.

• Micro diagnostics: debugging an error is far more easy, monitoring,

detection, isolation and repair of any kind of system error is easier.

• Development of specialized processors: many applications require

special purpose processors like DSP for communication, GPU for

image processing, have complex instruction set and require constant

upgradation, so Microprogrammed is an ideal choice.

35. Write a short note on memory hierarchy.

→ • The purpose of any memory device is to store programs and data.

• Seven types of memory devices are used in the computer forming a Memory
Hierarchy.

• Each plays a specific role, contributing to the speed, cost effectiveness, portability
etc.

The memory in a computer can be divided into five hierarchies based on the speed as
well as use. The processor can move from one level to another based on its
requirements. The five hierarchies in the memory are registers, cache, main memory,
magnetic discs, and magnetic tapes. The first three hierarchies are volatile memories
which mean when there is no power, and then automatically they lose their stored
data. Whereas the last two hierarchies are not volatile which means they store the
data permanently.

1) Registers

Usually, the register is a static RAM or SRAM in the processor of the computer

which is used for holding the data word which is typically 64 or 128 bits. The

program counter register is the most important as well as found in all the processors.

Most of the processors use a status word register as well as an accumulator. A status

word register is used for decision making, and the accumulator is used to store the

data like mathematical operation. Usually, computers like complex instruction set

computers have so many registers for accepting main memory, and RISC- reduced

instruction set computers have more registers.

2) Cache Memory

Cache memory can also be found in the processor, however rarely it may be another
IC (integrated circuit) which is separated into levels. The cache holds the chunk of

data which is frequently used from main memory. When the processor has a single

core then it will have two (or) more cache levels rarely. Present multi-core processors

will be having three, 2-levels for each one core, and one level is shared.

3) Main Memory

The main memory in the computer is nothing but the memory unit in the CPU that

communicates directly. It is the main storage unit of the computer. This memory is

fast as well as large memory used for storing the data throughout the operations of

the computer. This memory is made up of RAM as well as ROM.

4) Magnetic Disks

The magnetic disks in the computer are circular plates fabricated of plastic otherwise

metal by magnetized material. Frequently, two faces of the disk are utilized as well

as many disks may be stacked on one spindle by read or write heads obtainable on

every plane. All the disks in the computer turn jointly at high speed. The tracks in the

computer are nothing but bits which are stored within the magnetized plane in spots

next to concentric circles. These are usually separated into sections which are named

as sectors.
 5) Magnetic Tape

This tape is a normal magnetic recording which is designed with a slender

magnetizable covering on an extended, plastic film of the thin strip. This is mainly

used to back up huge data. Whenever the computer requires access to a strip, first it

will mount to access the data. Once the data is allowed, then it will be unmounted.

The access time of memory will be slower within the magnetic strip as well as it will

take a few minutes for accessing a strip.

36. Describe the characteristics of memory.

→ Memory Characteristics :

1) Location Based on its physical location, memory is classified into three types.

• On-Chip: This memory is present inside the CPU. E.g.:: Internal Registers and L1
Cache.

• Internal: This memory is present on the motherboard. E.g.:: RAM.

• External: This memory is connected to the motherboard. E.g.:: Hard disk.

2) Storage Capacity This indicates the amount of data stored in the memory.
Obviously it should be as large as possible.

It is represented as N x M. Here, N = Number of memory locations (no of words) M

= Number of bits per memory location (word size)

E.g.:: (4K x 8) means there are 4K locations of 8-bits each.

3) Transfer Modes : Data can be transferred from memory in two different ways.

• Word Transfer: Here, if CPU needs some data, it will transfer only that amount of
data. E.g.:: Data accessed from L1 Cache.

• Block Transfer: Here, if the CPU needs some data, it will transfer an entire block
containing that data. This makes further access to remaining data of this block much
faster. This is based on the Principle of Spatial Locality. A processor is most likely to
access data near the current location being accessed. E.g.:: On a cache miss, the
processor goes to main memory and copies a block containing that data.

4) Access Modes : Memories can allow data to be accessed in two different ways.

• Serial Access: Here locations are accessed one by one in a sequential manner. The
access time depends on how far the target location is, from the current location.
Farther the location, more will be its access time. E.g.:: Magnetic tapes.

• Random Access: Here all locations can be directly accessed in any random order.
This means all locations have the same access time irrespective of their address.
E.g.:: Most modern memories like RAM.

5) Physical Properties : There are various Physical attributes to memory.

• Writable: Contents of the memory can be altered. E.g.:: RAM

• Non-Writable: Contents of the memory cannot be altered. E.g.:: ROM

• Volatile: Contents of the memory are lost when power is switched off. E.g.:: RAM

• Non-Volatile: Contents of the memory are retained when power is switched off.
E.g.:: ROM. Most secondary memories like hard disk are writable as well as
non-volatile.

6) Access Time : It is the time taken between placing the request and completing the
data transfer. It should be as little as possible. It is also known as latency.

7) Reliability : It is the time for which the memory is expected to hold the data
without any errors. It is measured as MTTF: Mean Time To Failure. It should be
as high as possible.

8) Cost : This indicates the cost of storing data in the memory. It is expressed as
Cost/bit. It must be as low as possible.

9) Average Cost : It is the total cost per bit, for the entire memory storage. Consider
a system having two memories M1 (RAM) & M2 (ROM) If C1 is the cost of
memory M1, of size S1 & C2 is the cost of memory M2 of size S2

• Then the average cost of the memory is be calculated as: C(AVG) = (C1 S1 + C2
S2)/ (S1 + S2)

• Small sizes of expensive memory and large size of cheaper memory lowers the
average cost.

10) Hit Ratio (H) : Consider two memories M1 and M2. M1 is closer to the
processor

E.g.:: RAM, than M2 E.g.:: Hard disk. If the desired data is found in M1, then it is
called a Hit, else it is a Miss. Let N1 be the number of Hits and N2 the number of
Misses. The Hit Ratio H is defined as the number of hits divided by total attempts.

H = (N1) / (N1 + N2) It is expressed as a percentage. H can never be 100%. In most

computers it is maintained around 98%.

• No single memory can satisfy all the characteristics, hence we need a hierarchy of
memories.

• Cache memories are the fastest but also the most costly.

• Hard disk is writable as well as non volatile and is also very inexpensive, but is
much slower.

• CD/DVD etc. are needed for portability.

• ROM is non volatile, and is used for storing BIOS.

• DRAM is writable, faster than hard disk and cheaper than SRAM hence forms most
part of Main Memory.

37. What is the necessity of cache memory?

→
38. Explain cache mapping techniques.

→
39. Numericals based on cache mapping techniques.

→
40. Explain cache coherence problem

→
41. Explain memory interleaving techniques.

→
42. What is associative memory?

→
43. Explain six stage instruction pipeline with diagram

→
44. What is instruction pipelining?

→
45. Explain different types of pipeline hazards.

→
46. What is branch prediction and delayed branch?

→
47. Write short on performance measures such as cpu time, throughput.

→ • A useful basic metric is clock frequency in GHz • 1 GHz = 1000

MHz
• Clock cycle time = 1/clock frequency
• 1 GHz gives clock cycle time of 1 nanosecond
 CPU Time = CPU cycles for a program/Clock
frequency

• A program may have N instructions in its object

code, but that is not Instruction Count(IC).
• Dynamic count of the instructions actually executed is
important.
• A program may skip certain instructions due to
specified conditions and may repeat others due
to loops.

• Clocks required per

Instruction (CPI) is
given by CPI =
CPU clock cycles
for a program/IC
Hence, CPU time = IC . CPI . Cycle time
= IC . CPI/Clock frequency

CPU time = Cycle Time .Σ CPI k. IC k

48. Write a note on Flynn’s classification.

→ There are different ways to classify parallel computers. One of the

more widely used classifications, in use since 1966, is called Flynn's

Taxonomy.

• Flynn's taxonomy distinguishes multi-processor computer

architectures according to how they can be classified along the two

independent dimensions of Instruction and Data. Each of these

dimensions can have only one of two possible states: Single or

Multiple.

Flynn Matrix

• The matrix below defines the 4 possible classifications according to

Flynn

Single Instruction, Single Data (SISD)

• A serial (non-parallel)
computer

• Single instruction: only

one instruction stream is

being acted on by the

CPU during any one
clock cycle

• Single data: only one

data stream is being used as

input during any one clock cycle

• Deterministic execution

• This is the oldest and until recently, the most

prevalent form of computer

• Examples: most PCs, single CPU workstations and

mainframes

Single Instruction, Multiple Data (SIMD)

• A type of parallel computer

• Single instruction: All processing units execute the same instruction at any given
clock

cycle

• Multiple data: Each processing unit can operate on a different data element

• Examples:
• Processor Arrays: Connection Machine CM-2, Maspar MP-1, MP-2

• Vector Pipelines: IBM 9000, Cray C90, Fujitsu VP, NEC SX-2, Hitachi S820

Multiple Instruction, Single Data (MISD)

• A single data stream is fed into multiple processing units.

• Each processing unit operates on the data independently via

independent instruction streams.

• Some uses might be:

➢multiple cryptography algorithms attempting to crack a single coded

message.

Multiple Instruction, Multiple Data (MIMD)

• Currently, the most common type of parallel computer. Most modern

computers fall into this category.

• Multiple Instruction: every processor may be executing a different

instruction stream

• Multiple Data: every processor may be working with a different data

stream

• Execution can be synchronous or asynchronous, deterministic or non-

deterministic

• Examples: most current supercomputers, networked parallel computer

"grids" and multi-processor SMP computers - including some types of

PCs.
49. What is bus arbitration? Explain.

→ same answer as 50.

50. Explain bus contention.

→ In a Loosely coupled system all processors can use their local bus
simultaneously.

• But the system bus can be used by only one module at a

time. Hence there is contest for the system bus.
• This is called bus contention. It is resolved by various
arbitration schemes having different priority
methods.
 A) Daisy Chain Method

The material in this presentation belongs to St. Francis Institute of Technology and is solely for educational purposes. Distribution and modifications of the content is prohibited.

• All bus masters use the same line for Bus Request.
• If the Bus Busy line is inactive, the Bus Controller gives the Bus
Grant signal.
• Bus Grant signal is propagated serially through all masters
starting from nearest one.
 • The bus master, which requires the system bus, stops this
signal, activates the Bus Busy line and takes control of the
system bus.

B) Polling Method

Here also all bus masters use the same line for Bus Request.
• Here the controller generates binary address for the master. Eg: To connect 8 bus
masters we need 3 address lines.

• In response to a Bus Request, the controller "polls" the bus masters by sending a sequence of
bus master addresses on the address lines.Eg: 000,010,100,011 etc
• The selected master activates the Bus Busy line and takes control of the bus.

C) Independent Request Method

• Here, all bus masters have their individual Bus Request and Bus Grant lines.
• The controller thus knows which master has requested, so bus is granted
to that master.
• Priorities of the masters are predefined so on simultaneous Bus Requests, the
bus is granted based on the priority, provided the Bus Busy line is not active.
• The Controller consists of encoder and decoder logic for the
priorities.
51. Explain multi core architecture.

→
52. Numericals on Amdahl’s law