Faculty Aswan Faculty of Engineering Unit Code EE

Department Electrical Engineering Dep. Unit Title Experiment (6)

Year/ Year 3 Lecturer

Semester Semester 2 ( 2016-2017) Assistant

Course Digital Design Test(Digital) LAB Computers and Systems

Engineering Lab
Student name:……………………….. Evaluator
Eng: ………………………..
Date :………/………/……….
Mark: ……………../10

Experiment (6)

Registers and Counters

Main Goals
1. Providing introduction to registers.
2. Familiarizing students to different registers’ types and functions.
3. Recognizing the different pins of the 74195 register and check its
operation.
4. Building bidirectional shift register with 74195 register.
5. Provides an introduction to how to design counters.
6. Prepare student for construct and test various ripple counter circuits.
7. Recognizing the different pins of the 74161 counter and check its
operation.
8. Using 74161 counter to design special counters.

Theoretical background
Shift Registers
A register capable of shifting its binary information in one or both directions is
called a shift register. The logical configuration of a shift register consists of a chain
of flip-flops in cascade, with the output of one flip-flop connected to the input of the
next flip-flop. All flip-flops receive common clock pulses, which activate the shift
from one stage to the next.
The simplest possible shift register is one that uses only flip-flops, as shown in
Figure 1. The output of a given flip-flop is connected to the D input of the flip-flop at
its right. Each clock pulse shifts the contents of the register one bit position to the
right. The serial input determines what goes into the leftmost flip-flop during the shift.
The serial output is taken from the output of the rightmost flip-flop. Sometimes it is
necessary to control the shift so that it occurs only with certain pulses, but not with
others. This can be done by inhibiting the clock from the input of the register to
prevent it from shifting. The shift operation can he controlled through the D inputs of
the flip-flops rather than through the clock input. If however the shift register of
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Figure 1 is used, the shift can be controlled by connecting the clock through an AND
gate with an input that controls the shift.

Figure 1. 4-bit shift register

Serial Transfer
A digital system is said to operate in a serial mode when information is transferred
and manipulated one bit at a time. Information is transferred one bit at a time by
shifting the bits out of the source register into the destination register. This in contrast
to parallel transfer where all the bits of the register are transferred at the same
time.The serial transfer of information from register A to register B is done with shift
registers, as shown in the block diagram of of Figure 2. The serial output (SO) of
register A is connected to the serial input (SI) of register B. To prevent the loss of
information stored in the source register, the information in register A is made to
circulate by connecting the serial output to its serial input. The initial content of
register B is shifted out through its serial output and is lost unless it is transferred to a
third shift register. The shift control input determines when and how many times the
registers are shifted. This is done with an AND gate that allows clock pulses to pass
into the CLK terminals only when the shift control is active.

Figure 2. Block diagram

Figure 3. Timing diagram

Suppose the shift registers have four bits each. The control unit that supervises
the transfer must be designed in such a way that it enables the shift registers,
through the shift control signal, for a fixed time of four clock pulses. This is
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shown in the timing diagram of figure 3. The shift control signal is
synchronized with the clock and changes value just after the negative edge of
the clock. The next four clock pulses find. the shift control signal in the active
state so that the output of the AND gate connected to the CLK inputs produces
four pulses, T1, T2, T3, and T4. Each rising edge of the pulse causes a shift in
both registers. The fourth pulse changes the shift control to 0 and the shift
registers are disabled. Assume that the binary content of A before the shift is
1011 and that of B is 0010. The serial transfer from A to B occurs in four steps,
as shown in Table 1. With the first pulse T1, the right most bit of A is shifted
into the leftmost bit of B and is also circulated into the leftmost position of A.
At the same time, all bits of A and B are shifted one position to the right. The
previous serial output from B in the rightmost position is lost and its value
changes from 0 to 1. The three pulses perform identical operations, shifting the
bits of A into B, one at a time. After the fourth shift, the shift control goes to 0
and both registers A and B have the value 1011. Thus the content of A is
transferred into B, while the content of A remains unchanged. The difference
between serial and parallel modes of operation should he apparent from this
example. In the parallel mode, information is available from all bits of a
register and all bits can be transferred simultaneously during one clock pulse.
In the serial mode, the registers have a single serial input and a single serial
output. The information is transferred one bit at a time while the registers are
shifted in the same direction

Timing Pulse Shift Register A Shift Register B

Initial value 1 0 1 1 0 0 1 0
After T1 1 1 0 1 1 0 0 1
After T2 1 1 1 0 1 1 0 0
After T3 0 1 1 1 0 1 1 0
After T4 1 0 1 1 1 0 1 1
Table 1. Serial-transfer from register A to register B

Counters:

A sequential circuit that goes through a prescribed sequence of states upon

the application of input pulses is called a counter. The input pulses, called
count pulses, may be clock pulses or they may originate from an external
source and may occur at prescribed intervals of time or at random. In a counter,
the sequence of states may follow a binary count or any other sequence of
states.
A counter that follows the binary sequence is called a binary counter. An n-
bit binary counter consists of n flip-flops and can count in binary from 0 to 2n-
1. As an example, the state diagram of 3-bit counter is shown in Figure 4. As
seen from the binary states indicated inside the circles, the flip-flop output
repeat the binary count sequence with a return to 000 after 111. The directed
lines between circles are not marked with input-output values as in other state
diagrams. Remember that state transitions in clocked sequential circuits occur
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during a clock pulse; the flip-flops remain in their present states if no pulse
occurs. For this reason, the clock-pulse variable CP does not appear explicitly
as an input variable in a state diagrams or state table. From this point of view,
the state diagram of a counter does not have to show input-output values along
the directed lines. The only input to the circuit is the count pulse, and the output
is directly specified by the present states of the flip-flop. The next state of a
counter depends entirely on its present state, and the state transition occurs
every time the pulse occurs. Table 2 is the excitation table for 3-bit binary
counter.

Figure 2. State diagram of 3-bit binary counter

Table 2. Excitation table for 3-bit binary counter

Present state Next state Filp-flop Inputs
A2 A1 A0 A2 A1 A0 TA2 TA1 TA0
0 0 0 0 0 1 0 0 1
0 0 1 0 1 0 0 1 1
0 1 0 0 1 1 0 0 1
0 1 1 1 0 0 1 1 1
1 0 0 1 0 1 0 0 1
1 0 1 1 1 0 0 1 1
1 1 0 1 1 1 0 0 1
1 1 1 0 0 0 1 1 1

Using the map method to calculate the TA2, TA1 and TA0 we have:

TA2 = A0A1
TA1 = A0
TA0 = 1

Including these functions with three flip-flops, we obtain the logic diagram of
the counter, as shown in Figure 5.

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 Figure 5. Logic for 3-bit binary counter

Ripple counter
MSI counters come in two categories: ripple counters and synchronous
counters. In a ripple counter, the flip-flop output transition serves as a source
for triggering other flip-flops. In other words, the cp inputs of all flip-flops
(expect the first) are triggered not by the incoming pulses, but rather by the
transition that occurs in other flip-flops, as shown in Figure 6.

Figure 6. 4-bit binary ripple counter.

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Decimal Counter:

A decimal counter follows a sequence of ten state and return to 0 after the
count of 9. Such a counter must have at least four flip-flops to represented each
decimal digit, since a decimal digit is represented by a binary code with at least
four bits. The sequence of states in a decimal counter is dictated by the binary
code used to represent a decimal digit. If this is similar to a binary counter,
except that the state after 1001 (code for decimal digit 9) is 0000 (code for
decimal digit 0). See Figure and Figure 8.

Figure 7. State diagram of a decimal BCD counter

The following are the conditions for each flip-flop state transition:
1. Q1 is complemented on the negative edge of every pulse.
2. Q2 is complemented if Q8 = 0 and Q1 goes from 1 to 0. Q2 is
cleared if Q8 = 1 and Q1 goes from 1 to 0.
3. Q4 is complemented when Q2 goes from 1 to 0.
4. Q8 is complemented when Q2Q4 = 11 and Q1 goes from 1 to 0. Q8
is cleared if either Q4 or Q2 is 0 and Q1 goes from 1 to 0.

To verify that these conditions result in the sequence required by a BCD

counter, it is necessary to verify that flip-flop transition indeed follow a
sequence of states as specified by the timing diagram of Figure .

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 Figure 8. BCD ripple counter

Figure 9. Timing diagram of the decimal counter

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Binary counter with parallel load:

Counters employed in digital systems quite often require a parallel-load

capability for transferring an initial binary number prior to the count operation.
Error! Reference source not found. shows the IC 74161 of a counter that has
a parallel-load capability. The input load control when equal to 1 disables the
count sequence and causes a transfer of data from inputs I1 through I4 into flip-
flops A1 through A4, respectively. If the load input is 0 and the count input
control is 1, the circuit operates as counter. The clock pulses then cause the
state of the flip-flops to change according to the binary count sequence. If both
control inputs are 0, clock pulses do not change the state of the counter.

Figure 10: 74161 IC counter with parallel load

Equipments (photos):

1. 74195 IC register.
2. JK flip-flop 7476 ICs,
3. AND gate 7408 IC,
4. NAND gate 7400 IC,
5. 4-bit synchronous binary counter with parallel load asynchronous clear
74161 IC,
6. LEDs
7. Multimeter
8. Breadboard
9. Connecting wires
10. DC voltage supplies (5-Volts, 0-Volts).

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 IC type 7476 dual JK master-slave flip-flop

Exercise 6-1
Ex 6-1-1
IC Shift Register

IC type 74195 is a 4-bit shift register with parallel load and asynchronous clear.
The pin assignment to the inputs and outputs is shown in Figure 11.The single
control line labeled SH/LD (shift/load determines the synchronous operation of
the register. When SH/LD = 0, the control input is in the load mode and the
four data inputs are transferred into the four internal flip-flops, QA through
QD. When SH/LD = 1, the control input is in the shift mode and the
information in the register is shifted right from QA toward QD. The serial input
into QA during the shift is determined from the J and K inputs. The two inputs
behave like the J and the complement of K of a JK flip-flop. When both J and
K are equal to 0, flip-flop QA is cleared to 0 after the shift. If both inputs are
equal to 1, QA is set to 1 after the shift. The other two conditions for the J and
K inputs provide a complement or no change in the output of flip-flop QA
after the shift. The function table in table 8 for the 74195 shows the mode of
operation of the register. When the clear input goes to 0, the four flip-flops
clear to 0 asynchronously, that is, without the need of a clock. Synchronous
operations are affected by a positive transition of the clock. To load the input
data, the SH/LD must be equal to 0 and a positive clock-pulse transition must
occur. To shift right, the SH/LD must he equal to 1. The J and K inputs must
be connected together to form the serial input.
Perform an experiment that will verify the operation of the 74195 IC. Show
that it performs all the operations listed in the function table. Include in your
function table the two conditions for J K = 01 and 10.

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 Figure 11: IC Type 74195 Shift Register with Parallel Load

Ex 6-1-2
Bidirectional Shift Register without parallel load
The 74195 IC can shift only right from QA toward QD. It is possible to
convert the register to a bidirectional shift register by using the load mode to
obtain a shift left operation (from QD toward QA). This is accomplished by
connecting the output of each flip-flop to the input of the flip-flop on its left
and using the load mode of the SH/LD input as a shift-left control. Input D
becomes the serial input for the shift-left operation.
Connect the 74195 as a bidirectional shift register (without parallel load).
By connecting the serial input for shift right to a toggle switch. Construct the
shift left by connecting the serial input D to a toggle switch. Clear the register
and then check its operation by shifting right a single 1 from the serial input
switch and record each state in table 3. Shift left three more times and insert 0’s
from the serial input switch and record each state in table 4.

Timing Pulse SERIAL QA QB QC QD

INPUT
Initial value 1 0 0 0 0
After T1
After T2
After T3
After T4
Table 3

Timing Pulse SERIAL QA QB QC QD

INPUT
Initial value 0 1 1 1 1 (after t4 in table4)
After T1
After T2
After T3
Table 4

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Exercise 6-2
Ex 6-2-1
Ripple counter
 Construct a 4-bit binary ripple counter using 7476 ICs.
 Connect all asynchronous clear and preset inputs to logic-1.
 Connect the count pulse input to a pulser and check the counter for
proper operation.
Ex 6-2-2
Decimal Counter
 Design a ripple BCD counter that counts from 0000 to 1001. Use two
7476 and one 7408 IC as shown in Figure 8.
 Test the counter for the proper sequence.
Ex 6-2-3
Binary Counter with Parallel Load

a. IC type 74161 is a 4-bit synchronous binary counter with parallel load

and asynchronous clear. The internal logic is similar to the circuit shown
in Figure . The pin assignment to the inputs and outputs is shown in Figure
5. When the load signal is enabled, the four data inputs are transferred
into four internal flip-flops, QA through QD, with QD being the most
significant bit.There are two count-enable inputs called P and T. both
must be equal to 1 for the counter to operate. The load input in the 74161
is enabled when equal to 0. The two count inputs have don't care
conditions and may be equal to either 1 or 0. The internal flip-flops
trigger on the positive transition of the clock pulse.

b. Perform an experiment to verify the operation of the 74161 IC.

c. Show how the 74161 IC together with a 2-input NAND gate can be made
to operate as a synchronous BCD counter that counts from 0000 to 1001.
By using two ways, first by using NAND gate to detect the count of
1010, which then clears the counter asynchronous through the clear
input. Second use the NAND gate to detect the count of 1001, which then
causes all 0's to be loaded into the counter.

d. Connect each of the four circuits shown in Figure 13 to achieve a mod-6

counter.

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 Figure 12. IC type 74161 binary counter with parallel load

Table 5

Function Table
Clear Clock Load Count Function
0 X X X Clear outputs to 0
1  0 X Load input data
1  1 1 Count to next binary value
1  1 0 No change in output

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 Figure 13; Four ways to achieve a mod-6 counter using a counter with parallel load

Report
1- Construct a bidirectional shift register with parallel load using the 74195
register and the 74157 multiplexer. The circuit should be able to perform
the following operations: ( indicate your answer with a characteristic table
such as the following table.

a) Asynchronous clear,
b) Shift right,
c) Shift left,
d) Parallel load,

Clear Shift/Load Clock j K Serial Select Function

Input
Asynchronous
clear
Shift from QA
toward QD,
Shift from QD
toward QA,
Parallel Load

2- Design a digital clock (24 mode) by using six binary counters: 2 for seconds,
2 for minutes and 2 for hours

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