Lectures 1 7

Lecture Notes on Basic Electronics
for Students in Computer Science
John Kar-kin Zao and Wen-Hsiao Peng

Department of Computer Science, National Chiao-Tung Univeristy
1001 Ta-Hsueh Rd., 30010 HsinChu, Taiwan
August 2006
Contents
1 Preamble 1
1.1 Goal of This Course . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Content of This Course . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.3 Relationship with Other Disciplines . . . . . . . . . . . . . . . . . . . . . . 1
I System and Circuit Analysis 2
2 Signals and Systems 3

2.1 Basic Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2 Types of Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.3 Axiomatic Properties of Systems . . . . . . . . . . . . . . . . . . . . . . . 5
2.4 Time-Domain Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.4.1 Impulse Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.4.2 Step Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4.3 Sinusoidal Response . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4.4 Initial Value/Driving Free/Natural Response . . . . . . . . . . . . . 12
2.4.5 Transient Response . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.4.6 Steady-State Response . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.5 Frequency-Domain Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5.1 Phasor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5.2 Spectrum and Fourier Transform . . . . . . . . . . . . . . . . . . . 13
2.5.3 System Transfer Function Hs (ω) . . . . . . . . . . . . . . . . . . . . 14
2.5.4 Time Domain versus Frequency Domain . . . . . . . . . . . . . . . 16
3 Electrical Circuits 17
3.1 Basic Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2 Circuit Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3 Circuit Laws . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4 Network Theorems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
ii
CONTENTS
3.4.1 Equivalent Circuits of One-Port Networks . . . . . . . . . . . . . . 23

3.4.2 Equivalent Circuits of Two-Port Networks . . . . . . . . . . . . . . 25
3.5 Laplace Transforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.6 Equivalent Circuits in Laplace Domain . . . . . . . . . . . . . . . . . . . . 31
3.7 System Transfer Function in Time and Laplace Domains . . . . . . . . . . 33
3.8 Bode Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
II Devices — Diode, BJT, MOSFETs 49
4 Semiconductor 50
4.1 Intrinsic Silicon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.2 Doped Silicon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5 Diode 55
5.1 Physical Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5.1.1 The pn Junction Under Open Circuit . . . . . . . . . . . . . . . . . 55
5.1.2 The pn Junction Under Reverse-Bias . . . . . . . . . . . . . . . . . 57
5.1.3 The pn Junction in the Breakdown Region . . . . . . . . . . . . . . 59
5.1.4 The pn Junction Under Forward Bias Conditions . . . . . . . . . . 59
5.2 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
5.2.1 Forward Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
5.2.2 Reverse Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.2.3 Breakdown Region . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5.3 Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5.3.1 Large Signal Model . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5.3.2 Small Signal Model . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5.3.3 Circuit Analysis with Diodes . . . . . . . . . . . . . . . . . . . . . . 70
5.4 Special Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.4.1 Zener diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.4.2 Switching Controlled Rectifier (SCR) . . . . . . . . . . . . . . . . . 72
5.4.3 LED/Varactors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
5.5 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
5.5.1 Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
5.5.2 Rectifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
5.5.3 Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.5.4 Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.5.5 Digital Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
iii
CONTENTS
6 MOS Field-Effect Transistors (MOSFETs) 81

6.1 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.1.1 Physical Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.2 Characteristics of NMOS Transistor . . . . . . . . . . . . . . . . . . . . . . 83
6.2.1 Cut-off Region (vGS < Vt ) . . . . . . . . . . . . . . . . . . . . . . . 83
6.2.2 Triode (vGS > Vt , 0 < vDS < vGS − Vt ) . . . . . . . . . . . . . . . . 83
6.2.3 Saturation (vGS > Vt , vDS > vGS − Vt ) . . . . . . . . . . . . . . . . 87
6.3 Characteristics of PMOS Transistor . . . . . . . . . . . . . . . . . . . . . . 90
6.3.1 Body Effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6.3.2 Internal Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . 92
6.3.3 Temperature Effect . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
6.3.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
7 Bipolar Junction Transistor (BJT) 95

7.1 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
7.1.1 NPN Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
7.1.2 PNP Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
7.2 Operations of NPN Transistor . . . . . . . . . . . . . . . . . . . . . . . . . 98
7.2.1 Active Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
7.2.2 Reverse Active Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 102
7.2.3 Ebers-Moll (EM) Model . . . . . . . . . . . . . . . . . . . . . . . . 103
7.2.4 Saturation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
7.3 Operations of PNP Transistor . . . . . . . . . . . . . . . . . . . . . . . . . 106
7.3.1 Active Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
7.3.2 Reverse Active Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 108
7.3.3 Saturation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
7.3.4 Summary of the iC , iB , iE Relationships in Active Mode . . . . . . 108
7.4 The i − v Characteristics of NPN Transistor . . . . . . . . . . . . . . . . . 109
7.4.1 Common Base (iC − vCB ) . . . . . . . . . . . . . . . . . . . . . . . 109
7.4.2 Common Emitter (iC − vCE ) . . . . . . . . . . . . . . . . . . . . . . 110
8 Comparisons of BJT and MOSFET 115

8.1 NMOS and NPN Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . 115
8.1.1 NMOS Triode v.s. NPN Saturation . . . . . . . . . . . . . . . . . . 116
8.1.2 NMOS Saturation v.s. NPN Forward Active . . . . . . . . . . . . . 117
8.1.3 NMOS Cut-off v.s. NPN Cut-off . . . . . . . . . . . . . . . . . . . . 118
8.2 PMOS and PNP Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . 118
8.2.1 PMOS Triode v.s. PNP Saturation . . . . . . . . . . . . . . . . . . 119
8.2.2 PMOS Saturation v.s. PNP Forward Active . . . . . . . . . . . . . 120
8.2.3 PMOS Cut-off v.s. PNP Cut-off . . . . . . . . . . . . . . . . . . . . 121
iv
1
Preamble
1.1 Goal of This Course

• Analysis and design of electronic circuits.
1.2 Content of This Course

• Electric circuit (Passive Circuit ) analysis.
— Only containing Resistor (R), Capacitor (C), and Inductor (L).
— No signal amplification.
• Electronic circuit (Active Circuit ) analysis.
— Containing transistor.
— Single transistor circuit.
— Signal amplification.
• Operational amplifier and application.
1.3 Relationship with Other Disciplines
1
Part I
System and Circuit Analysis
2
2
Signals and Systems
2.1 Basic Concepts
Table 2.1: Signals and Systems in Time and Frequency Domains.
Signals Systems
Time Domain Waveforms, x(t) Impulse Response, h(t)
Frequency Domain Spectrum, X(ω) Frequency Response, H(ω)
Definition 2.1 System stands for the transformation of signal from one to another. It
can be viewed as a process in which input signals are transformed by the system or cause
the system to respond in some way, resulting in other signals as outputs.
Objects
Abstraction
Decomposition Components
Systems Composition Systems
Analysis
System characteristics
Synthesis /brhaviors
Formalization
Models
Figure 2.1: System from engineering perspective.
• Approach
— Abstraction
∗ Representing a real object by its special characteristics; that is, the relation
between its inputs and outputs, which becomes a system.
3
Sec 2.2. Types of Systems
— Decomposition
∗ Dividing a system into several smaller systems (components) and studying
them to understand the large system.
— Composition
∗ Putting several systems together to form a larger system and studying it.
• Model
Inputs LTI Systems Outputs
States
• Relative
Input Output
States
• Perspectives
— Time domain.
— Frequency domain.
2.2 Types of Systems

• Temporal characteristic
— Continuous-Time Systems
∗ Inputs/outputs of the systems are functions defined at continuous time.
Input x(t) Continuous-Time Output y(t)

System
Magnitude
Figure 2.2: Continuous-time systems.
— Discrete-Time Systems
4
Lecture 2. Signals and Systems
Input x[n] Discrete-Time Output y[n]

System
Magnitude
6 7 8 9 t
0 1 2 3 4 5
Figure 2.3: Discrete-time systems.
Input x(t) Output y(t)

Digital System
Magnitude
Figure 2.4: Digital system.
∗ Inputs/outputs of the systems are functions defined at discrete time.

• Magnitude
— Analog systems
∗ Inputs/outputs of the system have continuously varying values.
— Digital systems
∗ Inputs/outputs of the system have discrete values.
2.3 Axiomatic Properties of Systems

• Linearity
— If an input consists of the weighted sum of several signals, then the output is
the superposition of the responses of the system to each of those signals.
y1(t) = H{x1(t)}
y2(t) = H{x2(t)} (2.1)
a × y1(t) + b × y2(t) = H{a × x1(t) + b × x2(t)}
5
Sec 2.4. Time-Domain Analysis
y(t)
x(t) Inverse x(t)
System
System
Figure 2.5: Inverse system.
• Time-Invariant
— The behavior and characteristics of the system are fixed over time.
— For example, the magnitudes of resistors and capacitors of a circuit are un-
changed over time.
y(t) = H{x(t)}
y(t − τ ) = H{x(t − τ )} (2.2)
• Causality
— The output of the system depends only on the inputs at the present time and
in the past. Z t
— For example, y(t) = x(τ )dτ .
0
• Invertability
— Distinct inputs of the system lead to distinct outputs, and an inverse system
exists.
— For example, a system which is y(t) = 2x(t), for which the inverse system is
y(t) = 12 x(t).
• Stability
— If the input of the system is bounded, then the output must be bounded.
2.4 Time-Domain Analysis

Definition 2.2 The analysis of a LTI system that is based on the relationship between
time-varying inputs and their corresponding time-varying outputs.
• Inputs/outputs are time functions (waveforms).
2.4.1 Impulse Response

• Output of the system with a fictitious input of Direc-Delta function δ(t).
— For LTI systems, the system characteristic in time domain is the system impulse response.
6
• Direc-Delta function δ(t).

(
0 if t 6= 0
δ(t) = . (2.3)
∞ if t = 0
Z T
δ(t)dt = 1, ∀T > 0. (2.4)
−T
Magnitude
∞
1/T Magnitude
t t
-T/2 T/2 0
Figure 2.6: Direc-Delta function
— Signal sampling using Direc-Delta function.

Z ∞
x(τ ) = x(t)δ(t − τ )dt (2.5)
−∞
δ (t −τ )
1 x (τ ) 1
T ∫ x(t )δ (t − τ )dt = lim T →0 x (τ ) ×
T
× T = x (τ )
x (t )
t
T
τ−
T τ+
2
2 τ
Figure 2.7: Sampling using Direc-Delta function.
— Signal reconstruction: any real time-functions can be represented by using the

integrals of Delta functions as in Eq. (2.6).
Z ∞
x(t) = x(τ )δ(τ − t)dτ (2.6)
−∞
— Convolution
7
x (τ 1 )δ (t − τ 1 )
Magnitude
x (τ 2 )δ (t − τ 2 )
x (t )
t
τ1 τ2
Figure 2.8: A time function represented by a set of delta functions.
∗ Outputs of the LTI system is the convolution of the input and the system
impulse response.
Z ∞
y(t) = x(t) ∗ h(t) = x(τ )h(t − τ )dτ (2.7)
−∞
2.4.2 Step Response

• Output of the system w.r.t. an input x(t) of step function.
µ( t )
1
t
0
(
0 if t < 0
x(t) = u(t) = . (2.8)
1 if t ≥ 0
du(t)
= δ(t). (2.9)
dt
2.4.3 Sinusoidal Response

• Output of the system w.r.t. sinusoidal function input x(t).
x(t) = cos(2t) with ω = 2πf (2.10)
— ∗ f is frequency.
∗ ω = 2πf is the angular frequency.
∗ T = f1 is period.
— For a real LTI system with a sinusoidal input function, the output is also a
sinusoidal function but with changes in both magnitude and phase.
8
x (τ 1 )δ (t − τ 1 )
Magnitude
x (τ 2 )δ ( t − τ 2 )
x (t )
t
τ1 τ2
Magnitude
1 h(t )
LTI Impulse Response
System
t
0
Time-Invariant
t
τ1 τ2
Linearity
y (t )
x (τ 2 )h (t − τ 2 )
x(τ 1 ) h (t − τ 1 )
t
τ1 τ2
Figure 2.9: Continuous time convolution operation.
h(t)
x(t) = cos ωt → y(t) = kH(ω)k cos (ωt + ]H(ω)) ,
Z ∞
where H(ω) = h(τ )e−jωτ dτ = kH(ω)k ej]H(ω) (2.11)
−∞
†Advanced Topics
Proof.
h(t)
x(t) = cos ωt → y(t) = kH(ω)k cos (ωt + ]H(ω))
9
x [ 1]δ [ n − 1]
x [ 2 ]δ [ n − 2 ]
x [ 0 ]δ [ n ]
5 4
x [ 3 ]δ [ n − 3 ]
Magnitude 4
3 x [n ] Input
n
0 1 2 3
Magnitude
4 h [n ]
3
LTI 2 Impulse Response
1
System
n
0 1 2 3
16
12
8
4 x [ 0 ]δ [ n ] → x [ 0 ]h [ n ]
n
0 1 2 3
20
15
10
5 x [1 ]δ [ n − 1 ] → x [1 ] h [ n − 1]
n
0 1 2 3 4
16
12
8
4
x [ 2 ]δ [ n − 2 ] → x [ 2 ] h [ n − 2 ]
n
0 1 2 3 4 5
12
9
6
3 x [ 3 ]δ [ n − 3 ] → x [ 3 ]h [ n − 3 ]
n
0 1 2 3 4 5 6
39 38
32 22 Output
16
10 3 y[n] = ∑ x [ k ]h [n − k ]
n k
0 1 2 3 4 5 6
Figure 2.10: Discrete time convolution operation.
10
x(t)=cos(ωt) 1
0.5
0
-5 -2.5 0 2.5 5
t
-0.5
-1
Figure 2.11: Sinusoidal waveform.
y(t) = x(t) ∗ h(t)

Z ∞
= x(τ )h(t − τ )dτ
−∞
Z ∞
= cos(ωτ )h(t − τ )dτ
−∞
Z
1 ∞ jωτ
= (e + e−jωτ )h(t − τ )dτ
2 −∞
Z Z
1 ∞ jωτ 1 ∞ −jωτ
= e h(t − τ )dτ + e h(t − τ )dτ
2 −∞ 2 −∞
0
By defining τ = t − τ , the equation above can be written as follows:
Z ∞ Z ∞
1 jω(t−τ )
0 0 1 0 0
y(t) = e h(τ )dτ + e−jω(t−τ ) h(τ 0 )dτ 0
2 −∞ 2 −∞
Z ∞ 0 0
Define H(ω) = e−jωτ h(τ )dτ 0 = kH(ω)k ej]H(ω) as a complex function of ω. Its
−∞ Z ∞
0 ∗ 0
∗
complex conjugate is H (ω) = ejωτ h (τ )dτ 0 = kH(ω)k e−j]H(ω) .Since h(t) is a real
−∞
∗ 0 0
function, h (τ ) = h(τ ). Thus, y(t) can be formulized as follows:
Z Z
1 jωt ∞ −jωτ 0 0 0 1 −jωt ∞ jωτ 0
y(t) = e e h(τ )dτ + e e h(τ 0 )dτ 0
2 −∞ 2 −∞
1 jωt j]H(ω) 1 −jωt
= e × kH(ω)k e + e × kH(ω)k e−j]H(ω)
2 2
= kH(ω)k cos (ωt + ]H(ω))
• More generally, it is the output of the system w.r.t. complex exponential function
input x(t).
x(t) = ejωt = cos(ωt) + j sin(ωt) (2.12)
11
— Complex exponential function ejωt is the eigenfunction of any LTI systems.
h(t)
x(t) = ejωt → y(t) = H(ω)ejωt (2.13)
= kH(ω)k cos (ωt + ]H(ω)) + j kH(ω)k sin (ωt + ]H(ω))
Z ∞
∗ H(ω) = h(t)e−jωt dt.
−∞
h(t )
∞
x (t ) LTI y (t ) = ∫−∞ x (τ )h (t − τ )dτ
Input time function System Output time function
h(t)
LTI y (t ) = αe ,α = H (ω ) = ∫ h( t )e d t
jωt jωt − jωt
x( t ) = e
System
h (t )
jωt
x( t) = X (ω) e LTI y(t ) = α ' e , α ' = H (ω) X (ω)
jωt
System
Figure 2.12: The output of a LTI system with exponential complex function.
2.4.4 Initial Value/Driving Free/Natural Response

• Output y(t) w.r.t. null input x(t) = 0 and possibly non-zero initial system states.
Equivalently, it is solution of Homogeneous System Equation.
2.4.5 Transient Response

• The part of system output that will disappear (die down) as time progress.
yT (t) −→ 0 as t −→ ∞. (2.14)
— For Linear Time-Invariant (LTI) circuits, yT (t) = impulse response (with nec-
essary scaling and time-shifting).
2.4.6 Steady-State Response

• The part of system output that will remain after transient response dies down.
yS (t) = y(t) − yT (t). (2.15)
12
— For Linear Time-Invariant (LTI) circuits, yT (t) = impulse response (with nec-
essary scaling and time-shifting).
2.5 Frequency-Domain Analysis

Definition 2.3 Determination of system output(s) w.r.t complex sinusoidal inputs at dif-
ferent frequencies and with specific initial system state. Results are often displayed along
frequency axis or expression as functions of angular frequency (ω).
• Input X and Output Y are complex functions of angular frequency.
Input Output
x (ω) LTI Systems y( ω)
States
2.5.1 Phasor
• An electrical-engineering representation of sinusoidal signals in frequency domain.
• A constant complex number that encodes the magnitude and the phase of the
sinusoidal signals.
Example 2.4 Given sinusoidal signal x(t) = K cos(ωt + φ), P hasor X = Kejφ , where
° °
°X ° = K and phase ]X = φ.
• x(t) = <{Xejωt } = K cos(ωt + φ).
Im[X]
K X
ϕ
Re[X]
0
2.5.2 Spectrum and Fourier Transform

• Any finite-energy signal can be represented by sinusoidal functions (including both
sin and cos waveforms) of different frequencies.
13
Sec 2.5. Frequency-Domain Analysis
— The principle of Inverse Fourier Transform.

Z ∞
1
x(t) = X(ω)ejωt dω.
2π −∞
Z ∞
1
= kX(ω)k ej]X(ω) ejωt dω. (2.16)
2π −∞
Z ∞
1
= {kX(ω)k cos (ωt + ]H(ω)) + j kX(ω)k sin(ωt + ]X(ω))} dω.
2π −∞
— X(ω) is a complex function of angular frequency ω, which expresses the values

of the signal phasor in different frequencies.
X(ω) = kX(ω)k ej]X(ω) . (2.17)
∗ kX(ω)k is called magnitude spectrum, specifying the magnitude for differ-

ent sinusoidal components.
∗ ]X(ω) is called phase spectrum, specifying the phase for different sinu-
soidal components.
— X(ω) can be obtained by taking the Fourier Transform of x(t).
Definition 2.5 Given f (t), its Fourier Transform, which is defined as follows, is a com-
plex function of the angular frequency ω.
Z ∞
F (ω) ≡ =[f (t)] = f (t)e−jωt dt. (2.18)
−∞
• Fourier Transform of f (t) is the projection of f (t) on the basis functions ejωt .
Definition 2.6 Correspondingly, the Inverse Fourier Transform is as follows:

Z ∞
−1 1
f (t) ≡ = [F (ω)] = F (ω)ejωt dω. (2.19)
2π −∞
2.5.3 System Transfer Function Hs (ω)

• A ratio between the spectra of input and output signals of a linear time-invariant
circuit.
14
Time-Domain Analysis
h(t )
∞
x(t ) y (t ) = ∫ x (τ )h (t − τ )dτ
LTI −∞
Input time function System Output time function
h(t ) 1
1
∫ X (ω) H (ω )e dω
jω t
y (t ) =
∫ X (ω )e dω
jωt
x( t) =
2π LTI 2π
System
H (ω )
X (ω) LTI Y (ω) = H (ω ) X (ω )
Input Spectrum System Output Spectrum
Frequency-Domain Analysis
Figure 2.13: Relationship between time-domain analysis and frequency-domain analysis.
— It is also known as the frequency response of a LTI system.
Y (ω)
Hs (ω) ≡
X(ω)
kY (ω)k ej]Y (ω)
=
kX(ω)k ej]X(ω)
kY (ω)k j(]Y (ω)−]X(ω))
= e (2.20)
kX(ω)k
= kHs (ω)k ej]Hs (ω)
∗ kHs (ω)k = kY (ω)k / kX(ω)k is the magnitude response of the system.

∗ ]Hs (ω) = ]Y (ω) − ]X(ω) is the phase response of the system.
• From Eq. (2.13) and Eq. (2.16), each sinusoidal component X(ω)ejωt produces an
output signal of Y (ω)ejωt = X(ω)H(ω)ejωt , as shown in Figure 2.13. Thus, y(t) can
be written as follows.
Z ∞ Z ∞
1 jωt 1
y(t) = Y (ω)e dω = X(ω)H(ω)ejωt dω. (2.21)
2π −∞ 2π −∞
• The system transfer function Hs (ω) = H(ω), which is the Fourier Transform of the
system impulse response h(t).
15
Sec 2.5. Frequency-Domain Analysis
2.5.4 Time Domain versus Frequency Domain

• The frequency response of a LTI system is the Fourier transform of the system
impulse response.
H(ω) = = {h(t)} (2.22)
• The convolution of two signals in time domain is equivalent to the multiplication of

their representations in frequency domain.
=
y(t) = x(t) ∗ h(t) ←→ H(ω)X(ω) (2.23)
16
3
Electrical Circuits
3.1 Basic Concepts

• Electric charge
— 1 coulomb of negative change contains 6.241 × 1018 electrons.
• Current
— 1 ampere is a steady flow of 1 coulomb of change pass a given point in a con-
ductor in 1 second.
Q(coulombs)
I(amperes) = . (3.1)
t(seconds)
— Time varying current
q(t + ∆t) − q(t) ∆q

i(t) = lim = (3.2)
∆t→0 ∆t ∆t
• Voltage
— Voltage difference between two points is the work in joules required to move
1 coulomb of charge from one point to the other.
W (joules)
V (volts) = . (3.3)
Q(coulombs)
• Power
— The rate at which something either absorbs or produces energy.
— The power absorbed by an electric element is the product of the voltage and
the current.
W (joules)
P (Watts) = = V (volts) × I(amperes). (3.4)
t(seconds)
3.2 Circuit Elements

• Ideal voltage source
17
Sec 3.2. Circuit Elements
Resisto r Capacitor Inductor
iR vR iC vC iL vL
Current Source Voltage Sourse GND
DC Voltage Sourse
i v 5V
Figure 3.1: Basic circuit elements.
v
vi (pure AC)
vI = VI + vi
vI
VI (pure DC)
Figure 3.2: DC signals versus AC signals.
— Voltage source provides a specified voltage across the two terminals and does not
depend on the current flowing through the source.
— The output impedance of ideal voltage source is zero.
∗ The current flowing through an ideal voltage source is completely deter-
mined by the circuit connected to the source.
• Ideal current source
— Current source provides a specified current and does not depend on the voltage
across the source.
— The output impedance of ideal current source is infinite.
∗ The voltage across an ideal current source is completely determined by the
circuit connected to the source.
• DC signals v.s. AC signals
— Figure 3.2 shows the definitions of DC signals and AC signals.
• Resistor R
— Resistance is the property of materials that resists the movement of electrons.
18
Lecture 3. Electrical Circuits
— Ohm’s Law
V (volts)
R(ohms) = (3.5)
I(amperes)
— Conductance is the inverse of resistance.
— For parallel resistors,
1
RT = (3.6)
1/R1 + 1/R2 + 1/R3 .... + 1/RN
∗ When two resistors are connected in parallel, the equivalent resistance is

smaller than any of the two resistors.
R1 R2
RT = < R1
R1 + R2
R1 R2
RT = < R2 (3.7)
R1 + R2
— For series resistors,

RT = R1 + R2 + R3 .... + RN (3.8)
• Capacitor C
— Capacitance is the ability of a capacitor to store charges on its two conductors.
Q(coulombs)
C(farad) = (3.9)
V (volts)
— For time-varying voltage vC (t) across the capacitor

∗ The capacitor is an open circuit, i.e., iC (t) = 0, when vC (t) is a constant.
∗ The voltage across the capacitor can not jump. However, the current flow-
ing through the capacitor does not have such constraint.
∆q dvC (t)
iC (t) = lim =C× (3.10)
∆t→0 ∆t dt
Z
1 t
vC (t) = iC (τ )dτ (3.11)
C −∞
— For parallel capacitors,
CT = C1 + C2 + C3 .... + CN (3.12)
— For series capacitors,
1
CT = (3.13)
1/C1 + 1/C2 + 1/C3 .... + 1/CN
• Inductor L
19
Sec 3.3. Circuit Laws
— For time-varying current iL (t) flowing through the inductor

∗ The inductor is a short circuit, i.e., vL (t) = 0, when iL (t) is a constant.
∗ The current flowing through the inductor can not jump. However, the
voltage across the inductor does not have such constraint.
∆Nφ(flux linkages)
vL (t) = lim
∆t→0 ∆t
∆LiL
= lim
∆t→0 ∆t
iL (t + ∆t) − iL (t)
= lim L × (3.14)
∆t→0 ∆t
diL (t)
= L×
dt
Z
1 t
iL (t) = v(τ )dτ (3.15)
L −∞
— For parallel inductors,
1
LT = (3.16)
1/L1 + 1/L2 + 1/L3 .... + 1/LN
— For series capacitors,
LT = L1 + L2 + L3 .... + LN (3.17)
• Dual circuit
— Capacitor and Inductor formulas are the same except that the symbols differ.
— Capacitor
vo (t) dvo (t)
iS (t) = +C (3.18)
R dt
— Inductor
dio (t)
vS (t) = io (t)R + L (3.19)
dt
3.3 Circuit Laws

• Kirchhoff’s voltage law ( KVL )
— The algebraic sum of the voltages around any closed loop of a circuit is zero.
• Kirchhoff’s current law ( KCL )
— The algebraic sum of the currents entering every node must be zero.
20
iS vS iO
C R vO R
Curr ent Source Voltage Source

Parallel Serial
v i
C L
R R
Figure 3.3: Similarity between capacitor and inductor.
3.4 Network Theorems

Definition 3.1 Linear circuit is formed by interconnecting the terminals of independent sources,
controlled sources, and linear passive elements to form one or more closed paths.
• Linear passive elements include Resistor, Capacitor, and Inductor.

— The i − v characteristics of these elements satisfy the conditions of linearity.
∗ Resistor
v1 (t) = i1 (t)R
v2 (t) = i2 (t)R (3.20)
a × v1 (t) + b × v2 (t) = (a × i1 (t) + b × i2 (t))R
∗ Capacitor
d
(v1 (t))
i1 (t) = C
dt
d
i2 (t) = C (v2 (t)) (3.21)
dt
d
a × i1 (t) + b × i2 (t) = C (a × v1 (t) + b × v2 (t))
dt
∗ Inductor
Z t
i1 (t) = L v1 (τ )dτ
0
Z t
i2 (t) = L v2 (τ )dτ (3.22)
0
Z t
a × i1 (t) + b × i2 (t) = L (a × v1 (τ ) + b × v2 (τ ))dτ
0
Theorem 3.2 In a linear network containing multiple sources, the voltage across or current
21
Sec 3.4. Network Theorems
R1 R2
VA IA R3 V
(a)
=
R1 R2
R3
VA V1
(b)
+
R1 R2
R3
IA V2
(c)
Figure 3.4: Example of linear circuit with multiple independent sources.
through any passive element may be found as the algebraic sum of the individual voltages
or currents due to each of the independent sources action along, with all other independent
sources deactivated.
• Voltage source is deactivated by replacing it with a short circuit.

• Current source is deactivated by replacing it with an open circuit.
• Controlled sources remain active when the superposition theorem is applied.
Example 3.3 Given the circuit in Figure 3.4, find the voltage across the resistor R3 using
the superposition theorem of linear network.
1. The voltage across the resistor R3 is the superposition of the voltage when each
independent source actions alone, as shown in Figure 3.4 (b) and (c).
V = V1 + V2 (3.23)
2. The contribution of the voltage source VA .

• The current source IA is replaced with an open circuit.
R3
V1 = VA (3.24)
R1 + R2 + R3
3. The contribution of the current source IA .
22
• The voltage source VA is replaced with an short circuit.
R1 R3
V2 = IA (3.25)
R1 + R2 + R3
3.4.1 Equivalent Circuits of One-Port Networks
1
Linear Linear
Network Network
2
A B
(a)
ZT H
1
Linear
VT H Network
2 B
(b)
1
Linear
IN YN Network
2 B
(c)
Figure 3.5: Equivalent circuits. (a) The original circuit. (b) Thevenin’s equivalent. (c)
Norton’s equivalent.
• Equivalent circuit
— A reduction of a complex linear circuit into a simpler form.
— A model of a complex linear circuit contained in a black box.
Theorem 3.4 Thevenin’s theorem states that an arbitrary linear, one port network such
as network A in Figure 3.5 (a) can be replaced at terminals 1, 2 with an equivalent series-
connected voltage source VT H and impedance ZT H as in Figure 3.5 (b).
• VT H is the open-circuit voltage of network A at terminals 1, 2.

• ZT H is the ratio of the open-circuit voltage over short circuit current determined at
terminals 1, 2.
— The equivalent impedance looking into network A through terminals 1, 2 with
all independent sources deactivated.
∗ Voltage sources are replaced by short circuits.
∗ Current sources are replaced by open circuits.
23
Theorem 3.5 Norton’s theorem states that an arbitrary linear, one port network such as
network A in Figure 3.5 (a) can be replaced at terminals 1, 2 with an equivalent parallel-
connected current source IN and admittance YN as in Figure 3.5 (c).
• IN is the short-circuit current flowing through terminals 1, 2 due to network A.

• YN is the ratio of short-circuit current over open-circuit voltage at terminals 1, 2.
• Conversion of equivalent circuits.
— Any method for determining ZT H is equally valid for finding YN .
VT H
IN = ISC = (3.26)
ZT H
1
VT H = VOC = IN × (3.27)
YN
1
ZT H = (3.28)
YN
Example 3.6 In Figure 3.6, VA = 4V , IA = 2A, R1 = 2 Ω, R2 = 3 Ω, find the Thevenin’s
equivalent circuit and Norton’s equivalent circuit for the network to the left of terminals
1, 2.
R1 R2
1
VA IA
Figure 3.6: Examples of Thevenin’s and Norton’s equivalent circuits.
1. Thevenin’s equivalent
• VT H is the open-circuit voltage at terminals 1, 2.
VT H = VA + IA × R1 = 4 + 4 = 8V. (3.29)
• ZT H is the ratio of the open-circuit voltage over short circuit current determined
at terminals 1, 2 with network B disconnected.
— By the superposition of the short-circuit current caused by VA and IA , the
24
short circuit current can be found.
I1,2 = I(VA ) + I(IA )

1 R1
= VA + IA (3.30)
R1 + R2 R1 + R2
8
= A.
5
— By definition, ZT H can be derived as VT H /I1,2 = 5 Ω.

• Alternatively, ZT H can be found as the equivalent impedance for the circuit to
the left of terminals 1, 2.
— VA is replaced with short circuit.
— IA is replaced with open circuit.
ZT H = R1 + R2 = 5 Ω. (3.31)
2. Norton’s equivalent
• IN is the short-circuit current at terminals 1, 2, which can be derived as in Eq.
(3.30).
• YN is the ratio of the short-circuit current over the open-circuit voltage with
network B disconnected. From Eq. (3.29), the open circuit voltage is 8V .
Thus, YN = 85 A/8V = 1/5S.
• Alternatively, YN = 1/ZT H = 1/5 = 0.2S.
3.4.2 Equivalent Circuits of Two-Port Networks

• A two-port network is an electrical circuit or device with two pairs of terminals.
— Figure 3.7 depicts a two-port linear network.
— Only two of the four variables V1 , V2 , I1 , I2 can be independent.
I1 I2
+ Linear +
V1 V2
- Network -
I1 I2
Figure 3.7: Two-port linear network.
Characterization of Two-Port Networks
• Z parameters (V1 , V2 depend on I1 , I2 )
25
— The four zij parameters represent impedance.

— z12 and z21 are transfer impedances.
— Each of the zij parameters can be evaluated by open-circuiting an appropriate
port of the network.
V1 = z11 I1 + z12 I2
V2 = z21 I1 + z22 I2 (3.32)
V1
z11 = |I =0
I1 2
V1
z12 = |I =0
I2 1
V2
z21 = |I =0 (3.33)
I1 2
V2
z21 = |I =0
I2 1
— Z parameters in matrix form.

" # " #" #
V1 z11 z12 I1
= (3.34)
V2 z21 z22 I2
• Y parameters (I1 , I2 depend on V1 , V2 )

— The four yij parameters represent admittance.
— y12 and y21 are transfer admittances.
— Each of the yij parameters can be evaluated by short-circuiting an appropriate
port of the network.
I1 = y11 V1 + y12 V2
I2 = y21 V1 + y22 V2 (3.35)
I1
y11 = |V =0
V1 2
I1
y12 = |V =0
V2 1
I2
y21 = |V =0 (3.36)
V1 2
I2
y21 = |V =0
V2 1
26
— Y parameters in matrix form.

" # " #" #
I1 y11 y12 V1
= (3.37)
I2 y21 y22 V2
— Relation between yij parameters and zij parameters.

" # " #−1 " #
y11 y12 z11 z12 1 z22 −z21
= = (3.38)
y21 y22 z21 z22 z11 z22 − z12 z21 −z12 z11
• H parameters (V1 , I2 depend on I1 , V2 )

— The h11 represents impedance.
— The h22 represents admittance.
— Parameters h11 and h21 are obtained by short-circuiting port 2.
— Parameters h12 and h22 are obtained by open-circuiting port 1.
V1 = h11 I1 + h12 V2
I2 = h21 I1 + h22 V2 (3.39)
V1
h11 = |V =0
I1 2
V1
h12 = |I =0
V2 1
I2
h21 = |V =0 (3.40)
I1 2
I2
h22 = |I =0
V2 1
— H parameters in matrix form.

" # " #" #
V1 h11 h12 I1
= (3.41)
I2 h21 h22 V2
Example 3.7 In Figure 3.8, R1 = 10 Ω, R2 = 6 Ω, find the z parameters and the h

parameters for the network.
27
I1 R1 I2
+ +
V1 0.3I a Ia R2 V
2
- -
I1 I2
Figure 3.8: Example of two-port linear network.
• From Eq. (3.33), the zij parameters can be obtained as follows.
V1 (10 + 6)Ia 16
z11 = |I =0 = = = 12.31 Ω
I1 2 Ia + 0.3Ia 1.3
V1 6Ia − 0.3Ia × 10 3
z12 = |I =0 = = = 2.31 Ω
I2 1 Ia + 0.3Ia 1.3
V2 6Ia 6
z21 = |I =0 = = = 4.62 Ω
I1 2 Ia + 0.3Ia 1.3
V2 6Ia 6
z22 = |I =0 = = = 4.62 Ω
I2 1 Ia + 0.3Ia 1.3
• From Eq. (3.40), the hij parameters can be calculated as follows.
V1 I1 × R1
h11 = |V2 =0 = = R1 = 10 Ω
I1 I1
V1 Ia × R2 − 0.3Ia × R1 3
h12 = |I1 =0 = = = 0.5
V2 Ia × R2 6
I2
h21 = |V =0 = −1
I1 2
I2 Ia + 0.3Ia 1.3
h22 = |I1 =0 = = = 0.217S.
V2 Ia × R2 6
Equivalent Circuits of Special Two-Port Networks
• T-Model network. (Figure 3.9 (a))

— Z1, Z2,and Z3 can be derived from the Z parameters of a two-port networks.
" # " #
z11 z12 Z1 + Z3 Z3
= (3.42)
z21 z22 Z3 Z2 + Z3
• π-Model network. (Figure 3.9 (b))
28
— Za, Zb,and Zc can be derived from the Y parameters of a two-port networks.

" # " #
1 1 1
y11 y12 Za
+ Zc − Zc
= 1 1 1
(3.43)
y21 y22 − Zc Zb
+ Zc
• Transformation from π-Model to T-Model.
ZaZc
Z1 =
Za + Zb + Zc
ZbZc
Z2 = (3.44)
Za + Zb + Zc
ZaZb
Z3 =
Za + Zb + Zc
• Transformation from T-Model to π-Model.
Z1Z3 + Z1Z2 + Z2Z3

Za =
Z2
Z1Z3 + Z1Z2 + Z2Z3
Zb = (3.45)
Z1
Z1Z3 + Z1Z2 + Z2Z3
Zc =
Z3
I1 I2
Z1 Z2
V1 Z3 V2
(a) T-Model Network

I1 I2
Zc
V1 Za Zb V2
(b) π−Model Network
Figure 3.9: Equivalent circuits of two port networks. (a) T-Model Network. (b) Pi-
Model Network.
29
Sec 3.5. Laplace Transforms
3.5 Laplace Transforms

• Laplace Transform
— A mathematical tool for representing system transfer functions of causal LTI
systems.
— A generalization of Fourier transform.
∗ The result of Fourier transform can be obtained by evaluating the Laplace
transform along the imaginary axis.
Definition 3.8 Given f (t) with f (t) = 0 for t < 0, its Laplace Transform, which is
defined as follows, is a complex function over a complex-number domain.
Z Z
∞ ∞ ¡ ¢
F (s) ≡ L[f (t)] , −st
f (t)e dt = f (t)e−σt e−jωt dt. (3.46)
0− 0−
Definition 3.9 Correspondingly, the Inverse Laplace Transform is as follows:

I
−1 1
f (t) ≡ L [F (s)] = F (s)est ds. (3.47)
2πj c
Example 3.10 Given f (t) & g(t) (f (t) = g(t) = 0 for t < 0) and their Laplace Trans-
forms F (s) & G(s),the following shows the properties of Laplace Transform.
• Linearity
L
y(t) = af (t) + bg(t) ←→ Y (s) = aF (s) + bG(s) (3.48)
• Time Derivatives
df (t) L
y(t) = ←→ Y (s) = sF (s) − f (0− ) (3.49)
dt
dn f (t) L df (0− ) f (0− )

y(t) = ←→ Y (s) = sn F (s) − sn−1 f (0− ) − sn−2 ....... − dn−1
dt dt dt
• Time Integrals
Z t
L F (s) y(0− )
y(t) = f (τ )dτ + y(0− ) ←→ Y (s) = + (3.50)
0− s s
• Time Scaling
L 1 s
y(t) = f (αt) ←→ F ( ), where α > 0. (3.51)
α α
• Time Delay
L
y(t) = f (t − t0 ) ←→ Y (s) = e−st0 F (s), where t0 > 0. (3.52)
30
• t Multiplication
L dn F (s)
y(t) = tn f (t) ←→ Y (s) = (−1)n (3.53)
dsn
• s Shift
L
y(t) = eat f (t) ←→ Y (s) = F (s − a) (3.54)
• Convolution
L
y(t) = x(t) ∗ h(t) ←→ Y (s) = X(s)H(s) (3.55)
• Product I
L 1
y(t) = f (t)x(t) ←→ Y (s) = F (s)X(s − λ)dλ. (3.56)
2πj c
Example 3.11 Laplace Transform Pairs1
L
f (t) ←→ F (s)
L
δ(t) ←→ 1
L A
A ←→
s
L n!
Atn ←→ A( )
sn+1
L A
Aeat ←→
s−a
L s
cos ω 0 t ←→
s + ω20
2
L ω0
sin ω 0 t ←→
s + ω20
2
L Aejθ Ae−jθ 2A cos θ(s − a − ω 0 tan θ)

2Aeat cos (ω 0 t + θ) ←→ + =
s − (a + jω0 ) s − (a − jω 0 ) (s − a)2 + ω 20
3.6 Equivalent Circuits in Laplace Domain

• Capacitor
— i − v characteristic in Laplace domain.
∗ Admittance of capacitor in Laplace domain is sC.
dvC (t) L
iC (t) = C ←→ IC (s) = C(sVC (s) − vC (0− )) (3.57)
dt
∗ Figure 3.10 (a) depicts the KCL equivalent circuit in Laplace domain.
— v − i characteristic in Laplace domain.
1
Footnote
31
Sec 3.6. Equivalent Circuits in Laplace Domain
IC (s )
I C (s )
1/ s C
VC (s ) sC C vC (0− ) VC (s ) 1
v C ( 0− )
s
(a) (b)
IC (s)
s L I L ( s)
VL (s) 1 / s L 1 V L (s )
iL (0− )
s L Li ( 0 − )
(c) (d)
Figure 3.10: (a) KCL equivalent circuit of a capacitor in Laplace domain. (b) KVL
equivalent circuit of a capacitor in Laplace domain. (c) KCL equivalent circuit of an
inductor in Laplace domain. (b) KVL equivalent circuit of an inductor in Laplace domain.
∗ Impedance of capacitor in Laplace domain is 1/sC.

Z
1 t
vC (t) = iC (τ )dτ (3.58)
C −∞
Z
1 t L 1 1
= iC (τ )dτ + vC (0− ) ←→ VC (s) = IC (s) + vC (0− )
C 0 sC s
∗ Figure 3.10 (b) depicts the KVL equivalent circuit in Laplace domain.
• Inductor
— i − v characteristic in Laplace domain.
∗ Admittance of inductor in Laplace domain is 1/sL.
Z
1 t
iL (t) = vL (τ )dτ (3.59)
L −∞
Z
1 t L 1 1
= vL (τ )dτ + iL (0− ) ←→ IL (s) = VL (s) + iL (0− )
L 0 sL s
∗ Figure 3.10 (c) depicts the KCL equivalent circuit in Laplace domain.
— v − i characteristic in Laplace domain.
∗ Impedance of inductor in Laplace domain is sL.
diL (t) L
vL (t) = L ←→ VL (s) = L(sIL (s) − iL (0− )) (3.60)
dt
∗ Figure 3.10 (d) depicts the KVL equivalent circuit of an inductor in Laplace
32
domain.
3.7 System Transfer Function in Time and Laplace

Domains
• Two ways to deduce the system transfer function in time and Laplace domains.
— Start in time domain and then take the Laplace transform.
— Start in Laplace domain and use Inverse Laplace transform to return to time
domain.
Example 3.12 Consider the RC circuit in Figure 3.11, the input is the current source
is (t) and the output vo (t) is the voltage across the RC components. Find out the system
transfer function and the outputs w.r.t. different inputs.
iS R C vo
Figure 3.11: The RC circuit to be solved in time domain and Laplace domain.
• By writing the node equation with KCL in time domain, we obtain the system
equation.
vo (t) dvo (t)
iS (t) = +C (3.61)
R dt
• By taking Laplace transform to both sides, the system equation in Laplace domain
can be derived.
Vo (s)
IS (s) = + C(sVo (s) − vo (0− )) (3.62)
R
• The system transfer function in Laplace domain.
Vo (s) 1 R
H(s) = |vo (0− )=0 = = (3.63)
IS (s) sC + (1/R) 1 + sRC
33
Sec 3.7. System Transfer Function in Time and Laplace Domains
Initial Value (Driving Free) Response
• Given iS (t) = 0, IS (s) = 0, the output can be obtained from Eq. (3.62).
Vo (s)
0 = + C(sVo (s) − vo (0− ))
R
vo (0− ))
⇒ Vo (s) = (3.64)
s + (1/RC)
• The time domain response can be calculated by taking Inverse Laplace transform.
vo (t) = vo (0− )e−t/RC (3.65)
Impulse Response
• Given iS (t) = δ(t); IS (s) = 1, the output can be obtained from Eq. (3.63).
— For simplicity, we do not consider initial condition, i.e., vo (0− ) = limt→0− vo (t) =
0.
R
Vo (s) = (3.66)
1 + sRC
1 −t/RC
vo (t) = e (3.67)
C
Step Response
• Given iS (t) = u(t); IS (s) = 1s , the output can be obtained from Eq. (3.63).
0.
1
C R R
Vo (s) = = − (3.68)
s(s + (1/RC)) s s + (1/RC)
— The capacitor is like an open circuit once it is fully charged.
vo (t) = R − Re−t/RC = R(1 − e−t/RC ) (3.69)
Sinusoidal Response
• Given iS (t) = cos (ω0 t) u(t); IS (s) = s/ (s2 + ω 20 ), the output can be obtained from
Eq. (3.63).
0.
R s A Bs + D
Vo (s) = × 2 2
= + 2 (3.70)
1 + sRC s + ω0 1 + sRC s + ω 20
34
— The term A/ (1 + sRC) stands for transient response, which can be trans-
formed into exponentially decaying time function.
¡ ¢
∗ A = −R2 C/ 1 + (ω 0 RC)2 .
— The term (Bs + D)/ (s2 + ω 20 ) represent the steady state response, which shall
yield the time-domain signal.
Bs + D Bs D
2
= 2 + 2
2
s + ω0 s + ω0 s + ω20
2
D
⇒ vo (t) = B cos (ω0 t) + sin (ω 0 t)
ω0
= K 0 cos (ω 0 t − φ) (3.71)
r ³ ´2
D
∗ K0 = B2 + ω0
.
∗ φ = tan−1 ( ωD ).
µ 0 B³ ´2 ¶
ω0
∗ B = R/ 1 + 1/RC .
³ ´2 µ ³ ´2 ¶
1 ω0 ω0
∗ D = C 1/RC / 1 + 1/RC .
1
— ω 0 ¿ RC
∗ B ' R, D ' 0, vo (t) = R cos (ω 0 t) .
∗ At low frequency, the capacitor is similar to an open circuit.
1
— ω 0 À RC
¡ ¢
∗ B ' 0, D ' C1 , vo (t) = ω01C sin (ω0 t) = ω01C cos ω 0 t − π2 .
∗ At high frequency, the capacitor is similar to a short circuit.
— The circuit acts as a low-pass filter.
Example 3.13 Consider the RLC circuit in Figure 3.12, the input is the current source
is (t) and the output vo (t) is the voltage across the RLC components. Find out the system
transfer function and the outputs w.r.t. different inputs.
iS R C L vo
Figure 3.12: The RLC circuit to be solved in time domain and Laplace domain.
Start in Time Domain
35
iR (t ) iC (t ) iL (t)
iS (t) R C L vo (t )
Figure 3.13: Time domain analysis.
• By writing the node equation with KCL in time domain, we obtain
iS (t) = iR (t) + iC (t) + iL (t), (3.72)
where
vo (t)
iR (t) =
R
dvo (t)
iC (t) = C (3.73)
Z dt Z
1 t 1 t
iL (t) = vo (τ )dτ = vo (τ )dτ + iL (0− )
L −∞ L 0
• The system equation in time domain.

Z t
vo (t) dvo (t) 1
iS (t) = +C + vo (τ )dτ + iL (0− ) (3.74)
R dt L 0
• Apply the Laplace transform to both sides of Eq.(3.74).
Vo (s) 1 1
IS (s) = + C(sVo (s) − vo (0− )) + Vo (s) + iL (0− ), (3.75)
R sL s
where IS (s) , L[iS (t)] and Vo (s) = L[vo (t)].

• The system transfer function in Laplace domain.
— Assume no initial condition, i.e., vo (0− ) = limt→0− vo (t) = 0 and iL (0− ) =
limt→0− iL (t) = 0.
Vo (s) 1 1
= 1/( + sC + ) (3.76)
IS (s) R sL
Start in Laplace Domain
36
1 1 1 − Vo (s)
IS (s) sC −
iL (0 )
R C ov(0 ) sL s
Figure 3.14: Laplace domain analysis.
• Replace all the circuit elements by their KCL equivalent circuits in Laplace domain.
1
R −→
R
C −→ sCVo (s) − Cvo (0− ) (3.77)
1 1
L −→ Vo (s) + iL (0− )
sL s
IS (s) = IR (s) + IC (s) + IL (s)

µ ¶
Vo (s) ¡ −
¢ 1 1 −
= + sCVo (s) − Cvo (0 ) + Vo (s) + iL (0 ) (3.78)
R sL s
• The system transfer function.
IS (s) = IR (s) + IC (s) + IL (s)|vo (0− )=0 ,iL (0− )=0

Vo (s) 1
= + sCVo (s) + Vo (s) (3.79)
R sL
Vo (s) 1
⇒ = 1 1
IS (s) ( R + sC + sL )
Impulse Response
• Impulse response is the system output w.r.t an input signal of impulse function. It
is also the transfer function of the system which can be used to find system poles
and zeros.
L
— iS (t) = δ(t); δ(t) −→ 1.
— Assume no initial condition.
1
Vo (s) = 1 IS (s)
( R1
+ sC + sL )
1
= 1 1 ·1 (3.80)
( R + sC + sL )
sRL
= 2
s RLC + sL + R
37
• System poles and zeros are the roots of denominator and numerator of the system
transfer function.
— Zeros , the roots of N(s).
— Poles , the roots of D(s).
Vo (s) N(s)
H(s) = , (3.81)
IS (s) D(s)
— The simplest way to obtain H(s) is by analyzing the system impulse response
in Laplace domain.
Vo (s)
H(s) = = Vo (s)
1
sRL
= 2 (3.82)
s RLC + sL + R
N(s)
=
D(s)
• The time-domain expression of vo (t) , L−1 [Vo (s)] depends on the nature of the
system poles, which are the roots of denominator.
— Let the system characteristic equation be equal to 0.
s2 RLC + sL + R = 0 (3.83)
— Rewrite it as
as2 + bs + c = 0 with a = RLC, b = L, c = R (3.84)
— The roots are

√
−b ± b2 − 4ac
sP and s0P =
2a
r
b b 4ac
= − ± ( )2 − (3.85)
2a r 2a 4a2
b b c
= − ± ( )2 −
2a 2a a
— The nature of the roots (sP , s0P ) shall depend on the value of the critical expression.
b 2 c
λ2 , ( ) −
2a a
L 2 R
= ( ) −( ) (3.86)
2RLC RLC
1 2 1
= ( ) −
2RC LC
38
Impulse Response of RLC Circuit
0.8
0.6
0.4
vo(t)
0.2
0 2 4 6 8 10 12 14
0.2
0.4
t
Underdamped
Criticall Damped
Overdamped
Figure 3.15: Comparison of system impulse responses in different cases.
— Traditionally, we define two more parameters.

∗ Neper frequency α.
b 1
α, = (3.87)
2a 2RC
∗ Resonant frequency ω 0 .
r
c 1
ω0 , =√ (3.88)
a LC
— We can now rewrite the roots of the characteristics equation.

q
sP and s0P = −α ± α2 − ω20 (3.89)
• Three distinct cases are possible with respect to sP and s0P depending on the values
of α and ω0 .
• Overdamped
p
— λ , α2 − ω20 is real, i.e., α2 > ω 20 .
— sP and s0P are two real, distinct and negative values.
— Vo (s) can be factorized as follows.
s0
∗ A = RL/(1 − sPP ) and B = RL/(1 − ssP0 ).
P
39
∗ Both A and B are real numbers.
sRL
Vo (s) =
RLC(s − sP )(s − s0P )
A B
= + (3.90)
s − sP s − s0P
A B
= +
s + |sP | s + |s0P |
— By taking the inverse Laplace transform, the response of vo (t) (without initial
condition) can be formulized as follows:
0
vo (t) = Ae−|sP |t + Be−|sP |t (3.91)
— Figure 3.15 depicts the vo (t) in the overdamped case.

• Underdamped
p
— λ , α2 − ω20 is imaginary, i.e., α2 < ω 20 .
— sP and s0P are two complex conjugate poles.
p
∗ The damped resonant frequency ωd , ω 20 − α2 is real.
sP and s0P = −α ± jω d (3.92)
— Vo (s) can be factorized as follows.

∗ A and B are complex conjugates.
sRL
Vo (s) = (3.93)
RLC (s − (−α + jω d )) (s − (−α − jωd ))
A B
= + (3.94)
s − (−α + jω d ) s − (−α − jω d )
— Taking inverse Laplace transform, v0 (t) can be obtained.

∗ Note that (A + B) and j(A − B) are real number since A and B are
complex conjugates.
vo (t) = Ae(−α+jωd )t + Be(−α−jωd )t

¡ ¢
= e−αt Aejωd t + Be−jωd t
= e−αt [A (cos ω d t + j sin ω d t) + B (cos ω d t − j sin ωd t)] (3.95)
= e−αt [(A + B) cos ωd t + j(A − B) sin ωd t]
— Figure 3.15 depicts the vo (t) in the underdamped case.

• Critically damped
p
— λ , α2 − ω20 =0, i.e., α2 = ω20 .
40
jω
Critically damped +jω
-α
sP sP ' 0 σ
Overdamped -jω
Underdamped
Figure 3.16: Locations of poles and zeros.
— sP and s0P = −α.
sRL A B
Vo (s) = 2
= + (3.96)
RLC(s − (−α)) s + α (s + α)2
— Taking inverse Laplace Transform, v0 (t) can be obtained.
v0 (t) = Ae−αt + Bte−αt (3.97)
— Figure 3.15 depicts the v0 (t) in the case of critically damped.

• Summary
— The positions of poles determine the nature of System Response.
√ 1 !
sP and s0P = −α ± α2 − ω 2 with α = and ω0 = √
2RC LC
— Response is overdamped
∗ if α2 − ω20 > 0 and sP , s0P are two distinct real numbers.
— Response is underdamped
∗ if α2 − ω20 < 0 and sP , s0P are complex conjugate numbers.
— Response is critically damped
∗ if α2 = ω 20 and sP , s0P are real and the same.
— The positions of system poles move along the path (known as Root Locus)
shown in the following diagram.
Sinusoidal Response
• Sinusoidal response is the system output w.r.t an input signal of sinusoidal function.
— iS (t) = cos (ωt) u(t) or IS (s) = L[iS (t)] = s/ (s2 + ω 2 ) .
41
Sec 3.8. Bode Plots
— For simplicity, we do not consider initial condition.
s2 RL
Vo (s) = (3.98)
(s2 + ω 2 )(s2 RLC + sL + R)
s2 RL A B Ds + E
= 0 2 2
= + 0
+ 2
RLC(s − sP )(s − sP )(s + ω ) (s − sP ) (s − sP ) (s + ω2 )
— Instead of solving for the coefficients A, B, D, E analytically by hand (which is

a practically impossible task), we shall deduce the time and frequency domain
responses by reasoning.
— Time-Domain Response
∗ The terms A/(s−sP ) and B/(s−s0P ) stand for transient response. Both can
be transformed into damped response in time with exponentially decaying
envelop.
1
e−αt where α = (3.99)
2RC
∗ The term (Ds + E) /(s2 + ω 2 ) represent the steady state response, which
shall yield the time-domain signal K 0 cos(ωt − φ).
√
· K 0 = D2 + E 2 .
E
· φ = tan−1 ( D ).
Ds + E Ds E
= + 2
(s2 + ω 2 ) (s2
+ ω ) (s + ω 2 )
2
⇒ D cos(ωt)+E sin(ωt)
= K 0 cos(ωt − φ) (3.100)
3.8 Bode Plots

• A graph used to show the frequency response of an LTI system.
— To plot the magnitude in decibels (dB) and use a log scale for ω.
∗ The log scale helps to compress a wide range of data.
— Both the magnitude and the phase of the transfer function versus the angular
frequency ω.
• System transfer function H(s) can be written as a product of factors of the following
items.
1. Constant factor K.
2. Poles or zeros at the origin, s±N .
3. Real poles or zeros, (T s + 1)±N .
4. Complex-conjugate poles or zeros, (T 2 s2 +2T ζs+1)±N , where ζ is the damping
42
ratio and 0 < ζ < 1.

N(s)
H(s) = (3.101)
D(s)
• The magnitude of H(s) in dB allows us to plot the factors individually and sum the results
to obtain the complete plot.
|H(s)|dB = 20 log10 |H(s)| (3.102)
— Given H(s) as follows,
(1 + Tz1 s)(1 + Tz2 s)

H(s) = K (3.103)
(1 + Tp1 s)(1 + Tp2 s)
— |H(s)|dB can be obtained by plotting each factor individually
|H(s)|dB = 20 log10 |H(s)|

¯ ¯
¯ (1 + Tz1 s)(1 + Tz2 s) ¯
= 20 log10 ¯¯K ¯ (3.104)
(1 + Tp1 s)(1 + Tp2 s) ¯
= 20 log10 |K| + 20 log10 |1 + Tz1 s| + 20 log10 |1 + Tz2 s|
−20 log10 |1 + Tp1 s| − 20 log10 |1 + Tp2 s|
• Bode plot for each of the factors.

1. Constant factor, K.
— Magnitude
∗ The magnitude 20 log10 |K| is a constant.
— Phase
∗ The phase is a constant and equal to 0 ◦ (ej0 = 1) or ±180 ◦ (e±jπ = −1)
depending on whether K is positive or negative, respectively.
2. Poles or zeros at the origin, s±N .
— Magnitude
∗ The magnitude is a straight line that intersects the ω axis (0dB) at
ω = 1 and has a slope of ±20dB/decade.
— Phase
∗ The phase is a constant and equal to ±N90 ◦ .
H(jω) = (jω)±N = (ωejπ/2 )±N (3.105)
|H(jω)|dB = 20 log10 ω ±N
= ±20N log10 ω (3.106)
43
Sec 3.8. Bode Plots
]H(jω) = ±N(jπ/2) = ±N90 ◦ (3.107)
3. Real poles or zeros, (T s + 1)±N .

— Poles or zeros locate at − T1 .
¡ ¢±N
H(jω) = (jωT + 1)±N = rejθ (3.108)
|H(jω)|dB = rdB
µq ¶±N
2
= 20 log10 1 + (ωT ) (3.109)
¡ ¢
= ±10N log10 1 + (ωT )2
— Magnitude
∗ Low frequency response (ωT ¿ 1; ω ¿ T1 ): A horizontal line of 0dB.
|H(jω)|dB = ±10N log10 (1) = 0 dB (3.110)
∗ High frequency response (ωT À 1; ω À T1 ): A straight line of slope

±20NdB/decade that intersects 0dB when ω = T1 .
|H(jω)|dB = ±10N log10 (ωT )2

µ ¶
ω
= ±20N log10 (3.111)
1/T
µ ¶
1
= ±20N log10 ω − log10
T
∗ Corner frequency response ω = T1 .
|H(jω)|dB = ±10N log10 2 = ±3NdB (3.112)
|H(jω)| = 10±3N/20 = 0.7079N (negative) or 1.4125N ( positive )

(3.113)
— Phase
]H(jω) = ±N θ = ±N tan−1 ωT (3.114)
∗ Low frequency: ]H(jω) ≈ 0 ◦ .

∗ Corner frequency: ]H(jω) ≈ ±N45 ◦ .
∗ High frequency: ]H(jω) ≈ ±N90 ◦ .
4. Complex conjugate poles or zeros, (T 2 s2 + 2ζT s + 1)±N .
— For simplicity, we consider only the case of a single pair of complex conju-
gate poles.
44
∗ If the poles are repeated by N times, all coordinates on the curves will
be multiplied by N.
∗ If we have zeros instead of poles, curves are mirror images through the
ω axis.
1
H(s) = 2 2 (3.115)
T s + 2ζT s + 1
³¡ ¢ ´1/2
2 2 2 2 2 2
|H(jω)|dB = −20 log10 1 − T ω + 4ζ T ω
³¡ ¢2 ´
= −10 log10 1 − T 2 ω2 + 4ζ 2 T 2 ω2 (3.116)
— Magnitude
∗ Low frequency response (ωT ¿ 1; ω ¿ T1 ): A horizontal line of 0dB.
∗ High frequency response (ωT À 1; ω À T1 ): A straight line of slope
±40dB/decade that intersects 0dB when ω = T1 .
³¡ ¢2 ´
|H(jω)|dB = −10 log10 1 − T 2 ω 2 + 4ζ 2 T 2 ω 2
³¡ ¢2 ´
' −10 log10 T 2 ω 2 + 4ζ 2 T 2 ω 2 ' −40 log10 (T ω)
µ ¶
1
= −40 log10 ω − log10 (3.117)
T
— Phase
∗ 0 < ω < 1/T.
2T ζω
]H(jω) = − tan−1 (3.118)
1 − T 2ω2
∗ ω > 1/T.
2T ζω
]H(jω) = −180 + tan−1 (3.119)
T 2ω2 −1
Example 3.14 Consider the transfer function Vo (s) = R/(1 + sRC) where R = 1 kΩ
and C = µF, express its frequency responses including both the magnitude and the phase
responses with Bode Plot.
• Vo (s) can be firstly written as follows.
1
Vo (s) = R × (3.120)
1 + sRC
• The factor R.
— Magnitude is a constant and equal to 20 log10 103 = 60dB.
— Phase is a constant and equal to 0 ◦ .
• The factor 1/(1 + sRC).
— ω < 1/RC
45
Sec 3.8. Bode Plots
∗ Magnitude is a constant and equal to 0dB.

∗ Phase is around 0 ◦ .
— ω ≥ 1/RC
∗ Magnitude is a straight line of slope −20dB/decade.
∗ Phase is around −45 ◦ when ω = 1/RC.
∗ Phase is around −90 ◦ when ω À 1/RC.
B ode D iagram
60
50
Magnitude (dB)
40
30
20
0
Phase (deg)
-45
-90 1 2 3 4 5
10 10 10 10 10
Frequency (rad/sec)
Figure 3.17: Bode plot for the transfer function Vo (s) = R/(1 + sRC).
Example 3.15 Consider the transfer function Vo (s) = sRC/(1 + sRC) where R = 1 kΩ
and C = µF, express its frequency response including both the magnitude and the phase
responses with Bode Plot.
1
Vo (s) = RC × s × (3.121)
1 + sRC
• The factor RC
— Magnitude is a constant and equal to 20 log10 10−3 = −60dB.
• The factor s
— Magnitude is a straight line of slope 20dB/decade and intersects the ω-axis at
ω = 1.
— Phase is 90 ◦ .
46
• The factor 1/(1 + sRC).

— ω < 1/RC
∗ Magnitude is a constant and equal to 0dB.
∗ Phase is around 0 ◦ .
— ω ≥ 1/RC
∗ Magnitude is a straight line of slope −20dB/decade.
∗ Phase is around −45 ◦ when ω = 1/RC.
∗ Phase is around −90 ◦ when ω À 1/RC.
Bode D iagram
0
-10
Magnitude (dB)
-20
-30
-40
90
Phase (deg)
60
30
0 1 2 3 4 5
10 10 10 10 10
Frequency (rad/sec)
Figure 3.18: Bode plot for the system transfer function Vo (s) = sRC/(1 + sRC).
Example 3.16 Consider the transfer function Vo (s) = sRL/ (s2 RLC + sL + R) where
R = 1 kΩ, C = 1 µF and L = 1H, express its frequency response including both the
magnitude and the phase responses with Bode Plot.
1 1
Vo (s) = RL × s × = L × s × ¡ L
¢ (3.122)
(s2 RLC + sL + R) s2 LC + s R +1
• The factor L
— Magnitude is a constant and equal to 20 log10 1 = 0dB.
• The factor s
— Magnitude is a straight line that intersects the ω axis (0dB) at ω = 1 and has
a slope of 20dB/decade.
47
Sec 3.8. Bode Plots

L
• The factor 1/(s2 LC + s R + 1)
1 1
— ω ¿ T = √LC
∗ Magnitude is a horizontal line of 0dB.
2T ζω
∗ Phase is − tan−1 1−T 2 ω2 .
1 1
— ω À T = √LC
∗ Magnitude is a straight line of slope −40dB/decade that intersects 0dB
when ω = T1 .
∗ Phase is −180 + tan−1 T2T ζω
2 ω 2 −1 .
B ode D iagram
60
50
Magnitude ( dB)
40
30
20
10
0
90
45
Phase (de g)
-45
-90
1 2 3 4 5
10 10 10 10 10
Frequency (rad/sec)
Figure 3.19: Bode plot for the system transfer function Vo (s) =
sRL/ (s2 RLC + sL + R) .
48
Part II
Devices — Diode, BJT, MOSFETs
49
4
Semiconductor
• Semiconductor
— The number of charge carriers available to conduct current1 is between that of
conductors and that of insulators.
— Semiconductor is basically a pn junction where the p-type silicon contacts with
the n-type silicon.
∗ Different types of silicon are created by implanting different dopings.
4.1 Intrinsic Silicon

• Figure 4.1 shows the 2-D structure of the intrinsic silicon.
— Each atom shares each of its 4 valence electrons with a neighboring atom.
— Atoms are held in their positions by covalent bounds.
∗ Covalent bounds are intact at sufficient low temperature.
· No free electrons are available to conduct current.
∗ Covalent bounds may be broken by thermal ionization.
• Thermal ionization at room temperature (Figure 4.2)
— An electron leaves its parent atom; thus, a positive charge is left with the atom.
∗ The ionization results in free electrons and holes in equal numbers.
∗ At room temperature, the silicon has 1.5 × 1010 carries/cm3 and about
5 × 1022 atoms/cm3 .
· The concentration of free electrons n is equal to the concentration of
free holes p.
n = p = ni (4.1)
· ni is the number of free electrons (or holes) per cm3 in intrinsic silicon
at a given temperature.
n2i = BT 3 e−EG /kT (4.2)

1
The current of 1 ampere is defined as 1 coulomb of electric charge (which consists of about 6.242 ×
18
10 electrons) drifts every second at the same velocity through the imaginary plane through which the
conductor passes.
50
Lecture 4. Semiconductor
Figure 4.1: Two-dimensional representation of the silicon crystal.
Figure 4.2: Electrons and holes generated by thermal ionization.
· B is a material dependent parameter= 5.4 × 1031 for silicon.

· EG is the bandgap energy=1.12 electron volts (eV), representing the
minimum energy required to break a covalent bound and generate an
electron-hole pair.
· k is Boltzmann’s constant = 1.38 × 10−23 joules/kelvin.
· T is absolute temperature in Kelvins = 273 + temperature in ◦ C.
— An electron from a neighboring atom may be attracted and create a new hole.
∗ Ionization rate is equal to recombination rate in thermal equilibrium.
— The process repeats with a hole moves through the silicon and conducts current.
51
Sec 4.1. Intrinsic Silicon
∗ Holes and electrons move through silicon by diffusion and drift mecha-
nisms.
Figure 4.3: Illustration of diffusion mechanism: (a) a bar of intrinsic silicon, and (b) the
hole concentration profile.
• Diffusion mechanism
— Random motion due to thermal agitation.
— Non-uniform concentrations of free electrons and holes cause a net flow of
charge (or diffusion current).
— The current density of the hole diffusion current at any point.
dp
Jp = −qDp (4.3)
dx
∗ Jp in A/cm2 is the current density, i.e., the current per unit area of the
plane perpendicular to the x-axis.2
∗ p is the concentration of free holes.
∗ q is the magnitude of electron charge= 1.6 × 10−19 C.
∗ Dp is the diffusion constant of holes=12cm2 /s.
∗ A negative (dp/dx) results in a positive current in the x direction.
— The magnitude of the electron diffusion current at any point.3
dn
Jn = qDn (4.4)
dx
∗ Jn in A/cm2 is the current density, i.e., the current per unit area of the
plane perpendicular to the x-axis.
∗ n is the concentration of free electrons.
∗ q is the magnitude of electron charge= 1.6 × 10−19 C.
∗ Dn is the diffusion constant of electrons=34cm2 /s.
2
The unit of Jp can be derived from the formulation Jp = −q(charge)Dp (cm2 /s)dp(difference of the
number of the holes/cm3 )/dx(cm) = (charges/s)/cm2 =A/cm2 .
3
To double check.
52
Lecture 4. Semiconductor
∗ A negative (dn/dx) results in a negative current in the x direction.

• Drift mechanism
— Carrier drift occurs when an electric field is applied across a piece of silicon.
— Free electrons and holes are accelerated by electric field and acquire a drift velocity
(superimposed on the velocity of thermal motion).
vdrif t = up E (4.5)
∗ up is the mobility of holes in cm2 /V·s = 480.

∗ E is the strength of electric field in V/cm.
— The current density of holes in A/cm2 .
Jp−drif t = qpup E (4.6)
— The current density of electrons in A/cm2 .
Jn−drif t = qnun E (4.7)
∗ un is the mobility of electrons in cm2 /V·s = 1350.

— The total drift current density in A/cm2 .
Jdrif t= q(pup + nun )E (4.8)
∗ A form of Ohm’s law with the resistivity ρ = 1/q(pup + nun ) in Ω · cm.

• Einstein relationship
Dn Dp
= = VT (4.9)
µn µp
4.2 Doped Silicon

• Doped silicon
— Achieved by introducing a small number of impurity atoms.
• In n-type silicon, the majority of carriers are the negatively charged electrons.
— Achieved by implanting pentavalent impurity (also known as donor).
— In thermal equilibrium
∗ The concentration of free electrons nn0 ' ND .
∗ The product of electron and hole concentrations remains constant.
· pn0 is a function of temperature.
nn0 pn0 = n2i (4.10)
53
Sec 4.2. Doped Silicon
(a) n-type
(b) p-type
Figure 4.4: Doped n-type and p-type semiconductor.
• In p-type silicon, the majority of carriers are the positively charged holes.
— Achieved by implanting trivalent impurity (also known as acceptor).
— In thermal equilibrium
∗ The concentration of free holes pp0 ' NA .
∗ The product of electron and hole concentrations remains constant.
· np0 is a function of temperature.
np0 pp0 = n2i (4.11)
• A piece of p-/n-type silicon is electrically neutral.

— The majority of free carriers are neutralized by bound charges associated with
impurity atoms.
54
5
Diode
A two-terminal device with a nonlinear i − v characteristic.

• Main applications
— Rectifier.
— Generation of DC voltages from AC power.
— Generation of signals of various waveforms.
• Circuit symbol
Figure 5.1: The symbol of diode.
5.1 Physical Structure

• Diode is basically a pn junction device.
5.1.1 The pn Junction Under Open Circuit

• Figure 5.2 shows the pn junction with open circuit.
• Diffusion current ID .
— Generated by the movement of majority carriers.
— Electrons diffuse across the junction from the n side to the p side.
— Holes diffuse across the junction from the p side to the n side.
— The two currents add together to form a diffusion current ID with direction
from p side to n side.
• Depletion region.
— Electrons diffuse across the junction and combine with majority holes.
55
Sec 5.1. Physical Structure
Figure 5.2: (a) The pn junction with no applied voltage (open-circuited terminals). (b)
The potential distribution along an axis perpendicular to the junction.
∗ In p-type silicon, there will be a region depleted of holes and containing

uncovered bound negative charge.
— Holes diffuse across the junction and combine with majority electrons.
∗ In n-type silicon, there will be a region depleted of electrons and contain-
ing uncovered bound positive charge.
— The bound charges on both sides of the depletion region forms a junction built-in voltage.
µ ¶
NA ND
V0 = VT ln (5.1)
n2i
∗ NA and ND are the doping concentrations of the p side and the n side,
respectively.
∗ The built-in voltage V0 for silicon at room temperature is 0.6 ∼ 0.8V .
∗ The electric field acts as a barrier that must be overcome for holes and
electrons to diffuse.
— Depletion regions exist in both sides with equal among of charges.
∗ The depletion layer will extend deeper into the more lightly doped material.
qxp ANA = qxn AND (5.2)

xn NA
=
xp ND
56
Lecture 5. Diode
Figure 5.3: The pn junction excited by a constant-current source I in the reverse direc-
tion. To avoid breakdown, I is kept smaller than IS. Note that the depletion layer widens
and the barrier voltage increases by VR volts, which appears between the terminals as a
reverse voltage.
∗ The width of the depletion region of an open-circuit junction is typically

in the range of 0.1um to 1um.
r
2εs 1 1
Wdep = xn + xp = ( + )V0 (5.3)
q NA ND
• Drift current ISdrif t .

— Achieved by the movement of thermally generated minority carriers.
— Electrons in p-silicon diffuse to the depletion region and got swept to the n-
silicon.
— Holes in n-silicon diffuse to the depletion region and got swept to the p-silicon.
— The two currents add together to form a drift current ISdrif t with direction
from n side to p side.
— ISdrif t depends on temperature instead of the built-in voltage V0 .
• In thermal equilibrium and under open circuit condition, ISdrif t = ID .
— If ID > ISdrif t , the uncovered bound charges will increase and the voltage across
the depletion region will increase. This in turn causes ID to decrease.
— If ISdrif t > ID , the uncovered bound charges will decrease and the voltage
across it will decrease. This in turn causes ISdrif t to decrease.
5.1.2 The pn Junction Under Reverse-Bias

• Figure 5.3 depicts the pn junction with reverse bias.
• Electrons flows from the n-side to the p-side through the external circuit.
— Electrons leaving the n-side cause an increase in the positive bound charges.
— Holes leaving the p-side cause an increase in the negative bound charges.
57
— A increase in the width of, and the charges stored in, the depletion region.
∗ A higher barrier voltage results in the decrease of ID .
— In thermal equilibrium, ISdrif t − ID = I.
• Depletion capacitance
— As the voltage across the pn junction changes, the charges stored in the deple-
tion layer changes.1
— The charges qJ stored in the depletion layer.
∗ A function of VR .
∗ A is the cross-sectional area of the junction.
qJ = qN
= qND xn A
ND NA
= q Wdep A (5.4)
ND + NA
s
ND NA 2εs NA + ND
= q A ( )(V0 + VR )
ND + NA q NA ND
— The depletion capacitance.
dqJ Cj0
Cj = =q (5.5)
dVR 1 + VVR0
∗ The capacitance varies with the bias point.

∗ Cj0 is the value of Cj with no voltage applied.
Figure 5.4: The charge stored on either side of the depletion layer as a function of the
reverse voltage VR.
1
Capacitance C = ∆Q/∆V .
58
Lecture 5. Diode
5.1.3 The pn Junction in the Breakdown Region

• A sufficiently high junction voltage develops and many carriers are created by zener
or avalanche mechanism so as to support any value of reverse current.
— It is not a destructive process as long as the maximum power dissipation is not
exceeded.
• Zener effect
— It occurs when the breakdown voltage VZ < 5V.
— Electric field in the depletion regions increases to a point where it can break
covalent bounds and generate electron-hole pairs.
∗ The holes will be swept into the n side.
∗ The electrons will be swept into the p side.
∗ These electrons and holes constitute a reverse current across the junction.
• Avalanche effect
— It occurs when the breakdown voltage VZ < 7V.
— Minority carriers gain sufficient energy by the electric field to break the covalent
bounds.
∗ The carriers may have sufficient energy to cause other carriers to be liber-
ated in another ionizing collision.
5.1.4 The pn Junction Under Forward Bias Conditions
Figure 5.5: The pn junction excited by a constant-current source supplying a current I

in the forward direction. The depletion layer narrows and the barrier voltage decreases
by V volts, which appears as an external voltage in the forward direction.
• Figure 5.5 depicts the pn junction with forward bias.

• The barrier voltage is reduced since majority carriers neutralize some of the uncov-
ered bound charge.
— Majority carriers are supplied to both sides through the external circuit.
— Holes are injected into the n-side and electrons are injected into the p-side.
59
∗ The concentration of minority carriers at both sides will exceed the thermal
equilibrium, pn0 and np0.
∗ The excess concentration decreases exponentially as one moves away from
the junction.
∗ In the steady state, the concentration profile of excess minority carriers
remains constant.
— Diffusion current ID increases until the equilibrium is achieved with ID −
ISdrif t = I.
Figure 5.6: Minority-carrier distribution in a forward-biased pn junction. It is assumed

that the p region is more heavily doped than the n region.
• Diffusion capacitance
— In steady state, a certain amount of excess minority-carrier charge is stored in
each of the p and n bulk region. If the terminal voltage changes, this charge
will have to change before a steady state is achieved.
τT
Cd = I (5.6)
VT
∗ τ T is the mean transit time of the diode, which is related to the excess
minority carrier life time τ p and τ n .
∗ I is the diode current.
· The diffusion capacitance is negligibly small when the diode is reverse
bias.
• Depletion capacitance
— As the voltage across the pn junction changes, the chargee stored in the deple-
tion layer changes.
Cj = 2Cj0 (5.7)
60
Lecture 5. Diode
5.2 Characteristics
Figure 5.7: The diode i − v relationship with some scales expanded and others com-
pressed.
5.2.1 Forward Bias

• Forward region of operation is entered when the terminal voltage v is positive.
• The i − v curve in forward region is closely approximated by
i = IS (ev/nVT − 1) (5.8)
— IS is called saturation current (or scale current).

µ ¶
Dp Dn
IS = Aqn2i + (5.9)
Lp ND Ln NA
∗ A function of temperature.
· ni is the concentration of electrons in intrinsic silicon, which depends
on the temperature as suggested by Eq. (4.2).
· Generally, IS doubles in value for every 5 ◦ C rise in temperature.
∗ A factor proportional to the cross-sectional area of the diode.
· A is the cross-sectional area of the pn junction.
61
Sec 5.2. Characteristics
— VT is called thermal voltage, which is w 25mV in room temperature (20 ◦ C).
kT
VT = (5.10)
q
∗ k = Boltzmann’s constant = 1.38 × 10−23 joules/kelvin.

∗ T = Absolute temperature in Kelvins = 273 + temperature in ◦ C.
∗ q = Magnitude of electronic charge = 1.60 × 10−19 in coulomb.
— n is a value between 1 and 2
∗ A value depends on the material and physical structure of the diode.
∗ By default, n = 1 unless otherwise specified.
• If i À IS , the i − v curve in forward regions can be further approximated by the
exponential relationship.
i ' IS ev/nVT (5.11)
— The logarithmic form of i − v characteristic.

∗ The v − i curve is a straight line on semilog paper2 with a slope of 2.3nVT .
i i
v ' nVT ln( ) = 2.3nVT log10 ( ) (5.12)
IS IS
— A factor of 10 increases in current leads to the increase of voltage drop by a

factor of 2.3nVT , which is '60mV in room temperature and with n = 1.
I2
V2 − V1 ' nVT ln( ) (5.13)
I1
I2
' e(V2 −V1 )/nVT
I1
• Cut-in Voltage
— A consequence of the exponential i − v relationship.
∗ When v ¿ nVT , the current i is negligible.
∗ When v À nVT , the current i grows exponentially. (Fully Conducting)
∗ Example: Cut-in voltage Vcut in in Figure 5.7 is 0.5V.
— Cut-in voltage varies with temperature for a given diode.
• Fully Conducting
— The voltage v is greater than Vcut in and the current i grows exponentially.
— Voltage drop varies with temperature for a given diode.
5.2.2 Reverse Bias

• Reverse-bias is entered when the terminal voltage v is made negative.
2
The vertical axis is a linear axis for v and the horizontal axis is a log axis for i.
62
Lecture 5. Diode
Figure 5.8: The temperature dependency of the diode forward characteristic.
• The reverse current i approximates −Is .

— The term ev/nVT in Eq. (5.8) becomes negligible as v −→ −∞.
— A function of temperature.
∗ The reverse current doubles in value for every 10 ◦ C rise in temperature.
— A large part of reverse current is due to leakage effects.
∗ Leakage currents are proportional to the junction area.
∗ Real diodes exhibit reverse currents that are much larger than Is .
5.2.3 Breakdown Region

• Breakdown region is entered when the reverse voltage exceeds breakdown voltage
VZK .
• The reverse current i increases rapidly with very small increase in voltage drop.
— A good property for voltage regulation.
5.3 Model
5.3.1 Large Signal Model
Ideal Diode
• Forward biased
— Short circuit with zero voltage drop when v > 0.
• Reverse biased
— Open circuit with zero current when v < 0.
Exponential Model
• The most accurate description of the diode operation in forward region.
63
Sec 5.3. Model
Table 5.1: Comparison of the models in the diode forward region.
Model i − v Graph Equivalent Circuit
Ideal
Exponential
Piecewise-linear
Constant Voltage Drop
Small Signal
64
Lecture 5. Diode
Figure 5.9: The i-v characteristic of the ideal diod.
(a) Reverse Bias (b) Forward Bias

Figure 5.10: The characteristic of the ideal diod with positive and negative voltages
applied.
• The most difficult one to use due to nonlinear nature.

• Pencil-and-paper solutions: (1) graphical analysis, and (2) iterative analysis.
Example 5.1 Given the circuit to be analyzed as in Figure 5.11, find out the ID and VD
using graphical analysis.
Figure 5.11: A simple circuit used to illustrate graphical analysis with exponential
model.
65
Sec 5.3. Model
1. Assume VDD is greater than 0.5V so that the diode operates in forward bias region.
ID = IS eVD /nVT (5.14)
2. Further, writing a Kirchhoff loop equation, we can obtain the other equation that
governs the circuit operation.
VDD − VD
ID = (5.15)
R
3. Graphical analysis is performed by plotting Eq. (5.14) and Eq. (5.15) on the i − v
plane. The solution is the coordinate of the intersection of the two lines.
• The line specified by Eq. (5.15) is also known as the load line.
Figure 5.12: Graphical analysis for the circuit given in Figure 5.11.
Piecewise Linear Model
• A simpler model easier for analysis.

(
0 if vD < VD0
iD (vD ) = . (5.16)
(vD−VD0 )/γ D if vD ≥ VD0
Constant Voltage Drop Model
• The simplest model for analysis.

— Forward-conducting diode exhibits a voltage drop VD of 0.7V .
— The model frequently employed in the initial phase of analysis and design.
66
Lecture 5. Diode
Figure 5.13: The piecewise linear model of the diod forward i-v characteristic.
Figure 5.14: The constant voltage drop model of the diod forward i-v characteristic.
5.3.2 Small Signal Model

• Small signal model is used for the applications in which a diode is biased to operate
in the forward region and a small ac signal is superimposed on the dc quantities.
• Small signal analysis
— Determine the dc bias point (or quiescent point) using the large signal models.
∗ The constant voltage drop model is commonly used.
— Determine the small signal operation around the dc bias point by modeling the
diode with a resistance.
∗ The resistance is the slope of the tangent to the exponential i − v curve.
Example 5.2 Consider the circuit in Figure 5.15, where the dc voltage VD is applied to
the diode and a time varying signal vd (t) is further superimposed to the dc voltage VD ,
and the corresponding graphical representation, find out the iD (t) and vD (t) of the diode.
1. The dc operation point of the diode can be found as follows:
ID = Is eVD /nVT (5.17)
67
Sec 5.3. Model
Figure 5.15: Circuit for the development of the diode small signal model and the corre-
sponding graphical representation.
2. When the small signal vd (t) is applied, the instantaneous diode current iD (t) will be
iD (t) = Is e(VD +vd (t))/nVT

= Is eVD /nVT × evd (t)/nVT (5.18)
= ID × evd (t)/nVT
3. If the amplitude of the signal vd (t) is kept sufficiently small, the exponential term in
Eq. (5.18) can be expanded in a series.3 The small signal approximation is obtained
by truncating the series after the first two terms.
µ ¶
vd (t)/nVT vd (t)
iD (t) = ID × e ' ID × 1 + (5.19)
nVT
• Valid for signals whose amplitudes are sufficiently small, e.g., 10mV for the
case n = 2 and 5mV for n = 1.4
• The ac current in Eq. (5.19), defined as follows, is proportional to the signal
vd (t).
vd (t)
id (t) ≡ ID × (5.20)
nVT
• The diode small-signal resistance (or incremental resistance)5 , vd (t)/id (t) =
3
The fourier expansion of ex =.
4
The magnitude is approximately (1/5) × nVT .
5
Only the ac component is considered.
68
Lecture 5. Diode
nVT /ID , is inverse proportional to the bias current ID .
Conclusion 5.3 For diode, the small signal analysis can be performed separately from
the dc analysis.
• After the dc analysis is performed, the small signal equivalent circuit is obtained
by eliminating all dc sources (i.e., short-circuiting dc voltage sources and open-
circuiting ac current sources.) and replacing the diode with its small-signal resistance.
Example 5.4 Consider the circuit shown in Figure 5.16 (a) for the case in which R =
10K Ω. The power supplier V + has a dc value of 10V on which it is superimposed a 60Hz
sinusoid of 1-V peak amplitude. Calculate the dc voltage of the diode and the amplitude of
the sine-wave signal appearing across it. Assume the diode to have a 0.7-V drop at 1-mA
current and n=2.
Figure 5.16: Example of separating small signal analysis from dc analysis.
1. Consider dc signal only as in Figure 5.16 (b), the dc current of the diode is
10 − 0.7
ID = = 0.93mA
10
2. Since the dc current is very close to 1mA, the diode voltage will be very close to
the assumed 0.7V . At this quiescent point, the diode incremental resistance γ d is
nVT 2 × 25
γd = = = 53.8 Ω
ID 0.93
3. Now we remove the dc source and replace the diode with incremental resistance as
in Figure 5.16 (c). Then, the peak amplitude of vd can be calculated as follows.
γd
vd (peak) = vs × = 5.35mV.
R + γd
69
Sec 5.3. Model
4. As compared with nVT = 50mV, the peak amplitude of vd is quite small. The use
of the small-signal model is justified.
5.3.3 Circuit Analysis with Diodes

Analysis of a circuit including diodes normally goes through the following procedure.
• Make plausible assumptions.
• Apply linear circuit analysis.
• Check solution and repeat the process if necessary.
Example 5.5 Resolve the current I and the voltage V for the two circuits in Figure ??.
Case A
1. Diodes D1 and D2 are assumed to be forward biased and replaced with short circuits.
It follows that VB = 0 and V = 0. Consequently,
10 − 0
ID2 = = 1mA.
10
2. Further, writing a node equation at the node B.
0 − (−10)
I +1= ⇒ I = 1mA.
5
3. Thus, both D1 and D2 are conducting as originally assumed.
Case B
70
Lecture 5. Diode
1. Diodes D1 and D2 are assumed to be forward biased and replaced with short circuits.
It follows that VB = 0 and V = 0. Consequently,
10 − 0
ID2 = = 2mA.
5
2. Further, writing a node equation at the node B.
0 − (−10)
I +2= ⇒ I = −1mA.
10
3 Since this is not possible, the assumption is invalid. To obtain a consistent solution,
the assumption is modified in such a way that D1 is off. As a result,
10 − (−10)
ID2 = = 1.33mA.
15
V = VB = −10 + 1.33 × 10 = 3.3V.
5.4 Special Diodes

5.4.1 Zener diode
Figure 5.17: Symbol of Zener diode and its i-v characteristics.
• Zener diodes are specifically designed to operate in breakdown region.

— The steep i − v characteristic is ideal for voltage regulators6 .
6
Voltage regulators need to provide constant dc output voltages in the face of changes in load current
and system power-supply voltage.
71
Sec 5.5. Applications
Figure 5.18: Model for the Zener diode.
• Parameters of Zener diodes.

— The voltage VZ across the diode at a testing current IZT . (The operating point)
— The incremental resistance γ z at the operation point.
— The knee current IZK .
∗ The i − v curve for currents greater than IZK is almost a straight line.
• Model of Zener diodes in breakdown region is specified in Eq. (5.21).
— Applied for IZ > IZK and VZ > VZ0 .
— VZ0 is the intersection of the straight line of slope 1/γ z and the voltage axis.
VZ = VZ0 + γ z IZ (5.21)
5.4.2 Switching Controlled Rectifier (SCR)
5.4.3 LED/Varactors
5.5 Applications
5.5.1 Regulator
Example 5.6 Use of the Zener diode as a Shunt Regulator which appears in parallel
with the load. The 6.8-V Zener diode in Figure 5.19 is specified to have VZ = 6.8V at
IZ = 5mA,γ Z = 20 Ω, and IZK = 0.2mA.The supply voltage V + is normally 10V but can
vary by ±1V .
1. From Eq. (5.21) and the given conditions, VZ0 can be derived as 6.7V .
2. The Vo with no loading.
10 − 6.7
IZ = I = = 6.35mA
0.5 + 0.2
Vo = VZ0 + γ Z × IZ = 6.83V
72
Lecture 5. Diode
Figure 5.19: Use of Zener diode as a Shut Regulator.
3. The line regulation (∆Vo /∆V + ) due to the ±1V change of power supply.
γZ
∆Vo = ∆V + ×
R + γZ
∆Vo γZ 20
= = = 38.5mV /V
∆V + R + γZ 500 + 20
4. The load regulation (∆Vo /∆IL ) as a load resistor draws a current IL = 1mA.
• Assume the total current I does not change significantly when the load is
connected.
∆Vo = γ Z × ∆IZ = 20 × −1 = −20mV.

∆Vo
= −20mV /mA
∆IZ
5. The change of Vo when a load resistor RL = 2K Ω is connected.

• Assume the total current I does not change significantly when the load is
connected.
• The approximation of the load current is as follows and the change of Vo can
be obtained accordingly.
6.8
∆IZ = = 3.4mA.
2
∆Vo = γ Z × ∆IZ = 20 × −3.4 = −68mV.
• The accurate number from circuit analysis is ∆Vo = −70mV.

6. The change of Vo when a load resistor RL = 0.5K Ω is connected.
• It is impossible that the load would draw a current of 6.8/0.5 = 13.6mA. Thus,
73
the diode must be cut-off. Accordingly, the Vo can be obtained as follows:
R
Vo = V + × = 5V.
R + RL
7. The minimum value of RL for which the diode still operates in the breakdown region.
• The minimum voltage supply is around 9V . At this point, the lowest current
supplied is (9 − 6.7)/0.5 = 4.6mA and thus the load current is 4.6 − 0.2 =
4.4mA. The corresponding value of RL = 6.7/4.4 = 1.5K Ω.
5.5.2 Rectifier
• A diode rectifier is an essential building block of the dc power supply.
• Figure 5.20 depicts the block diagram of the dc power supply.
— Power transformer
∗ To step the line voltage down to the required value.
∗ To minimize the risk of electric shock by providing electrical isolation be-
tween the equipment and the power line.
— Diode rectifier
∗ Convert input sinusoid to a unipolar output.
∗ Two parameters must be specified in selecting the diodes.
· The largest current the diode is expected to conduct.
· The largest reverse current that is expected to withstand without
breakdown. (Peak inverse voltage)
— Filter
∗ Convert pulsating waveform to a constant output.
— Voltage regulator
∗ To reduce the ripple
∗ To stabilize the dc output as the load current changes.
Figure 5.20: Block diagram of a dc power supply.
74
Lecture 5. Diode
Half-Wave Rectifier
• Utilize alternate half-cycles of the input sinusoid.

• Figure 5.21 shows an example of half-wave rectifier.
— PIV= VS .
— It may not function properly when the input signal is small.
(
0 if VS < VD0
vo = R
. (5.22)
R+γ D
× (VS − VD0 ) if VS ≥ VD0
Figure 5.21: Circuit of half-wave rectifier.
Full-Wave Rectifier
• Utilize both halves of the input sinusoid.

• Figure 5.22 shows an example of full-wave rectifier.
— When the input voltage is positive, both of the signals vS will be positive.
∗ D1 will conduct and D2 will be reverse biased.
— When the input voltage is negative, both of the signals vS will be negative.
∗ D1 will be reverse biased and D2 will conduct.
— vo is unipolar since the current always flows through R in the same direction.
— PIV= 2VS − VD .
— A center-tapped transform is required.
• Figure 5.23 shows another implementation of full-wave rectifier.
— When the input voltage is positive, the signals vS will be positive.
∗ D1 and D2 will conduct; D3 and D4 will be reverse biased.
— When the input voltage is negative, the signals vS will be negative.
75
Figure 5.22: Circuit of full-wave rectifier using center-tapped transformer.
∗ D3 and D4 will conduct; D1 and D2 will be reverse biased.

— vo is unipolar since the current always flows through R in the same direction.
— PIV= vo + vD2 (forward)= VS − 2VD + VD = VS − VD .
— Advantages
∗ PIV is about half the value for the center-tapped implementation.
∗ A center-tapped transform is not required.
∗ Less turns are required for the secondary winding of the transformer.
Figure 5.23: Circuit of the bridge rectifier.
The Peak Rectifier
• The peak rectifier reduces the variation of output voltage by introducing a capacitor.
• Figure 5.24 shows the circuit of the peak rectifier.
— The capacitor charges to the peak of the input VP .
— The diode cuts off and the capacitor discharges through the load R.
76
Lecture 5. Diode
Figure 5.24: Circuit of the peak rectifier.
∗ The output vo (t) during the discharge.7
vo (t) = VP e−t/RC (5.23)
∗ The voltage drop Vγ due to the discharge.8
VP − Vγ ' VP e−T /RC

T
⇒ Vγ = VP (1 − e−T /RC ) ' VP (5.24)
RC
· To keep Vγ small, we must select a capacitor C so that RC À T.

∗ The alternative expression of Vγ .
T IL
Vγ ' VP = (5.25)
RC fC
· IL = VP /R is the load current when Vγ is small.

· f = 1/T is the frequency of the voltage supplier.
· To keep Vγ small, we can either select a large capacitor C or increase
the frequency of the voltage supplier.
— The discharge continues until vI exceeds the capacitor voltage.
7
The node equation when the diode is cut off: C dvdt
o (t)
+ vo (t)
R = 0.
8 x
e =
77
5.5.3 Limiting
• Limiter (also known as clipper) limits the voltage between the two output terminals.
Figure 5.25: Transfer characteristic for a limiter circuit.
• Eq. (5.26) and Figure 5.25 show the transfer function of limiter.
⎧
⎪
⎨ L− if vI < L− /K
vo = KvI if L− /K ≤ vI ≤ L+ /K . (5.26)
⎪
⎩
L+ if vI > L+ /K
• Diode can be combined with resistors to implement limiters.

— Figure 5.26 (a) and (b) are single limiters.
∗ Single limiter works for either positive or negative peak.
— Figure 5.26 (c) is a double limiter.
∗ Double limiter works for both positive and negative peaks.
— Figure 5.26 (d) shows that the threshold and saturation current can be con-
trolled by using strings of diodes and/or by connecting a dc voltage in series
with the diode.
— Figure 5.26 (e) shows another double limiter using double-anode Zener.
5.5.4 Clamping
• Diodes can be used for the circuit of dc restorer (also known as clamped capacitor).
• Figure 5.27 shows an example of dc restorer with no load.
— When vI = −6V, the capacitor will charge to a voltage vC .
∗ vC is equal to the magnitude of the most negative peak, i.e., 6V.
∗ The polarity of vC is indicated as in Figure 5.27.
78
Lecture 5. Diode
Figure 5.26: A varity of basic limiting circuits.
∗ The diode is turned off and the capacitor retains its voltage indefinitely.
— When vI = 4V, the output vC = vI + vC = 10V.
• Figure 5.28 shows the example of dc restorer with a load resistor R.
— As t0 < t < t1 , the output voltage falls exponentially with time constant RC.
— At t1 , the input decreases by Va and the output attempts to follow.
∗ The diode conduct heavily and quickly discharge the capacitor.
— At the end of the period t1 to t2 , the output voltage is around −0.5V .
Figure 5.27: The clamped capacitor or dc restorer with a square-wave input and no
load.
79
Figure 5.28: The dc restorer with a load resistor R.
5.5.5 Digital Logic

• Diodes can also be used for logic gates as shown in Figure 5.29.
Figure 5.29: Digital logic gates: (a) OR gate; (b) AND gate. (Positive logic system)
80
6
MOS Field-Effect Transistors (MOSFETs)
• A three-terminal device that uses the voltages of the two terminals to control the
current flowing in the third terminal.
— The basis for amplifier design.
— The basis for switch design.
— The basic element of integrated circuits.
• Applications
— Signal amplification.
— Digital logic.
— Memory, and so on.
• Circuit symbol
Figure 6.1: (a) Circuit symbol for the n-channel enhancement-type MOSFET. (b) Mod-
ified circuit symbol. (c) Simplified circuit symbol.
Figure 6.2: (a) Circuit symbol for the p-channel enhancement-type MOSFET. (b) Mod-
ified circuit symbol. (c) Simplified circuit symbol.
81
Sec 6.1. Structure
Figure 6.3: Physical structure of the enhancement-type NMOS transistor.
6.1 Structure
6.1.1 Physical Structure
• Enhancement-type NMOS transistor (Figure 6.3)
— Structure
∗ Body (B)
· The device is fabricated on a p-type substrate.
∗ Source (S) and Drain (D)
· Two heavily doped n-type regions.
· Charges carriers are electrons.
· Current flows from drain to source.
∗ Gate electrode (G)
· A thin layer of silicon dioxide (SiO2 ), which is an electrical insulator.
· Polysilicon is deposited on top of the oxide layer.
∗ Mental contacts are made to the regions of source, drain, and body.
— The substrate forms pn-junctions with the source and drain regions.
∗ The pn-junctions are reverse-biased.
· The drain (D) is at a positive voltage relative to the source (S).
· The pn-junctions is cut-off by connecting the body (B) to the source (S).
· The MOSFET is thus treated as a three-terminal device.
• Enhancement-type PMOS transistor
— Structure
∗ Body (B)
· The device is fabricated on a n-type substrate.
∗ Source (S) and Drain (D)
· Two heavily doped p-type regions.
82
Lecture 6. MOS Field-Effect Transistors (MOSFETs)
· Charges carriers are holes.

· Current flows from source to drain.
∗ Gate electrode (G)
· A thin layer of silicon dioxide (SiO2 ), which is an electrical insulator.
· Polysilicon is deposited on top of the oxide layer.
∗ Mental contacts are made to the regions of source, drain, and body.
— The source and drain regions form pn-junctions with the substrate.
∗ The pn-junctions are reverse-biased.
· The source (S) is at a positive voltage relative to the drain (D).
· The pn-junctions is cut-off by connecting the body (B) to the drain (D).
· The MOSFET is thus treated as a three-terminal device.
— NMOS transistor is smaller and faster than PMOS transistor.
— PMOS operates in the same manner as NMOS excepts that vGS and vDS are
negative and the threshold voltage Vt is negative.
• Complementary MOS (CMOS, Figure 6.4)
— CMOS employs MOS transistors of both polarities.
∗ NMOS is implemented directly in p-type substrate.
∗ PMOS is fabricated in a created n region, known as n well.
∗ The two devices are isolated by a thick region of SiO2 .
— CMOS is widely used in both analog and digital circuits and virtually replace
designs based on NMOS alone.
6.2 Characteristics of NMOS Transistor

• Figure 6.5 depict the iD − vDS characteristic of a NMOS transistor.
6.2.1 Cut-off Region (vGS < Vt )

• When vGS < Vt , the transistor is turned off.
— No current flow from drain to source.
— As vGS = 0, two back-to-back diodes exists in series between source and drain.
• In reality, for values of vGS smaller than Vt but close to Vt , a small drain current
flows.
— The subthreshold current is an exponential function of vGS .
6.2.2 Triode (vGS > Vt , 0 < vDS < vGS − Vt )

• vGS > 0 (refer to Figure 6.6).
— Holes in substrate.
∗ The holes are pushed downward, leaving behind a carrier-depletion region.
83
Sec 6.2. Characteristics of NMOS Transistor
Vdd
n-well
Metal
Gate
Source (P+)
Drain (P+)
Input
Output
Source (n+)
Drain (n+)
Ground
Figure 6.4: Corss-section of a CMOS integrated circuit and the layout mask (Courtesy
of NCTU Si2 Lab).
84
Figure 6.5: iD − vDS characteristic for a NMOS transistor .
Figure 6.6: The enhancement-type NMOS with vGS > VT and with a small vDS .
∗ The depletion region is populated by the bound negative charge.

— Electrons in drain and source.
∗ Positive gate voltage attracts electrons from the n+ source and drain.
∗ Electrons accumulate near the surface of the substrate under the gate and
form a ”channel” connecting the source and the drain.
— The threshold voltage Vt is the value of vGS at which a sufficient number of
electrons form a channel.
• The iD − vDS curve in triode region (vGS > Vt ) is specified by Eq. (6.1).
∙ ¸
W 1 2
iD = kn0 (vGS − Vt )vDS − vDS (6.1)
L 2
— ∗ L is the length of the channel.
85
∗ W is the width of the channel.

∗ kn0 is a constant (process transconductance parameter) determined by the
process technology.
— Drain current is proportional to the aspect ratio W/L.
— For a given process technology, there is a minimum channel length Lmin and a
minimum channel width Wmin .
• vDS ' 0 (refer to Figure 6.6).
— vDS causes a current iD to flow through the induced n channel from drain to source.
— iD depends on the density of electrons in the channel, which in turn depends
on vGS .
— The transistor acts like a resistor with the resistance controlled by vGS .
∗ The conductance of the channel is proportional to the excess gate voltage
(vGS − Vt ), as shown in Figure 6.7 and Eq. (6.2).
∙ ¸−1
−1 ∂iD
rDS = gDS =
∂vDS
∙ ¸−1
0 W
= kn [(vGS − Vt ) − vDS ] (6.2)
L
∙ ¸−1
0 W
' kn (vGS − Vt )
L
vDS
'
iD
Figure 6.7: The iD − vDS characteristics of the MOSFET with small vDS .
• 0 < vDS < vGS − Vt (refer to Figure 6.8).

— The voltage between the gate and points along the channel decreases from vGS
at the source to vGS − vDS at the drain, as shown in Figure 6.8.
∗ Channel becomes more tapered when vDS is increased.
∗ Resistance of channel increases when vDS is increased.
86
· The iD − vDS curve bends as shown in Figure 6.5.
(a)
(b)
Figure 6.8: The change of channel shape when the drain-source voltage is increased.
6.2.3 Saturation (vGS > Vt , vDS > vGS − Vt )

• As vDS = vGS − Vt , the channel pinches-off.
— The drain current iD can be obtained by substituting vDS = vDSsat = vGS − Vt
in Eq. (6.1).
W1
iD = kn0 (vGS − Vt )2 (6.3)
L2
— The drain current iD is independent of the drain voltage vDS (in a first-order
approximation) and is determined by the gate voltage vGS .
∗ Ideally, the Large-Signal model for NMOS is an ideal current source con-
trolled by vGS .
• Finite output resistance
— In practice, increasing vDS beyond vDSsat does affect the channel.
— Channel-length modulation (refer to Figure 6.10)
∗ As vDS is increased, the depletion region increases and the pinch-off point
moves toward the source.
87
Figure 6.9: The iD − vGS characteristic for a NMOS transistor in saturation region.
∗ Eq (6.4) shows the iD −vDS characteristic with channel-length modulation.
1 0 W
iD = kn (vGS − Vt )2
2 L − 4L
1 0W 4L
' kn (1 + )(vGS − Vt )2
2 L L
1 0W λ0 vDS
= kn (1 + )(vGS − Vt )2 (6.4)
2 L L
1 0W
= k (vGS − Vt )2 (1 + λvDS )
2 nL
∗ λ is a process technology parameter and can be obtained as in Figure 6.11.

· VA is referred to as the Early voltage.
· VA typically falls in the range of 0.9V − 9V.
1 0W
iD ' kn (vGS − Vt )2 (1 + λvDS ) = 0
2 L
1 1
⇒ λ=− = (6.5)
vDS VA
Figure 6.10: As vDS is increased beyond vDSsat , the pinch-off point is moved toward the
source.
88
Figure 6.11: Effect of vDS on iD in saturation region.
• — Equivalent output resistance ro

∗ Inversely proportional to the drain current ID without considering Early
effect.
1 W
iD = kn0 (vGS − Vt )2 (1 + λvDS ) = ID (1 + λvDS ) (6.6)
2 L
∗ Controlled by (vGS − Vt ).
∆vDS 1 VA
ro = = =
∆iD λID ID
VA
= (1 + λvDS )
iD
VA vDS
= + (6.7)
iD iD
— Figure 6.12 shows the large signal equivalent model of the NMOS in saturation region.
Figure 6.12: Large signal equivalent model of the NMOS in saturation region.
• Figure 6.13 recaps the relative levels of terminal voltage of the NMOS transistor for
operation in different regions.
89
Sec 6.3. Characteristics of PMOS Transistor
Figure 6.13: The relative levels of the terminal voltages of the NMOS transistor for
operation in the triode region and in the saturation region.
6.3 Characteristics of PMOS Transistor
Figure 6.14: The PMOS with voltages applied and the directions of current flow indi-
cated.
• The threshold voltage Vt (relative to the source terminal) is negative.

• Cut-off region
— The gate voltage vGS (relative to the source terminal) is greater than Vt .
vGS > Vt = − |Vt |

⇒ vSG < |Vt | (6.8)
• Triode region
— To induce a channel, we apply a gate voltage that is more negative than Vt .
vGS ≤ Vt = − |Vt |
⇒ vSG ≥ |Vt | (6.9)
— To prevent the channel from pinch-off, drain voltage vDS must be higher than
90
Figure 6.15: The relative levels of the terminal voltages of the PMOS.
gate voltage vGS by at least |Vt |.
vDS > vGS − Vt = vGS + |Vt |

⇒ vSD ≤ vSG − |Vt | (6.10)
— The iD − vDS characteristic is exactly the same as the NMOS.

∗ vDS , vGS ,and Vt are negative values.
∙ ¸
W 1 2
iD = kp0 (vGS − Vt )vDS − vDS
L 2
∙ ¸
0W 1 2
= kp (vSG − |Vt |)vSD − vSD (6.11)
L 2
• Saturation
— To operate in saturation, drain voltage vDS must be lower than (vGS + |Vt |) .
vDS ≤ vGS − Vt = vGS + |Vt |

⇒ vSD > vSG − |Vt | (6.12)
— The iD − vDS characteristic is exactly the same as the NMOS.

∗ λ, vDS , vGS ,and Vt are negative values.
1 0W
iD ' kp (vGS − Vt )2 (1 + λvDS )
2 L
1 0W
= k (vSG − |Vt |)2 (1 + |λ| vSD ) (6.13)
2 pL
• Figure 6.15 recaps the relative levels of terminal voltage of the PMOS transistor for
operation in different regions.
6.3.1 Body Effect

• In integrated circuits, the substrate (body) is common to many MOS transistors.
91
• To maintain cut-off for all the substrate-to-channel junctions

— The body is connected to the most negative power supply in an NMOS circuit.
— The body is connected to the most positive power supply in a PMOS circuit.
• The reverse bias voltage vSB widens the depletion regions and decreases the depth
of the channel.
— The increasing of vSB causes an increase in the threshold voltage Vt .
∗ Vt0 is the threshold voltage with vSB = 0.
∗ γ is the body effect parameter.
∗ 2φ is the surface potential parameter.
∙q ¸
¡ ¢ q
Vt = Vt0 + γ 2φf + VSB − 2φf (6.14)
• Body Effect (Back-Gate Effect)

— The body acts as a second gate.
— When vGS is kept constant, vSB ↑ ⇒ Vt ↑ ⇒ iD ↓.
6.3.2 Internal Capacitances

• Device has internal capacitances
— Cgs : Gate to Source capacitance.
∗ The source diffusion extends slightly under the gate. (Overlap capacitance)
— Cgd : Gate to Drain capacitance.
∗ The drain diffusion extends slightly under the gate. (Overlap capacitance)
— Cgb : Gate to Body capacitance.
∗ The gate electrode forms a parallel plate capacitor with channel.
— Csb : Source to Body capacitance.
∗ Depletion capacitance of the reverse-biased pn junction (Body to Source).
— Cdb : Drain to Body capacitance.
∗ Depletion capacitance of the reverse-biased pn junction (Body to Drain).
• Gate capacitive effect (Cgs , Cgd , Cgb )
— Triode
∗ The gate-channel capacitance is W LCox
∗ Model
1
Cgs = Cgd = W LCox + W Lov Cox (6.15)
2
— Saturation
∗ The gate-channel capacitance is 23 W LCox .
92
∗ Model
2
Cgs = W LCox + W Lov Cox
3
Cgd = W Lov Cox (6.16)
— Cut-off
∗ The gate-body capacitance is W LCox .
∗ Model
Cgs = Cgd = W Lov Cox

Cgb = W LCox (6.17)
• Depletion layer capacitance (Csb , Cdb )

— Junction capacitances from the bottom side and the side walls of the diffusion.
— Source to body depletion capacitance Csb (assume small signal)
∗ Csb0 : The capacitance with zero voltage.
∗ V0 : Junction built-in voltage.
Csb0
Csb = q (6.18)
1 + VVSB
0
— Source to body depletion capacitance Cdb (assume small signal)

∗ Cdb0 : The capacitance with zero voltage.
∗ V0 : Junction built-in voltage.
Cdb0
Cdb = q (6.19)
1 + VVdB
0
• Capacitance effects must be considered when the MOSFET is operated at high

frequency.
6.3.3 Temperature Effect

• iD decreases as temperature increases.
• Both Vt and k0 are temperature sensitive.
— Vt decreases by about 2mV for every 1 ◦ C rise in temperature.
— k0 decreases with temperature and its effect is a dominant one.
6.3.4 Summary
• The saturation region is used for the operation of amplifier.
93
• The triode and cut-off regions are used for the operation of switch.
94
7
Bipolar Junction Transistor (BJT)
• A three-terminal device that uses the voltage of the two terminals to control the
current flowing in the third terminal.
— The basis for amplifier design.
— The basis for switch design.
— The basic element of high speed integrated digital and analog circuits.
• Applications
— Discrete-circuit design.
— Analog circuits.
∗ High frequency application such as radio frequency analog circuit.
— Digital circuits.
∗ High speed digital circuit such as emitter coupled circuit (ECC).
∗ Bi-CMOS (Bipolar+CMOS) circuits that combines the advantages of MOS-
FET and bipolar transistors.
· MOSFET: high-input impedance and low-power.
· Bipolar transistors: high-frequency-operation and high-current-driving
capabilities.
• Circuit symbol
— The arrowhead on the emitter implies the polarity of the emitter-base voltage.
∗ NPN: vBE > 0.
∗ PNP: vEB > 0.
7.1 Structure
7.1.1 NPN Transistor
• Figure 7.2 depicts a simplified NPN transistor.
— Emitter (E): heavily doped n-type region.
— Base (B): lightly doped p-type region.
— Collector (C): heavily doped n-type region.
— Two diodes connected in series with opposite directions.
∗ EBJ: Emitter-Base junction.
95
Sec 7.1. Structure
Figure 7.1: Circuit symbols of (a) NPN and (b) PNP transistors.
Figure 7.2: A simplified structure of the NPN transistor.
∗ CBJ: Collector-Base junction.

• Figure 7.3 shows the cross-section view of an NPN transistor.
— The NPN transistor has asymmetrical structure.
— α and β parameters are different for forward active and reverse active modes.
• Modes of operations
— Cutoff
∗ EBJ (Reverse), CBJ (Reverse)
∗ vBE < 0, vCB > 0.
— Active (refer to Figure 7.7)
∗ EBJ (Forward), CBJ (Reverse)
∗ vBE > 0, vCB > 0.
— Reverse Active
∗ EBJ (Reverse), CBJ (Forward)
∗ vBE < 0, vCB < 0.
— Saturation
∗ EBJ (Forward), CBJ (Forward)
∗ vBE < 0, vCB < 0.
96
Lecture 7. Bipolar Junction Transistor (BJT)
Figure 7.3: Cross-section of an NPN BJT.
• Figure 7.4 shows the voltage polarities and current flow in the NPN transistor biased
in the active mode.
Figure 7.4: Voltage polarities and current flow in the NPN transistor biased in the active
mode.
7.1.2 PNP Transistor
Figure 7.5: A simplified structure of the PNP transistor.
• Figure 7.5 depicts a simplified PNP transistor.

— Emitter (E): heavily doped p-type region.
97
Sec 7.2. Operations of NPN Transistor
— Base (B): lightly doped n-type region.

— Collector (C): heavily doped p-type region.
— Two diodes connected in series with opposite directions.
∗ EBJ: Emitter-Base junction.
∗ CBJ: Collector-Base junction.
• Modes of operations
— Cutoff
∗ EBJ (Reverse), CBJ (Reverse)
∗ vEB < 0, vBC < 0.
— Active (refer to Figure 7.7)
∗ vEB > 0, vBC > 0.
— Reverse Active
∗ EBJ (Reverse), CBJ (Forward)
∗ vEB < 0, vBC < 0.
— Saturation
∗ EBJ (Forward), CBJ (Forward)
∗ vEB > 0, vCB > 0.
• Figure 7.6 shows the voltage polarities and current flow in the PNP transistor biased
in the active mode.
Figure 7.6: Voltage polarities and current flow in the PNP transistor biased in the active
mode.
7.2 Operations of NPN Transistor

7.2.1 Active Mode
• Emitter-Base Junction
98
Figure 7.7: Current flow in an NPN transistor to operate in the active mode.
— Forward bias, vBE > 0.

— Electrons in the emitter region are injected into the base causing a current iE1 .
— Holes in the base region are injected into the emitter region causing a current
iE2 .
∗ Generally, iE1 >> iE2 .
iE (t) = iE1 + iE2 (7.1)
• Base region
— Figure 7.8 depicts the concentration of minority carriers (electrons) in the base
region.
— Tapered concentration causes the electrons to diffuse through the base region
toward the collector.
∗ Some of the electrons may combine with the holes causing a concave shape
of the profile.
∗ The recombination process is quite small due to lightly doped and thin
base region.
np (0) = np0 evBE /VT (7.2)
— Diffusion current In (flowing from right to the left) is proportional to the slope
of the concentration profile.
∗ AE is the cross-sectional area of the base-emitter junction.
∗ Dn is the electron diffusivity in the base region.
∗ W is the effective width of the base.
dnp (x) np (0)

In = AE qDn = −AE qDn (7.3)
dx W
99
• Collector-Base Junction
— Reverse bias, vBC > 0.
— The electrons near the collector side are swept into the collector region causing
zero concentration at the collector side.
Figure 7.8: Profiles of minority carrier concentrations in the base and in the emitter of
an NPN transistor.
• Collector current, iC .
— Most of the diffusing electrons will reach the collector region, i.e., iC = −In .
∗ Only a very small percentage of electrons are recombined with the holes
in the base region.
— As long as vCB > 0, iC is independent of vCB .
∗ The electrons that reach the collector side of the base region will be swept
into the collector as collector current.
iC = −In
np (0)
= AE qDn
W
AE qDn np0 vBE /VT
= e (7.4)
W
AE qDn n2i vBE /VT
= e
W NA
= IS evBE /VT
— Saturation current (also known as scale current) IS = (AE qDn n2i )/ (W NA )

∗ A strong function of temperature.
∗ Proportional to the cross-sectional area of the base-emitter junction.
∗ Inverse proportional to the base width W.
• Base current iB
100
— iB is composed of two currents.

∗ The holes injected from the base region into the emitter region.
AE qDp n2i vBE /VT

iB1 = e (7.5)
ND Lp
∗ The holes that have to be supplied by the external circuit due to the
recombination.
· τ b is the average time for a minority electron to recombine with a
majority hole.
1 AE qW n2i vBE /VT
iB2 = e (7.6)
2 τ b NA
— Formulation of iB in terms of iC .
∗ IS is the
³ saturation current´ of iC (refer to Eq.(7.4))
Dp NA W 2
∗ β = 1/ Dn ND Lp + 12 DWn τ b is a constant (normally in the range 50 ∼ 200)
for a given transistor.
∗ β is mainly influenced by (1) the width of the base region, and (2) the
NA
relative dopings of the base region and the emitter region N D
.
· To achieve high β values, the base should be thin (W small) and
lightly doped, and the emitter heavily doped.
iB = iB1 + iB2
Dp NA W 1 W 2 vBE /VT
= IS ( + )e
Dn ND Lp 2 Dn τ b
µ ¶
Dp NA W 1 W2
= + iC
Dn ND Lp 2 Dn τ b
1
= × iC (7.7)
β
• Emitter current iE
— From KCL, the iE and iC can be related as follows:
iE = iB + iC
1
= iC + iC
β
1+β
= × iC (7.8)
β
1
= × iC
α
1
= × Is evBE /VT
α
∗ α = β/ (1 + β) ' 1 is a constant for a given transistor.
101
∗ Small change in α corresponds to large changes in β.

• Recapitulation
— Configuration
— Relationship between iC , iB , and iE .
∗ iC = β × iB .
· β (normally in the range 50∼200) is a constant for a given transistor.
∗ iC = α × iE .
· α (β/ (1 + β) - 1) is a constant for a given transistor.
∗ iB , iC , and iE are all controlled by vBE .
iC = IS evBE /VT
1
iB = IS evBE /VT (7.9)
β
1
iE = IS evBE /VT
α
— Figure 7.9 depicts the large signal equivalent model of the NPN transistor.
∗ In Figure 7.9 (a), iC behaves as a voltage (vBE ) controlled current source.
1
iC + iB = iE = iC (7.10)
α
∗ In Figure 7.9 (b), iC behaves as a current (iE ) controlled current source.
iC + iB = iE
⇒ αiE + iB = iE (7.11)
∗ The diode DE represents the forward base-emitter junction.
7.2.2 Reverse Active Mode

• The α and β in the reverse active mode are much lower than those in the forward
active mode.
— αR is in the range of 0.01 to 0.5.
∗ In forward active mode, the collector virtually surrounds the emitter re-
gion.
· Electrons injected into the thin base region are mostly captured by the
collector.
∗ In reverse active mode, the emitter virtually surrounds the collector re-
gion.
· Electrons injected into the thin base region are partly captured by the
102
Figure 7.9: Large signal equivalent model of the NPN BJT operating in the forward
active mode.
Figure 7.10: Large signal equivalent model of the NPN BJT operating in the reverse
active mode.
collector.
— β R is in the range of 0.01 to 1.
• CBJ has a much larger area than EBJ.
— The diode DC denotes the forward base-collector junction.
— The diode DC has larger scale current (ISC ) than DE does.
∗ The diode DC has lower voltage drop when forward biased.
7.2.3 Ebers-Moll (EM) Model

• A composite model that can be used to predict the operations of the BJT in all
possible modes.
— Combine Figure 7.9 (b) and Figure 7.10.
• α and β
103
Figure 7.11: Ebers-Moll model of the NPN transistor.
— αF and β F denotes the parameters in forward active mode.

— αR and β R denotes the parameters in reverse active mode.
• Equivalent saturation current ISE and ISC
— From Figure 7.9 (b) and Figure 7.10, ISE and ISC are the equivalent saturation currents
at the EBJ and CBJ, respectively.
1
ISE = IS
αF
1
ISC = IS (7.12)
αR
⇒ αF ISE = αR ISC = IS
• iC , iB , and iE in the EM model
iE = iDE − αR iDC
iC = −iDC + αF iDE (7.13)
iB = (1 − αF )iDE + (1 − αR )iDC
¡ ¢
— iDE = ISE evBE /VT − 1 .
¡ ¢
— iDC = ISC evBC /VT − 1 .
104
• By Eq. (7.12),
IS vBE /VT
iE = (e − 1) − IS (evBC /VT − 1)
αF
IS vBC /VT
iC = IS (evBE /VT − 1) − (e − 1) (7.14)
αR
IS vBE /VT IS vBC /VT
iB = (e − 1) + (e − 1)
βF βR
— β F = αF /(1 − αF ).
— β R = αR /(1 − αR ).
7.2.4 Saturation Mode

• CBJ is in forward bias, i.e., vBC > 0.4V.
— CBJ has larger junction area than EBJ.
∗ CBJ has larger saturation current IS and lower cut-in voltage than EBJ.
∗ In forward bias,
· The voltage drop across CBJ is 0.4V.
· The voltage drop across EBJ is 0.7V.
— As vBC is increased, iC will be decreased and eventually reach zero.
IS vBC /VT
iC ' IS evBE /VT − e (7.15)
αR
Figure 7.12: Concentration profile of the minority carriers in the base region of an NPN
transistor.
105
Sec 7.3. Operations of PNP Transistor
Figure 7.13: Current flow in a PNP transistor biased to operate in the active mode.
7.3 Operations of PNP Transistor

7.3.1 Active Mode
• Current in a PNP transistor is mainly conducted by holes.
• Emitter-Base Junction
— Forward bias, vEB > 0.
— Holes in the emitter region are injected into the base causing a current iE1 .
— Electrons in the base region are injected into the emitter region causing a cur-
rent iE2 .
∗ Generally, iE1 >> iE2 .
iE (t) = iE1 + iE2 (7.16)
• Base region
— Tapered concentration causes the holes to diffuse through the base region to-
ward the collector.
∗ Some of the holes may combine with the electrons.
∗ The recombination process is quite small due to lightly doped and thin
base region.
• Collector-Base Junction
— Reverse bias, vBC > 0.
— The holes near the collector side are swept into the collector region causing
zero concentration at the collector side.
• Collector current, iC .
— Most of the diffusing holes will reach collector region.
∗ Only a very small percentage of holes are recombined with the electrons
106
Figure 7.14: Large signal equivalent model of the PNP BJT operating in the forward
active mode.
in the base region.

— As long as vBC > 0, iC is independent of vBC .
∗ The holes that reach the collector side of the base region will be swept into
the collector as collector current.
• Base current iB
— iB is composed of two currents.
∗ The electrons injected from the base region into the emitter region.
∗ The electrons that have to be supplied by the external circuit due to the
recombination.
• Emitter current iE
— From KCL, the iE and iC can be related as follows:
iE = iB + iC
1
= iC + iC
β
1+β
= × iC (7.17)
β
1
= × iC
α
1
= × Is evEB /VT
α
∗ α = β/ (1 + β) ' 1 is a constant for a given transistor.

∗ Small change in α corresponds to large changes in β.
• Figure 7.14 depicts the large signal equivalent model of the PNP transistor.
107
Sec 7.3. Operations of PNP Transistor
Figure 7.15: Ebers-Moll model of the PNP transistor.
• Figure 7.15 shows the EM model of the NPN transistor.
7.3.2 Reverse Active Mode

• Similar to NPN transistor.
7.3.3 Saturation Mode

• Similar to NPN transistor.
7.3.4 Summary of the iC , iB , iE Relationships in Active Mode

• NPN transistor
ic = Is evBE /VT
Is vBE /VT
iB = e (7.18)
β
Is vBE /VT
iE = e
α
108
Figure 7.16: The iC − vCB characteristics of an NPN transistor.
iC = αiE
iC = βiB
iE
iB = (1 − α)iE = (7.19)
1+β
iE = (1 + β)iB
• PNP transistor.
— The vBE in Eq. (7.18) is replaced by vEB .
7.4 The i − v Characteristics of NPN Transistor

7.4.1 Common Base (iC − vCB )
• Figure 7.16 depicts the iC versus vCB for various iE , which is also known as the
common-base characteristics.
— Input port: emitter and base terminals.
∗ Input current iE .
— Output port: collector and base terminals.
∗ Output current iC .
— The base terminal serves as a common terminal to both input port and output
port.
• Active Region (vCB ≥ −0.4V )
— iC depends slightly on vCB and shows a small positive slope.
109
Sec 7.4. The i − v Characteristics of NPN Transistor
— iC shows a rapid increase, known as breakdown phenomenon, for a relatively

large value of vCB .
— Each iC − vCB curve intersects the vertical axis at a current level equal to αIE .
∗ Total or large-signal α (common-base current gain)
· α = iC /iE , where iC and iE denote the total collector and emitter
currents, respectively.
∗ Incremental or small-signal α
· α = ∆iC /∆iE .
∗ Usually, the values of incremental and total α differs slightly.
• Saturation Region (vCB < −0.4V )
— CBJ is forward biased.
— The EM model can be used to determine the vCB at which iC is zero.
7.4.2 Common Emitter (iC − vCE )

• Figure 7.17 depicts the iC versus vCE for various vBE , which is also known as the
common-emitter characteristics.
— Input port: base and emitter terminals.
∗ Input current iB .
— Output port: collector and emitter terminals.
∗ Output current iC .
— The emitter terminal serves as a common terminal to both input port and
output port.
• Active Region (vCB ≥ −0.4V )
— iC increases as the vCE is increased, which is known as Early Effect.
∗ At a given vBE , increasing vCE increases the width of the depletion region
of the CBJ.
∗ The effective base width W is decreased.
∗ As shown in Eq. (7.4), IS is inversely proportional to the base width W .
— When extrapolated, the characteristics line meet at point on the negative vCE
(normally in the range of 50V to 100V), −VA .
∗ VA is a constant for a given transistor.
• Large signal equivalent circuit model in active mode.
— The linear dependency of iC on vCE can be formulized as follows:
vCE vCE
iC = IS evBE /VT (1 + ) = IC (1 + ) (7.20)
VA VA
— The output resistance looking into the collector-emitter terminals.

∗ Inversely proportional to the collector current IC without considering Early
effect.
110
Figure 7.17: The iC − vCE characteristics of the BJT.
∗ Controlled by vBE .
∆vCE
∆iC = IS evBE /VT ( ) (7.21)
VA
∆vCE VA
⇒ ro = =
∆iC IC
— Figure 7.18 depicts the large signal equivalent circuit model of an NPN BJT
in the active mode and with the common emitter configuration.
∗ Figure 7.18 (a), voltage vBE controls the collector current source.
∗ Figure 7.18 (b), the base current iB controls the collector current source
β × iB .
— Large signal or DC β
∗ The ratio of total current in the collector to the total current in the base,
which represents the ideal current gain (where ro is not present) of the
common-emitter configuration.
iC
β dc = |v =constant (7.22)
iB CE
∗ β is also known as the common-emitter current gain.

— Incremental or AC β
∗ Short-circuit common-emitter current gain.
∗ AC β and DC β differ approximately 10% to 20%.
∆iC
β ac = |v =constant (7.23)
∆iB CE
111
Figure 7.18: Large signal equivalent circuit model of an NPN BJT operating in the
active mode and with common-emitter configuration.
Figure 7.19: An expanded view of the common-emitter characteristic in the saturation

region.
• Saturation Region (vCB < −0.4V )

— Figure 7.19 depicts an expanded view of the common-emitter characteristic in
the saturation region.
— Analytical expressions of iC − vCE using EM model.
∗ vBE = vCE + vCB .
IS vBC /VT
iC ' IS (evBE /VT ) − (e )
αR
IS vBE /VT IS vBC /VT
IB ' (e )+ (e ) (7.24)
βF βR
Ã 1
!
evCE /VT − αR
iC ' (β F IB ) βF
(7.25)
evCE /VT − βR
112
Figure 7.20: Plot of normalized iC versus vCE for an NPN transistor with β F = 100 and
αR = 0.1.
• Large signal equivalent circuit model in saturation mode.

— The saturation transistor exhibits a low collector-to-emitter resistance RCEsat .
∂vCE
RCEsat = |i =I ,i =I ' 1/10β F IB (7.26)
∂iC B B C C
— At the collector side, the transistor is modeled as a resistance RCEsat in series

with a battery vCEof f as shown in Figure 7.21 (c).
∗ VCEof f is typically around 0.1V .
∗ VCEsat is typically around 0.1 ∼ 0.3V .
VCEsat = VCEof f + ICsat RCEsat (7.27)
— For many applications, the even simpler model shown in Figure 7.21 is used.
113
Figure 7.21: Equivalent circuit representation of the saturated transistor.
114
8
Comparisons of BJT and MOSFET
8.1 NMOS and NPN Transistors

• Circuit symbols and physical structures
— NMOS has symmetric structure for drain and source.
— NPN has asymmetric structure for collector and emitter.
• Current
— NMOS: current flows from drain to source.
— NPN: current flows from collector to emitter.
• Voltage
— NMOS: vD > vS , vG > vS .
— NPN: vB > vE , vC > vE .
NMOS NPN
NMOS NPN
115
Sec 8.1. NMOS and NPN Transistors
• iD − vDS (common source) v.s. iC − vCE (common emitter)
NMOS
NPN
8.1.1 NMOS Triode v.s. NPN Saturation

• NMOS Triode iD − vDS v.s. NPN Saturation iC − vCE
NMOS NPN
116
Lecture 8. Comparisons of BJT and MOSFET
• NMOS
— The two terminals drain and source act as a resistor controlled by (vGS − Vt ) .
• NPN
— The two terminals collector and emitter act as a resistor controlled by IB (or
vBE ).
NMOS Triode NPN Saturation

Bias vGS > Vt , vDS < vGS − Vt vBE > 0.5, vCE < vBE − 0.4 ' 0.3
£ ¤
i−v iD = kn0 W (vGS − Vt )vDS − 12 vDS
2
iC ' IS evBE /VT − αISR evBC /VT
£ L0 W ¤−1 vDS
ro rDS ' kn L (vGS − Vt ) ' iD rCE ' 1/10β F IB
• Equivalent large signal model
NMOS NPN
8.1.2 NMOS Saturation v.s. NPN Forward Active

• NMOS
— The two terminals drain and source act as a current source controlled by (vGS − Vt ) .
• NPN
— The two terminals collector and emitter act as a current source controlled by
IB (or vBE ).
NMOS Saturation NPN Active

Bias vGS > Vt , vDS > vGS − Vt vBE > 0.5, vCE > vBE − 0.4 ' 0.3
1 0 W
i−v ID = k (vGS
2 n L
− Vt )2 IC ' IS evBE /VT = βiB
Early Effect iD = ID (1 + λvDS ), λ = 1/VA iC = IC (1 + λvCE ), λ = 1/VA
ro rDS = VA /ID rCE ' VA /IC
117
Sec 8.2. PMOS and PNP Transistors
NMOS NPN
8.1.3 NMOS Cut-off v.s. NPN Cut-off

• NMOS
— VGS < Vt .
• NPN
— VBE < 0.5, VBC < 0.4.
8.2 PMOS and PNP Transistors

• Circuit symbols and physical structures
— PMOS has symmetric structure for drain and source.
— PNP has asymmetric structure for collector and emitter.
• Current
— PMOS: current flows from source to drain.
— PNP: current flows from emitter to collector.
• Voltage
— PMOS: vD < vS , vG < vS .
— PNP: vB < vE , vC < vE .
PMOS PNP
• iD − vDS (common source) v.s. iC − vCE (common emitter)
118
PMOS [vDS → vSD , (vGS − Vt ) → (vSG − |Vt |) , −VA → − |VA |]
PNP [vCE → vEC , vBE → vEB , −VA → − |VA |]
8.2.1 PMOS Triode v.s. PNP Saturation

• NMOS Triode iD − vSD v.s. NPN Saturation iC − vEC
PMOS [vDS → vSD , (vGS − Vt ) → (vSG − |Vt |)] PNP [vCE → vEC , vBE → vEB ]
• PMOS
— The two terminals source and drain acts as a resistor controlled by vSG − |Vt | .
119
Sec 8.2. PMOS and PNP Transistors
• NPN
— The two terminals emitter and collector acts as a resistor controlled by IB .
PMOS Triode PNP Saturation

Bias vSG > |Vt |, vSD < vSG − |Vt | vEB > 0.5, vEC < vEB − 0.4 ' 0.3
£ ¤
i−v iD = kp L (vSG − |Vt |)vSD − 2 vSD iC ' IS evEB /VT − αISR evCB /VT
0W 1 2
£ ¤−1 vSD
ro rSD ' kp0 W L
(vSG − |Vt |) ' iD rEC ' 1/10β F IB
PMOS PNP
8.2.2 PMOS Saturation v.s. PNP Forward Active

• NMOS
— The two terminals source and drain acts as a current source controlled by vSG −
|Vt | .
• PNP
— The two terminals emitter and collector acts as a current source controlled by
IB (or vEB ).
PMOS Saturation PNP Active

Bias vSG > |Vt |, vSD > vSG − |Vt | vEB > 0.5, vEC > vEB − 0.4 ' 0.3
i−v ID = 12 kp0 W
L
(vSG − |Vt |)2 IC ' IS evEB /VT = βiB
Early Effect iD = ID (1 + |λ| vSD ), |λ| = 1/ |VA | iC = IC (1 + |λ| vEC ), |λ| = 1/ |VA |
ro rDS = |VA | /ID rCE ' |VA | /IC
120
PMOS PNP
8.2.3 PMOS Cut-off v.s. PNP Cut-off

• PMOS
— VSG < |Vt | .
• PNP
— VEB < 0.5, VCB < 0.4.
121

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Lecture Notes on Basic Electronics

for Students in Computer Science

John Kar-kin Zao and Wen-Hsiao Peng

I System and Circuit Analysis 2

2 Signals and Systems 3

3.4.1 Equivalent Circuits of One-Port Networks . . . . . . . . . . . . . . 23

II Devices — Diode, BJT, MOSFETs 49

6 MOS Field-Eﬀect Transistors (MOSFETs) 81

7 Bipolar Junction Transistor (BJT) 95

8 Comparisons of BJT and MOSFET 115

1.1 Goal of This Course

1.2 Content of This Course

1.3 Relationship with Other Disciplines

System and Circuit Analysis

2.1 Basic Concepts

Table 2.1: Signals and Systems in Time and Frequency Domains.

Figure 2.1: System from engineering perspective.

Inputs LTI Systems Outputs

2.2 Types of Systems

Input x(t) Continuous-Time Output y(t)

Figure 2.2: Continuous-time systems.

Input x[n] Discrete-Time Output y[n]

Figure 2.3: Discrete-time systems.

Input x(t) Output y(t)

Figure 2.4: Digital system.

∗ Inputs/outputs of the systems are functions defined at discrete time.

2.3 Axiomatic Properties of Systems

Figure 2.5: Inverse system.

2.4 Time-Domain Analysis

• Inputs/outputs are time functions (waveforms).

2.4.1 Impulse Response

• Direc-Delta function δ(t).

Figure 2.6: Direc-Delta function

— Signal sampling using Direc-Delta function.

Figure 2.7: Sampling using Direc-Delta function.

— Signal reconstruction: any real time-functions can be represented by using the

Figure 2.8: A time function represented by a set of delta functions.

2.4.2 Step Response

2.4.3 Sinusoidal Response

x(t) = cos(2t) with ω = 2πf (2.10)

Figure 2.9: Continuous time convolution operation.

Figure 2.10: Discrete time convolution operation.

Figure 2.11: Sinusoidal waveform.

y(t) = x(t) ∗ h(t)

— Complex exponential function ejωt is the eigenfunction of any LTI systems.

2.4.4 Initial Value/Driving Free/Natural Response

2.4.5 Transient Response

2.4.6 Steady-State Response

yS (t) = y(t) − yT (t). (2.15)

2.5 Frequency-Domain Analysis

• Input X and Output Y are complex functions of angular frequency.

• x(t) = <{Xejωt } = K cos(ωt + φ).

2.5.2 Spectrum and Fourier Transform

— The principle of Inverse Fourier Transform.

— X(ω) is a complex function of angular frequency ω, which expresses the values

X(ω) = kX(ω)k ej]X(ω) . (2.17)

∗ kX(ω)k is called magnitude spectrum, specifying the magnitude for diﬀer-

Definition 2.6 Correspondingly, the Inverse Fourier Transform is as follows:

2.5.3 System Transfer Function Hs (ω)

Input time function System Output time function

Figure 2.13: Relationship between time-domain analysis and frequency-domain analysis.

— It is also known as the frequency response of a LTI system.